 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 2SJ450 Silicon P Channel MOS FET Application High speed power switching UPAK Features * * * * Low on-resistance. Low drive power High speed switching 2.5V gate drive device. G D 2 3 2 1 4 1 3 S 1. Gate 2. Drain 3. Source 4. Drain Table 1 Absolute Maximum Ratings (Ta = 25C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Drain peak current Channel dissipation Channel temperature Storage temperature Symbol VDSS VGSS ID ID(pulse)* IDR Pch** Tch Tstg Ratings -60 20 -1 -2 -1 1 150 -55 to +150 Unit V V A A A W C C -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- * PW 100 s, duty cycle 10 % ** When using aluminium ceramic board (12.5 x 20 x 70 mm) 2SJ450 Table 2 Electrical Characteristics (Ta = 25C) Item Drain to source breakdown voltage Gate to source breakdown voltage Zero gate voltage drain current Gate to source leak current Gate to source cutoff voltage Static drain to source on state resistance Static drain to source on state resistance Fowerd transfer admittance Symbol V(BR)DSS V(BR)GSS IDSS IGSS VGS(off) RDS(on) RDS(on) |yfs| Ciss Coss Crss td(on) tr td(off) tf VDF trr Min -60 Typ -- Max -- Unit V Test conditions ID = -10 mA, VGS = 0 IG = 100 A, VDS = 0 VDS = -50 V, VGS = 0 VGS = 16 V, VDS = 0 VDS = -10 V, ID = -1 mA -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- 20 -- -- V -------------------------------------------------------------------------------------- -- -- -0.5 -- -- -- -- 0.85 -50 10 -1.5 1.2 A A V -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- ID = -0.5 A VGS = -4 V * ID = -0.3 A VGS = -2.5 V * ID = -0.5 A VDS = -10 V VDS = -10 V VGS = 0 f = 1 MHz VGS = -10 V, ID = -0.5 A RL = 60 -------------------------------------------------------------------------------------- -- 1.1 1.9 -------------------------------------------------------------------------------------- 0.6 1.0 -- S -------------------------------------------------------------------------------------- Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Body-drain diode forward voltage Body-drain diode reverse recovery time * Pulse Test Marking is "UY". -- -- -- -- -- -- -- -- 150 72 24 6 9 50 35 -0.9 -- -- -- -- -- -- -- -- pF pF pF s s s s V IF = -1 A, VGS = 0 IF = -1 A, VGS = 0 diF / dt = 50A / s ---------------------------------------------------------------- ---------------------------------------------------------------- -------------------------------------------------------------------------------------- ---------------------------------------------------------------- ---------------------------------------------------------------- ---------------------------------------------------------------- -------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------- -- 100 -- ns -------------------------------------------------------------------------------------- 2 2SJ450 Power vs. Temperature Derating 2.0 Pch (W) Test Condition : When using the aliminium Ceramic board (12.5 x 20 x 70 mm) 1.5 Channel Dissipation 1.0 0.5 0 50 100 150 Ta (C) 200 Ambient Temperature Package Dimensions Unit : mm * UPAK 4.5 0.1 0.4 1.8 max 1.5 0.1 0.44 max f1 1.5 1.5 3.0 0.8 min 0.53 max 0.48 max 1 2 3 2.5 0.1 4.25 max 4 0.44 max Hitachi Code EIAJ JEDEC UPAK SC-62 UPAK |
Price & Availability of 2SJ450
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |