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936&5HY$
PCI Bus Target Interface
Datasheet Revision 1.1
(c)V3 Semiconductor Corp.
V3 Semiconductor makes no warranties for the use of its products. V3 does not assume any liability for errors which may appear in this document, however, we will attempt to notify customers of such errors. V3 Semiconductor retains the right to make changes to either the documentation, specification or component without notice. Please verify with V3 Semiconductor to be sure you have the latest specifications before finalizing a design.
(c) V 3 S e m ic o n d u c to r 1 9 9 7 T h e E m b e d d e d C h ip s e t C o m p a n y is a t ra d e m a r k o f V 3 S e m ic o n d u c to r C o r p . A l l o t h e r t r a d e m a r k s a r e t h e p r o p e r t y o f t h e ir re s p e c ti v e o w n e r s .
V300PSC Rev. A0
PCI BUS TARGET INTERFACE
* A general purpose PCI bus target interface * Multiplexed and de-multiplexed 32-, 16-, or bit local bus interface * Fully compliant with PCI 2.1 specification * Large, 288-byte FIFOs using V3's unique DYNAMIC BANDWIDTH ALLOCATIONTM architecture * On-the-fly byte order (endian) conversion including automatic endian detection The V300PSC provides the highest performance, most flexible, and most economical method to connect a general purpose 32-, 16-, 8bit local bus to the PCI bus. V3 Semiconductor's simple to use local bus interface makes the V300PSC the fastest route to adding PCI to your system. The V300PSC may be used in systems without a CPU for a generic PCI target interface. The V300PSC supports independent interface speeds allowing the PCI bus to run at the full 33MHz frequency, regardless of local bus clock rate. The V300PSC uses the unique DYNAMIC BANDWIDTH ALLOCATIONTM FIFOs to decouple the local and PCI bus, while dramatically improving the overall throughput of the system. 8-
* Address space remapping * Mailboxes w/doorbell interrupts * Flexible PCI and local interrupt management * Serial EEPROM configuration interface * 33MHz local bus with independent PCI bus operation up to 33MHz * Low cost 160-pin EIAJ PQFP package
A PCI master can gain access to the local bus through two programmable address apertures with address remapping capabilities, and on-thefly byte order conversion. To support existing DOS I/O devices a special decoder mode allows up to 3 I/O regions (and one memory region below 1MB) to be decoded. The V300PSC's interrupt control mechanism is very flexible and allows interrupts from multiple sources on the local bus to share a single PCI interrupt. The V300PSC operates up to 33MHz, and is packaged in a low cost, 160-pin EIAJ Plastic Quad Flat Pack (PQFP) package.
GENERIC 32-, 16-, 8-BIT TARGET APPLICATION
V96BMC V96SSC MEMORY
D R A M
ROM
TYPICAL APPLICATION
V300PSC PCI to LOCAL BUS BRIDGE PCI SLOT or EDGE CONNECTOR
PCI PERIPHERAL
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC Data Sheet Rev 1.1
1
V3 Semiconductor reserves the right to change the specifications of this product without notice. V300PSC, V96SSC and V96BMC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.
V300PSC
This document contains the product codes, pinouts, package mechanical information, DC characteristics, and AC characteristics for the V300PSC. Detailed functional information is contained in the V300PSC User's Manual.
V3 Semiconductor retains the rights to change documentation, specifications, or device functionality at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design.
1.0 Product Codes
Table 1: Product Codes
Product Code V300PSC-33 REV A0 Local Bus Type 32-,16-,8- bit multiplexed / demultiplexed Package 160-pin EIAJ PQFP Frequency 33MHz
2.0 Pin Description and Pinout
Table 2 below lists the pin types found on the V300PSC. Table 3 and 4 describe modes and function of each pin on the V300PSC. Table 5 and Table 6 list the pins by pin number. Figure 1 and Figure 2 show the pinout for the 160-pin EIAJ PQFP package and Figure 3 shows the mechanical dimensions of the package.
Table 2: Pin Types
Pin Type PCI I PCI O PCI I/O PCI I/OD I/O4 I O4 PCI input only pin. PCI output only pin. PCI tri-state I/O pin. PCI input with open drain output. TTL I/O pin with 4mA output drive. TTL input only pin. TTL output pin with 4mA output drive. Description
Table 3: RESET State for Configuration and Test Mode Pins
PIN# Connection for de-multiplexed bus Connection for multiplexed bus 134 (ALE) Pull-Up Pull-Down 135 (BTERM) Pull-Up Pull-Up 153 Pull-Up Pull-Down
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V300PSC Data Sheet Rev 1.1
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC
Table 4: Signal Descriptions
PCI Bus Interface Signal AD[31:0] C/BE[3:0] PAR FRAME Type PCI I/O PCI I PCI I/O PCI I Ra Z Z Z Z Description Address and data, multiplexed on the same pins. Bus Command and Byte Enables, multiplexed on the same pins. Parity represents even parity across AD[31:0] and C/BE[3:0]. Cycle Frame indicates the beginning and burst length of an access. Initiator Ready indicates the master agent is ready to complete the current data phase of the transaction. Target Ready indicates the target agent's (V300PSC) ability to complete the current data phase of the transaction. Stop indicates the V300PSC is requesting the master to stop the current transaction (retry or disconnect). Device Select, indicates the V300PSC device has decoded its address as the target of the current access. Initialization Device Select is used as a chip select during configuration read and write transactions. It must be driven high in order to access the chip's internal configuration space. PCLK provides timing for all transactions on the PCI bus. Asserted low to bring all internal operations to a reset state. Parity Error is used to report data parity errors during all PCI transactions except a Special Cycle. System Error is used to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. Level-sensitive interrupt requests may be received or generated.
IRDY
PCI I
Z
TRDY
PCI O
Z
STOP
PCI O
Z
DEVSEL
PCI O
Z
IDSEL
PCI I
Z
PCLK PRST PERR
PCI I PCI I PCI I/O
Z Z Z
SERR
PCI I/OD PCI I/OD
Z
INT[A:D]
Z
Serial EEPROM Interface Signal SCL/LPERR SDA Type O4 I/O4 R X X Description EEPROM clock. Local parity error. EEPROM data.
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC Data Sheet Rev 1.1
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V300PSC
Table 4: Signal Descriptions (cont'd)
Local Bus Interface Signal LAD[31:0] LA[5:2] LD[31:0] LA[31:2] BE[3:0] W/R ALE ADS RDYRCV READY HOLD HOLDA LPAR[3:0] BLAST BTERM LINT LRST LCLK Type I/O4 O4 I/O4 I/O4 I/O4 I/O4 I/O4 I/O4 I/O4 O4 I I/O4 I/O4 I/O4 O4 I/O4 I Z Z Z H L/Z R Z Z Z Z Z Z Z Z Z Description Local address and multiplexed data bus (multiplexed mode). Lower local address bus. Generated during local bus master cycles and incremented during a burst (multiplexed mode). Local data bus (de-multiplexed mode). Local address bus (de-multiplexed mode). Local bus byte enables. Write/Read. Address Latch Enable: used to latch the address during the address phase (multiplexed mode). Asserted low to indicate the beginning of a bus cycle. Local Bus data ready. Local bus hold request: asserted by the P3PSC to initiate a local bus master cycle. Local bus hold acknowledge. Local bus parity. Burst last. Bus Time-out. Burst terminate. Local interrupt request. Local bus RESET signal. Local bus clock.
L
Power and Ground Signals Signal VCC GND Type R Description POWER pins for connection to the board's VCC plane. GROUND pins for connection to the board's GND plane.
a. R indicates state during reset.
4
V300PSC Data Sheet Rev 1.1
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC
Table 5: Pin Assignments (multiplexed bus)
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Signal VCC INTD PRST PCLK '1' NC AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3 IDSEL AD23 AD22 VCC GND AD21 AD20 AD19 AD18 AD17 PIN # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Signal VCC AD14 AD13 AD12 AD11 AD10 AD9 AD8 C/BE0 VCC GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VCC GND LAD0 NC LAD1 NC LAD2 PIN # 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 Signal VCC NC LAD8 NC LAD9 NC LAD10 NC LAD11 NC LAD12 NC LAD13 NC LAD14 NC LAD15 NC LAD16 VCC GND NC LAD17 NC LAD18 NC PIN # 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 Signal VCC NC LAD25 LA5 LAD26 LA4 LAD27 LA3 LAD28 LA2 LAD29 LAD30 LAD31 ALE BTERM RDYRCV HOLD HOLDA ADS VCC GND LCLK GND VCC BE3 BE2
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC Data Sheet Rev 1.1
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V300PSC
Table 5: Pin Assignments (multiplexed bus) (cont'd)
PIN # 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal AD16 C/BE2 FRAME GND IRDY TRDY DEVSEL STOP PERR SERR PAR C/BE1 AD15 GND PIN # 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Signal NC LAD3 NC LAD4 NC LAD5 NC LAD6 NC LAD7 NC LPAR0 LPAR1 GND PIN # 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Signal LAD19 NC LAD20 NC LAD21 NC LAD22 NC LAD23 NC LPAR2 LPAR3 LAD24 GND PIN # 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Signal BE1 BE0 BLAST W/R '1' LRST '0' LINT SDA SCL/ LPERR INTA INTB INTC GND
Table 6: Pin Assignments (de-multiplexed bus)
PIN # 1 2 3 4 5 6 7 8 Signal VCC INTD PRST PCLK '1' NC AD31 AD30 PIN # 41 42 43 44 45 46 47 48 Signal VCC AD14 AD13 AD12 AD11 AD10 AD9 AD8 PIN # 81 82 83 84 85 86 87 88 Signal VCC LA23 LD8 LA22 LD9 LA21 LD10 LA20 PIN # 121 122 123 124 125 126 127 128 Signal VCC LA6 LD25 LA5 LD26 LA4 LD27 LA3
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V300PSC Data Sheet Rev 1.1
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC
Table 6: Pin Assignments (de-multiplexed bus) (cont'd)
PIN # 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3 IDSEL AD23 AD22 VCC GND AD21 AD20 AD19 AD18 AD17 AD16 C/BE2 FRAME GND IRDY TRDY DEVSEL STOP PERR PIN # 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal C/BE0 VCC GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VCC GND LD0 LA31 LD1 LA30 LD2 LA29 LD3 LA28 LD4 LA27 LD5 LA26 LD6 LA25 PIN # 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 Signal LD11 LA19 LD12 LA18 LD13 LA17 LD14 LA16 LD15 LA15 LD16 VCC GND LA14 LD17 LA13 LD18 LA12 LD19 LA11 LD20 LA10 LD21 LA9 LD22 LA8 LD23 PIN # 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 Signal LD28 LA2 LD29 LD30 LD31 '1' BTERM READY HOLD HOLDA ADS VCC GND LCLK GND VCC BE3 BE2 BE1 BE0 BLAST W/R '1' LRST '1' LINT SDA
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC Data Sheet Rev 1.1
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V300PSC
Table 6: Pin Assignments (de-multiplexed bus) (cont'd)
PIN # 36 37 38 39 40 Signal SERR PAR C/BE1 AD15 GND PIN # 76 77 78 79 80 Signal LD7 LA24 LPAR0 LPAR1 GND PIN # 116 117 118 119 120 Signal LA7 LPAR2 LPAR3 LD24 GND PIN # 156 157 158 159 160 Signal SCL/ LPERR INTA INTB INTC GND
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V300PSC Data Sheet Rev 1.1
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC
Figure 1: Multiplexed Mode Pinout for 160-pin EIAJ PQFP (top view)
GND LAD24 LPAR3 LPAR2 NC LAD23 NC LAD22 NC LAD21 NC LAD20 NC LAD19 NC LAD18 NC LAD17 NC GND Vcc LAD16 NC LAD15 NC LAD14 NC LAD13 NC LAD12 NC LAD11 NC LAD10 NC LAD9 NC LAD8 NC Vcc Vcc NC LAD25 LA5 LAD26 LA4 LAD27 LA3 LAD28 LA2 LAD29 LAD30 LAD31 ALE BTERM# RDYRCV# HOLD HOLDA ADS# Vcc GND LCLK GND Vcc BE3# BE2# BE1# BE0# BLAST# W/R# '1' LRST# '0' LINT# SDA SCL/LPERR# INTA# INTB# INTC# GND 120 121 81 80
V300PSC
160 1 41 40
GND LPAR1 LPAR0 NC LAD7 NC LAD6 NC LAD5 NC LAD4 NC LAD3 NC LAD2 NC LAD1 NC LAD0 GND Vcc AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND Vcc C/BE0# AD8 AD9 AD10 AD11 AD12 AD13 AD14 Vcc
V300PSC require pull-down resistor on ALE and pull-up resistor on BTERM to ensure proper multiplexed mode operation.
Vcc INTD# PRST# PCLK '1' N/C AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 Vcc GND AD21 AD20 AD19 AD18 AD17 AD16 C/BE2# FRAME# GND IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR C/BE1# AD15 GND
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC Data Sheet Rev 1.1
9
V300PSC
Figure 2: De-Multiplexed Mode Pinout for 160-pin EIAJ PQFP (top view)
GND LD24 LPAR3 LPAR2 LA7 LD23 LA8 LD22 LA9 LD21 LA10 LD20 LA11 LD19 LA12 LD18 LA13 LD17 LA14 GND Vcc LD16 LA15 LD15 LA16 LD14 LA17 LD13 LA18 LD12 LA19 LD11 LA20 LD10 LA21 LD9 LA22 LD8 LA23 Vcc Vcc LA6 LD25 LA5 LD26 LA4 LD27 LA3 LD28 LA2 LD29 LD30 LD31 '1' BTERM# READY# HOLD HOLDA ADS# Vcc GND LCLK GND Vcc BE3# BE2# BE1# BE0# BLAST# W/R# '1' LRST# '1' LINT# SDA SCL/LPERR# INTA# INTB# INTC# GND 120 121 81 80
V300PSC
160 1 41 40
GND LPAR1 LPAR0 LA24 LD7 LA25 LD6 LA26 LD5 LA27 LD4 LA28 LD3 LA29 LD2 LA30 LD1 LA31 LD0 GND Vcc AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND Vcc C/BE0# AD8 AD9 AD10 AD11 AD12 AD13 AD14 Vcc
V300PSC require pull-up resistors on ALE and BTERM to ensure proper de-multiplexed mode operation.
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Vcc INTD# PRST# PCLK '1' N/C AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 Vcc GND AD21 AD20 AD19 AD18 AD17 AD16 C/BE2# FRAME# GND IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR C/BE1# AD15 GND
V300PSC Data Sheet Rev 1.1 Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC
Figure 3: 160-pin EIAJ PQFP mechanical details
Unit of Measurement = millimeters
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC Data Sheet Rev 1.1
11
V300PSC 3.0 DC Specifications
The DC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.1, Section 4.2.1.1. For more information on the PCI DC specifications, see the PCI Specification.
Table 7: Absolute Maximum Ratings
Symbol VCC VIN IIN TSTG Parameter Supply voltage DC input voltage DC input current Storage temperature range Value -0.3 to +7 -0.3 to VCC+0.3 10 -40 to +125 Units V V mA C
Table 8: Guaranteed Operating Conditions
Symbol VCC TA Parameter Supply voltage Ambient temperature range Value 4.75 to 5.25 0 to 70 Units V C
3.1
PCI Bus DC Specifications Table 9: PCI Bus Signals DC Operating Specifications
Symbol VIH VIL IIH IIL VOH VOL CIN CCLK CIDSEL LPIN
Parameter Input high voltage Input low voltage Input high leakage current Input low leakage current Output high voltage Output low voltage Input pin capacitance PCLK pin capacitance IDSEL pin capacitance Pin inductance
Condition
Min 2.0 -0.5
Max VCC+0.5 0.8 70 -70
Units V V A A V
Notes
VIN = 2.7V VIN = 0.5V IOUT = -2mA IOUT = 3mA, 6mA 2.4
1 1
0.55 10 5 12 8 20
V pF pF pF nH
2 3
4
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V300PSC Data Sheet Rev 1.1
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC
Notes: 1. Input leakage currents include high impedance output leakage for all bi-directional buffers with tri-state outputs. 2. Signals without pullup resistors have greater than 3mA low output current. Signals requiring pull resistors have greater than 6mA output current. The latter include FRAME, TRDY, IRDY, STOP, SERR, PERR. 3. Absolute maximum pin capacitance for a PCI unit is 10pF (except for CLK). 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
3.2
Local Bus DC Specifications
Table 10: Local Bus Signals DC Operating Specifications
Symbol VIL VIH IIL IIH VOL4 VOH4 IOZL IOZH Description Low level input voltage High level input voltage Low level input current High level input current Low level output voltage for 4 mA outputs and I/O pins High level output voltage for 4 mA outputs and I/O pins Low level float input leakage High level float input leakage Conditions VCC = 4.75V VCC = 5.25V VIN=GND, VCC=5.25V VIN = VCC = 5.25V IOL = -4 mA IOH = 4 mA VIN = GND VIN = VCC VCC = 5.25V PCLK = LCLK = 33MHz VCC = 5.0V PCLK = LCLK = 33MHz 2.4 -10 10 150 2.0 -10 10 0.4 Min Max 0.8 Units V V A A V
V A A mA
ICC (max) Maximum supply current ICC (typ) CIO Typical supply current Input and output capacitance
120 10
mA pF
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC Data Sheet Rev 1.1
13
V300PSC 4.0 AC Specifications
The AC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.1, Section 4.2.1.2. For more information on the PCI AC specifications, including the V/I curves for 5V signalling, see section 4.2.1.2 of Rev 2.1 PCI Specification.
4.1
PCI Bus Timings Table 11: PCI Bus Signals AC Operating Specifications
Symbol
Parameter Switching current high (Test point) Switching current low (Test point)
Condition 0VMin -44 -44+(VOUT-1.4)/0.024
Max
Units mA
Notes 1 1, 2, 3 3 1 1, 3 3
IOH(AC)
1.4VEquation A -142
mA mA mA
95 VOUT/0.023 Equation B 206 -25+(VIN+1)/0.015 1 5
IOL(AC)
2.2V>VOUT>0.55 VOUT=0.71 -5mA mA mA
ICL tR tF
Low clamp current Unloaded output rise time Unloaded output fall time
V/ns
4
2.4V to 0.4V
1
5
V/ns
4
Notes: 1. Refer to the V/I curves in Section 4.2.1 of the PCI Specification. This specification does not apply to CLK and RST which are system outputs. "Switching Current High" specifications are not relevant to open drain outputs such as SERR and INTA-INTD. 2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the voltage rail (as it does in the pull-down curve). This difference is intended to allow for an optional N-channel pullup. 3. Maximum current requirements are met as drivers pull beyond the first step voltage (AC drive point). Equations defining these maximums (A and B) are provided with the respective V/I curves given in the PCI Spec. The equation defined maxima is met by design. 4. The minimum slew rate (slowest signal edge) is met by the PCI drivers. The maximum slew rate (fastest signal edge) is a guideline. Motherboard designers must bear in mind that rise and fall times faster than this maximum guideline could occur, and should ensure that signal integrity modeling accounts for this. Equation A: IOH = 11.9*(VOUT - 5.25V)*(VOUT + 2.45V) for VCC > VOUT > 3.1V Equation B: IOL = 78.5*VOUT(4.4V - VOUT) for 0V < VOUT < 0.71V
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V300PSC Data Sheet Rev 1.1
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC
4.2 Local Bus Timings Table 12: Local Bus AC Test Conditions
Symbol VCC VIN COUT Parameter Supply voltage Input low and high voltages Capacitive load on output and I/O pins Limits 4.75 to 5.25 0.4 and 2.0 50 Units V V pF
Table 13: Capacitive Derating for Output and I/O Pins
Output Drive Limit 4mA Derating 0.058 ns/pF for loads > 50pF
Figure 4: Clock and Synchronous Signals
TC TCH TSU TH TCL
LOCAL CLOCK INPUT SETUP/HOLD OUTPUT VALID
Tczo VALID TCOV VALID
OUTPUT DRIVE
TCOZ
VALID
OUTPUT FLOAT
Figure 5: ALE Signal
TALE
ALE AD
ADDRESS TASU TAH
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC Data Sheet Rev 1.1
15
V300PSC
Table 14: Local Bus Timing Parameters for Vcc = 5 Volts +/- 5%
33MHz # 1 2 3 4 4a 4b 5 6 6a 7 8 Symbol TC TCH TCL TSU TSU TSU TH TCOV TCOV TCZO TCOZ LCLK period LCLK high time LCLK low time Synchronous input setup Synchronous input setup (BTERM) Synchronous input setup (data) Synchronous input hold LCLK to output valid delay LCLK to output valid delay (address, data, byte enable, parity) LCLK to output driving delay LCLK to high impedance delay 4 3 3 3 3 3 1 1 2 Description Notes Min 30 12 12 7 4 5 2 14 15 15 15 Max Units ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Measured at 1.5V. 2. All local bus signals except those in 4a, 4b, 4c. 3. All local bus signals except those in 6a. 4. READY, BLAST, ADS are driven to high impedance at the falling edge of LCLK.
Table 15: ALE Timing Parameters for Vcc = 5 Volts +/- 5%
33MHz # Symbol 1 2 3 TALE TASU TAH ALE Pulse Width Address setup to ALE falling (ALE as output) Address hold from ALE falling (ALE as output) Description Min TCH-4 TCH-5 TCL-5 Max Units ns ns ns
16
V300PSC Data Sheet Rev 1.1
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC
Table 16: PCI Bus Timing Parameters for Vcc = 5 Volts +/- 5%
# 1 2 3 4 5 6 7 Symbol TC TSU TH TCOV TCZO TCOZ TRST PCLK period Synchronous input setup to PCLK Synchronous input hold from PCLK PCLK to output valid delay PCLK to output driving delay PCLK to high impedance delay Reset period 2 1 Description Notes Min 30 7 0 3 4 5 16*TC 11 11 18 Max Units ns ns ns ns ns ns
4.3
Serial EEPROM Port TImings
The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms generated are shown in Figure 6.
Figure 6: Serial EEPROM Waveforms and Timings
512 PCI BUS CLOCKS STOP CONDITION
START CONDITION
SCL
SDA
256 PCI BUS CLOCKS
256 PCI BUS CLOCKS
Copyright (c) 1997, V3 Semiconductor Corp.
V300PSC Data Sheet Rev 1.1
17
V300PSC 5.0 Revision History
Table 17: Revision History
Revision Number 1.1 1.0 Date 4/97 3/97 Comments and Changes Second revision. Updated signal names and product codes. Preliminary data sheet. DC and AC specs TBD. Sent only to a limited number of customers.
USA: 2348G Walsh Ave. Santa Clara CA 95051 Phone: (408)988-1050 Fax: (408)988-2601 Toll Free: (800)488-8410 (Canada and U.S. only) World Wide Web: http://www.vcubed.com
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V300PSC Data Sheet Rev 1.1
Copyright (c) 1997, V3 Semiconductor Corp.

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