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ST5x86
100 and 120 MHz 3.45 Volt 5x86 CPU
PRELIMINARY DATA
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586-CLASS PERFORMANCE - 100 and 120 MHz core speeds with 33, 40, and 50 MHz bus options - 16 KByte write-back cache - Superpipelining and branch prediction - Data forwarding - Decoupled load/store unit - On-chip FPU with 64-bit interface SMALL FOOTPRINT - 208-pin QFP, 168-pin CPGA, 168-pin PPGA
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BUILT-IN POWER MANAGEMENT - System management mode - Suspend mode - FPU, pipeline, and cache auto idle - Stop clock capability - Operates at 3.45V with 5V tolerant I/O x86 INSTRUCTION SET COMPATIBLE - Runs Windows, DOS, UNIX, Novell and others
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The ST5x86TM microprocessor is a high performance 586-class CPU compatible with all popular x86 operating systems, including DOS, Windows, Windows NT, Windows95, UNIX, Novell, OS/2 and Solaris. The 586-class performance is achieved by a superpipelined architecture in the integer unit combined with data forwarding, branch prediction, 16-KByte write-back cache, single-cycle instruction decode, and single-cycle execution.
The 5x86 processor provides many power saving features that make it ideal for power sensitive systems. The CPU automatically powers down the Floating Point Unit (FPU) and other internal circuits when they are not in use. Fast entry and exit from System Management Mode (SMM) allow frequent use of the SMM feature without noticeable performance degradation.
BLOCK DIAGRAM
October 1995
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
ST5x86
1.0 ARCHITECTURE OVERVIEW The SGS-THOMSON 5x86 family represents a new generation of x86-compatible 64-bit microprocessors with fifth-generation features. The Branch Target Buffer provides branch prediction with accuracy averaging 80%. The decoupled Load/Store unit allows multiple instructions in a single clock cycle. Other features include single-cycle execution, single-cycle instruction decode, 16-KByte Write-Back cache, and clock rates up to 120 MHz made possible by the use of advanced process technologies and superpipelining. The 100-MHz core speed option can operate with a bus speed of either 33 MHz or 50 MHz. The 120-MHz core speed option operates with a bus speed of 40 MHz. The 5x86 CPU operates from a 3.45-volt power supply, resulting in lower power consumption at all clock frequencies. Where additional power savings are required (especially in portable applications), designers can make use of suspend mode, stop clock capability, and System Management Mode (SMM). 1.1 Major Functional Blocks The 5x86 CPU is divided into major functional blocks as shown in the overall block diagram on the first page of this manual. - Integer Unit - Floating Point Unit - Write-Back Cache - Memory Management Unit - Bus Interface Unit The Integer Unit consists of the - Instruction Buffer - Instruction Fetch Unit - Instruction Decoder and Issue Unit. Instructions are executed in the integer unit and in the floating point unit. The cache unit stores the most recently used data and instructions and provides fast access to this information for the integer and floating point units. When external memory access is required, the physical address is calculated by the Memory Management Unit and then passed to the Bus Interface Unit, which provides the interface between the external system board and the processor's internal execution and cache units. Figure 1.1. Integer-Unit Pipeline
Instruction Fetch Stage
Instruction Decode Stage
Address Calculation Stage 1
Address Calculation Stage 2
Execution Stage
Write Back
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1.2 INTEGER UNIT The superpipelined Integer Unit fetches, decodes, and executes x86 instructions through the use of a 6-stage integer pipeline (Figure 1.1.). 1.2.1 Pipeline Stages The Instruction Fetch pipe stage generates from the on-chip cache, a continuous, high-speed instruction stream for use by the processor. Up to 128 bits of code are read during a single clock cycle. Branch prediction logic, within the prefetch unit, generates a predicted target address for unconditional or conditional branch instructions. When a branch instruction is detected, the instruction fetch stage starts loading instructions at the predicted address within a single clock cycle. Up to 48 bytes of code are queued prior to the Instruction Decode stage. The Instruction Decode stage evaluates the code stream provided by the instruction fetch stage and determines the number of bytes in each instruction and the instruction type. Instructions are processed and decoded at a maximum rate of one instruction per clock. The Address Calculation function is superpipelined and contains two stages, AC1 and AC2. If the instruction refers to a memory operand, the AC1 calculates a linear memory address for the instruction. The AC2 stage performs any required memory management functions, cache accesses and reg-
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ister file accesses. If a floating point instruction is detected by AC2, the instruction is sent to the floating point unit for processing. The Execution stage, under control of microcode, executes instructions using the operands provided by the address calculation stage. Write-Back, the last stage of the integer unit, updates the register file within the integer unit or writes to the load/store unit within the memory management unit. 1.2.2 Branch Control Branch instructions occur, on average, every five instructions in x86-compatible programs. When the normal sequential flow of a program changes due to a branch instruction, the pipeline stages may stall because they are waiting for the CPU to calculate or retrieve and decode the new instruction stream. The 5x86 CPU minimizes the performance impact and latency of branch instructions by using branch prediction. 1.2.3 Branch Prediction The 5x86 CPU uses a Branch Target Buffer (BTB) to store branch target addresses and branch prediction information. During the fetch stage, the instruction stream is checked for the presence of branch instructions. If an unconditional branch instruction is encountered, the 5x86 processor accesses the BTB to check for the branch instruction's target address. If the branch instruction hits in the BTB, the 5x86 CPU begins fetching at the target address specified by the BTB. In the case of conditional branches, the BTB also provides history information to indicate whether the branch is more likely to be taken or not taken. If the conditional branch instruction hits in the BTB, the 5x86 CPU begins fetching instructions at the predicted target address. The decision to fetch the taken or not taken target address is based on a four-state branch prediction algorithm that achieves approximately 80% prediction accuracy. If the conditional branch misses in the BTB, the 5x86 processor predicts whether the branch will be taken or not-taken based on the opcode of the instruction. Once fetched, a conditional branch instruction is decoded and then dispatched to the pipeline. The conditional branch instruction continues through the pipeline and is resolved in the EX stage. Correctly predicted branch instructions execute in a single clock. If resolution of a branch indicates that a misprediction has occurred, the 5x86 CPU flushes the pipeline and starts fetching from the correct target address. Although the branch is resolved in the EX stage, the misprediction latency is five clock cycles. If a conditional branch misses in the BTB, the 5x86 CPU prefetches both the predicted path and the non-predicted path for each conditional branch, eliminating the cache access cycle on a misprediction. Since the target address of a return (RET) instruction is dynamic rather than static, the 5x86 processor caches the target addresses for RET instructions in a return stack rather than in the BTB. The return address is pushed on the return stack during a CALL instruction and popped during the corresponding RET instruction. 1.3 Write-Back Cache The 16-KByte write-back unified cache is a data/instruction cache and is configured as four-way set associative. The cache stores up to 16 KBytes of code and data in 1024 cache lines. 1.4 Memory Management Unit The memory management unit translates the linear address supplied by the integer unit into a physical address to be used by the cache unit and the bus interface. Memory management procedures are x86-compatible, adhering to standard paging mechanisms. The memory management unit also contains a load/store unit that is responsible for scheduling cache and external memory accesses. The load/store unit incorporates two performance-enhancing features:
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Load Store reordering - prioritizes memory reads required by the integer unit over writes to external memory Memory-read bypassing - eliminates unnecessary memory reads by using valid data still in the execution unit.
1.5 Floating Point Unit The 5x86 processor floating point unit interfaces to the integer unit and the cache unit through a 64-bit bus. The 5x86 CPU FPU is x87-instruction-set compatible and adheres to the IEEE-754 standard. Because most applications contain FPU instructions mixed with integer instructions, the 5x86 FPU achieves high performance by completing integer and FPU operations in parallel. FPU instructions are dispatched to the pipeline within the integer unit. The address calculation stage of the pipeline checks for memory management exceptions and accesses memory operands for use by the FPU. Once the instructions and operands have been provided to the FPU, the FPU completes instruction execution independently of the integer unit.
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1.6 Bus Interface Unit The Bus Interface Unit provides the signals and timing required by external circuitry. The signal descriptions and bus interface timing information is provided in Chapter 3 and Chapter 4 of the data book. 1.7 Configuration Registers The 5x86 CPU provides four 8-bit Configuration Control Registers (CCR1, CCR2, CCR3 and CCR4) that include control for the on-chip write-back cache, and SMM features. The CPU also provides a Power Management Control Register (PMR), two 8-bit internal read-only device identification registers (DIR0 and DIR1), one 24-bit SMM Address Region Register (SMAR), and an 8 bit Performance Control Register PCR0. The CCR, PMR, DIR, PCR0, and SMAR registers exist in I/O memory space and are selected by a "register index" number as listed in Table 1.1. (Page 5). Access to these registers is achieved by writing the index of the register to I/O port 22h. I/O port 23h is then used for data transfer. Each I/O port 23h data transfer must be preceded by an I/O port 22h register index selection, otherwise the second and later I/O port 23h operations are directed off-chip and produce external I/O cycles. If the register index number is outside the C0h-CFh, FEh-FFh range, external I/O cycles will also occur. If the MAPEN field in CCR3 is set to 0001, then access can be made to the CCR4, PCR0, and PMR registers. Otherwise, external I/O cycles will occur if the register index number is outside the range C0-CFh, FEh, FFh. The MAPEN field must remain 0 during normal operation to allow system registers located at port 22h to be accessed.
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Table 1.1. Configuration Registration Set
REGISTER and INDEX Performance Control [PCR0] MAPEN 7 6 5 4 3 2 1 0
20h*
1h
LSSER
LOOP_EN
BTB_EN
RSTK_EN
Control 1 C1h [CCR1] Control 2 C2h [CCR2] Control 3 C3h [CCR3] Control 4 E8h* [CCR4] SMM Address CDh [SMAR0] SMM Address CEh [SMAR1] SMM Address CFh [SMAR2] Power ManageF0h* ment [PMR] Device ID0 [DIR0] Device ID1 [DIR1] FEh
xh xh xh 1h USE_SUSP MAPEN3 BWRT WT1
MMAC
SMAC
USE_SMI
SUSP_HALT LOCK_NW USE_WBAK LINBRST IORT2 NMI_EN IORT1 SMI_LOCK IORT0
MAPEN2 MAPEN1 MAPEN0 SMM_MODE DTE_EN MEM_BYP
xh
A31
A30
A29
A28
A27
A26
A25
A24
xh
A23
A22
A21
A20
A19
A18
A17
A16
xh
A15
A14
A13
A12
S1ZE3
SIZE2
SIZE1
SIZE0
1h
HLF_CLK
CLK1
CLK0
xh
DEVICE_ID
FFh
xh
SID3
SID2
SID1
SID0
RID3
RID2
RID1
RID0
Note: The following register index numbers are reserved for future use: C0h through CFh and FEh, FFh. *Note: MAPEN must be set to access these registers.
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Figure 1.2. Performance Control Register 0 (PCR0)
Table 1.2. PCR0 Bit Definitions
BIT POSITION NAME DESCRIPTION Return Stack Enable. If = 1: the Return Stack is enabled and RET instructions will speculatively execute the code following the associated CALL to improve performance. If = 0: the Return Stack is not enabled and optimum performance will not be achieved. Branch Target Buffer enable. If = 1: the Branch Target Buffer is enabled and branch prediction occurs. If = 0: no branch prediction will occur. Loop Enable. If = 1: the CPU will not flush the prefetch buffer if the destination of a jump is already present in the prefetch buffer. This eliminates the need for a read from the cache and thus improves performance. Reserved. Load Store Serialize Enable (Reorder Disable). If = 1: all memory reads and writes will occur in execution order (load store serializing enabled, reordering disabled). If = 0: memory reads and writes can be reordered for optimum performance (load store serializing disabled, reordering enabled). Memory accesses in the address range 640K to 1M will always be issued in execution order. LSSER should be set to ensure that memory-mapped I/O devices operating outside of the address range 640K to 1M will operate correctly.
0
RSTK_EN
1
BTB_EN
2
LOOP_EN
3-6
7
LSSER
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Figure 1.3. Configuration Control Register 1 (CCR1)
Table 1.3. CCR1 Bit Definitions
BIT POSITION 1* NAME DESCRIPTION Enable SMM Pins If = 1: SMI# input/output pin and SMADS# output pin are enabled. If = 0: SMI# input pin ignored and SMADS# output pin floats. System Management Memory Access If = 1: Any access to addresses within the SMM memory space cause external bus cycles to be issued with SMADS# output active. SMI# input is ignored. If = 0: No effect on access. Main Memory Access If = 1: All data accesses which occur within an SMI service routine (or when SMAC = 1) access main memory instead of SMM memory space. If = 0: No effect on access.
USE_SMI
2*
SMAC
3*
MMAC
Note: Bits 0, 4-7 are reserved. Bits 1-3 are cleared to 0 at reset. *Note: Access enabled by CCR3, bit 0, SMI-Lock bit.
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Figure 1.4. Configuration Control Register 2 (CCR2)
Table 1.4. CCR2 Bit Definitions
BIT POSITIO N NAME DESCRIPTION Enable Write-Back Cache Interface Pins If = 1: Enable INVAL and WM_RST input pins, CACHE#, and HITM# output pins. When enabling write-back cache mode, the USE_WBAK bit must be set prior to setting the NW bit in CR0. If = 0: INVAL and WM_RST input pins are ignored, and CACHE# and HITM# output pins float. LOCK NW Bit If = 1: Prohibits changing the state of the NW bit in CR0. Suspend on HALT If = 1: CPU enters suspend mode following execution of a HALT instruction. Write-Through Region 1 If = 1: Forces all writes to the address region between 640 KBytes to 1 MByte that hit in the on-chip cache to be issued on the external bus. Enable Burst Write Cycles If = 1: Enables use of 16-byte burst write-back cycles. Enable Suspend Pins If = 1: SUSP# input and SUSPA# output are enabled. If = 0: SUSP# input is ignored and SUSPA# output floats.
1
USE_WBAK
2 3
LOCK_NW SUSP_HALT
4
WT1
6
BWRT
7
USE_SUSP
Note: Bits 0 and 5 are reserved. Bits 1-4, 6 and 7 are cleared to 0 at reset.
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Figure 1.5. Configuration Control Register 3 (CCR3)
Table 1.5. CCR3 Bit Definitions
BIT POSITI ON NAME DESCRIPTIO N SMM Register Lock If = 1: the following SMM control bits can not be modified: CCR1 bits: 1, 2, and 3 CCR3 bit: 1 all SMAR bits. However, while operating within a SMI handler these SMM control bits can be modified. Once set, the SMI_LOCK bit can only be cleared by asserting the RESET pin. NMI Enable If = 1: NMI is enabled during SMM. If = 0: NMI is not recognized during SMM. Linear Address Burst Cycles If = 1: linear address sequence is used while performing burst cycles. If = 0: "1+4" address sequencing is used while performing burst cycles.
0
SMI_LOCK
1*
NMI_EN
2
LINBRST
3*
SMM Mode SMM_MODE If = 1: SMM pins function as defined for SL-compatible mode. If = 0: SMM pins function as defined for standard Cyrix SMM mode. MAPEN[3-0] MAP Enable If = 1h: all configuration registers are accessible. All accesses to port 22h are trapped. If = 0h: only configuration registers C0h through CFh, FEh and FFh are accessible.
4-7
Note: Bits 0-7 are cleared to zero at reset. *Note: Access defined by CCR3, bit 0, SMI-Lock bit.
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Figure 1.6. Configuration Control Register 4 (CCR4)
Table 1.6. CCR4 Bit Definitions
BIT POSITION NAME DESCRIPTION I/O Recovery Time Specifies the minimum number of bus clocks between I/O accesses: 0h = no clock delay 1h = 2-clock delay 2h = 4-clock delay 3h = 8-clock delay 4h = 16-clock delay 5h = 32-clock delay (default value after RESET) 6h = 64-clock delay 7h = 128-clock delay If = 1: Memory read bypassing is enabled. If = 0: Memory read bypassing is disabled. Enable Directory Table Entry Cache If = 1: the Directory Table Entry cache is enabled. If = 0: the Directory Table Entry cache is disabled.
2-0
IORT[2-0]
3
MEM_BYP
4
DTE_EN
Note: Bits 0-4 are cleared to zero at reset, bits 5-7 are reserved.
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Figure 1.7. Power Management Register (PMR)
Table 1.7. PMR Bit Definitions
BIT POSITION NAME DESCRIPTION Core Clock/Bus Clock Ratio If = 0h: ratio = 1/1 If = 1h: ratio = 2/1 (default power-up for CLKMUL pin = 0) If = 2h: ratio = reserved If = 3h: ratio = 3/1 (default power-up for CLKMUL pin = 1) At reset, the CLK[1-0] bits are initialized to 1h if CLKMUL = 0, or to 3h if CLKMUL = 1. After reset is completed, CLK[1-0] bits may be set to 0h in order to obtain lower power consumption. The default power-up value must be restored when peak CPU performance is required. Half Speed Clock If = 1: the CPU core operates at half the speed of the external bus clock regardless of the CLK[1-0] bits except during external bus transfers. When an external bus transfer occurs, the core clock frequency automatically increases in frequency for the duration of the transfer. When the transfer is complete, the core returns to half the frequency of the bus.
1-0
CLK[1-0]
2
HLF_CLK
Note: Bit 2 is cleared to zero at reset, bits 3-7 are reserved.
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Figure 1.8. SMM Address Region Registers (SMAR)
Note: The SMAR register is accessed as three unique registers using separate register indices CDh, CEh, and CFh. Note: Access to the SMAR register is enabled by CCR3 bit 0, SMI_LOCK bit.
Table 1.8. SMAR-SIZE Field Bit Definitions
SIZE (3-0) 0h 1h 2h 3h 4h 5h 6h 7h BLOCK SIZE Disabled 4 KBytes 8 KBytes 16 KBytes 32 KBytes 64 KBytes 128 KBytes 256 KBytes SIZE (3-0) 8h 9h Ah Bh Ch Dh Eh Fh BLOCK SIZE 512 KBytes 1 MBytes 2 MBytes 4 MBytes 8 MBytes 16 MBytes 32 MBytes 4 KBytes (same as 1h)
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Figure 1.9. Device Identification Register 0 (DIR0)
Table 1.9. DIR0 Bit 0 Definitions
BIT POSITIO N 7-0 NAME DEVICE_ID[7-0] DESCRIPTION CPU Device Identification Number (read only).
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Figure 1.10. Device Identification Register 1 (DIR1)
Table 1.10. DIR1 Bit Definitions
BIT POSITION 3-0 7-4 NAME RID[3-0] SID[3-0] DESCRIPTION Revision Identification: RID[3-0] are read only and indicate device revision number. Stepping Identification: SID[3-0] are read only and indicate device stepping number.
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2.0 ELECTRICAL SPECIFICATIONS This section provides information on electrical connections, absolute maximum ratings, recommended operating conditions, and DC characteristics, and AC characteristics. All voltage values in Electrical Specifications are with respect to V SS unless otherwise noted. 2.1 Electrical Connections 2.1.1 Power and Ground Connections and Decoupling Testing and operating the 5x86 CPU requires the use of standard high frequency techniques to reduce parasitic effects. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the VCC and GND pins. 2.2 Pull-Up/Pull-Down Resistors Table 2.1. lists the input pins that are internally connected to pull-up and pull-down resistors. When unused, these inputs do not require connection to external pull-up or pull-down resistors. The SUSP# pin is unique in that it is connected to a pull-up resistor only when SUSP# is not asserted. CLKMUL should not be connected to a switching signal. Table 2.1. Pins Connected to Internal Pull-Up and Pull-Down Resistors
SIGNAL A20M# AHOLD BOFF# BS16# BS8# BRDY# CLKMUL EADS# FLUSH# IGNNE# INVAL KEN# RDY# SUSP# UP# WM_RST RESISTOR 20-k pull-up 20-k pull-down 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-down
It is recommended that the ADS#, LOCK# and SMI# output pins be connected to pull-up resistors, as indicated in Table 2.2. The external pull-ups guarantee that the signals remain high (inactive) during hold acknowledge states. Table 2.2. Pins Requiring External Pull-Up Resistors
SIGNAL ADS# LOCK# SMI# EXTERNAL RESISTOR 20-k pull-up 20-k pull-up 20-k pull-up
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2.2.2 Unused Input Pins All inputs not used by the system designer and not listed in Table 2.1. (Page 15) should be kept at either ground or VCC. To prevent possible spurious operation, connect active-high inputs to ground through a 20-k ( 10%) pull-down resistor and active-low inputs to VCC through a 20-k ( 10%) pull-up resistor. 2.2.3 NC Designated Pins Pins designated NC should be left disconnected. Connecting an NC pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. Table 2.3. Absolute Maximum Ratings
ALL 5x86 CPUs PARAMETER MIN Operating Case Temperature Storage Temperature Supply Voltage, VCC Voltage On Any Pin Input Clamp Current, IIK Output Clamp Current, IOK -65 -65 -0.5 -0.5 MAX 110 150 4.0 6.0 10 25 C C V V mA mA Power Applied No Bias UNITS NOTES
2.3 Absolute Maximum Ratings Table 2.3. lists absolute maximum ratings for the 5x86 microprocessors. Stresses beyond the listed ratings may cause permanent damage to the device. Exposure to conditions beyond these limits may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings may also result in reduced useful life and reliability. These are stress ratings only and do not imply that operation under any conditions other than those listed under "Recommended Operating Conditions" Table 2.4. (Page 17) is possible. .
Power Applied Power Applied
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2.4 Recommended Operating Conditions Table 2.4. lists the recommended operating conditions for the 5x86 CPU. Table 2.4. Recommended Operating Conditions
ALL 5x86 CPUs PARAMETER MIN TC Operating Case Temperature VCC Supply Voltage VIH High-Level Input Voltage VIL Low-Level Input Voltage All Inputs Except CLK CLK Input Only IOH High-Level Output Current IOL Low-Level Output Current 0 3.3 2.0 -0.3 -0.3 MAX 85 3.6 5.5 0.6 0.5 -2.0 5.0 C V V UNITS NOTES
V mA mA VO=VOH(MIN) VO=VOL(MAX}
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2.5 DC Characteristics Table 2.5. DC Characteristics (at Recommended Operating Conditions)
ALL 5x86 CPUs PARAMETER MIN VOL Output Low Voltage 2.4 15 200 -400 MAX 0.45 V V IOL = 5 mA IOH = -2 mA 0 < VIN < VCC, See Table 2.1. VIH = 2.4 V, See Table 2.1. VIL = 0.45 V, See Table 2.1. UNITS NOTES
VOH Output High Voltage II Input Leakage Current for all pins except those with internal pull-ups or pull-downs Input Leakage Current for all pins with internal pull-downs. Input Leakage Current for all pins with internal pull-ups.
A A A
IIH IIL
ICC Active ICC 5x86-100 at fCLK = 100 MHz 5x86-120 at fCLK = 120 MHz ICCSM Suspend Mode ICC 5x86-100 at fCLK = 100 MHz 5x86-120 at fCLK = 120 MHz ICCSS Standby ICC (Suspended and CLK Stopped) CIN Input Capacitance
0.9 TYP 1.0 TYP 20 TYP 50 TYP 15 TYP
1.2 1.4 75 75 60 20 20 20
A
Note 1
A A
pF pF pF
Notes 1, 3 fCLK = 0 MHz, Note 4 f = 1 MHz, Note 2 f = 1 MHz, Note 2 f = 1 MHz, Note 2
COUT Output or I/O Capacitance CCLK CLK Capacitance
Notes:
1. fCLK ratings refer to internal clock frequency. 2. Not 100% tested. 3. All inputs are at 0.4 or VCC - 0.4 (CMOS levels). All inputs held are static except clock and all outputs are unloaded (static IOUT = 0 mA). This specification is also valid for UP# = 0. 4. All inputs are at 0.4 or VCC - 0.4 (CMOS levels). All inputs are held static and all outputs are unloaded (static IOUT = 0 mA).
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2.6 AC Characteristics Table 2.6. (Page 19) through Table 2.12. (Page 25) list the AC characteristics including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 2.1. (Page 20) and Figure 2.2. (Page 21). The rising-clock-edge reference level VREF and other reference levels are shown in Table 2.6. Drive Level and Measurement Points for Switching Characteristics
SYMBOL VREF VIHD VILD
Note: Refer to Figure 2.1.
Table 2.6. below. Input or output signals must cross these levels during testing. Figure 2.1. shows output delay (A and B) and input setup and hold times (C and D). Input setup and hold times are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation.
VOLTAGE (Volts) 1.5 2.3 0
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Figure 2.1. Drive Level and Measurement Points for Switching Characteristics
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Table 2.7. Clock Specifications Tcase = 0 to 85 C (See Figure 2.2.)
5x86-100 33-MHz BUS MIN CLK Frequency T1 T2 T3 T4 T5 T6 CLK Period CLK Period Stability CLK High Time CLK Low Time CLK Fall Time CLK Rise Time 11 11 3 3 30 250 9 9 3 3 MAX 33 25 250 7 7 2 2 5x86-120 40-MHz BUS MIN MAX 40 20 250 5x86-100 50-MHz BUS MIN MAX 50 MHz ns ps ns ns ns ns At 2 V 0.5 V 2 to 0.5 V 0.5 to 2 V
PARAMETER
UNITS
NOTES
Figure 2.2. CLK Timing and Measurement Points
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Table 2.8. Output Valid Delays CL = 50 pF, Tcase = 0 to 85 C (See Figure 2.3.)
5x86-100 33-MHz BUS MIN T7 T7a T7b All output signals not listed below D31 - D0, DP3 - DP0 A19 - A2 3 3 3 MAX 14 14 14 5x86-120 40-MHz BUS MIN 3 3 3 MAX 14 14 14 5x86-100 50-MHz BUS MIN 2 3 2 MAX 12 12 10.5 ns ns ns
PARAMETER
UNITS
Figure 2.3. Output Valid Delay Timing
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Table 2.9. Output Float Delays CL = 50 pF, Tcase = 0 to 85 C (See Figu re 2.4.)
5x86-100 33-MHz BUS MIN T8 All output signals. MAX 20 5x86-120 40-MHz BUS MIN MAX 19 5x86-100 50-MHz BUS MIN MAX 18 ns
PARAMETER
UNITS
Figure 2.4. Output Float Delay Timing
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Table 2.10. Input Setup Times Tcase = 0 to 85 C (See Figure 2.5.)
5x86-100 33-MHz BUS MIN T9 T9a T9b T9c All inputs not listed below HOLD, AHOLD BOFF# A31 - A4, D31 - D0, DP3 - DP0 5 6 7 5 5x86-120 40-MHz BUS MIN 5 5 6 5 5x86-100 50-MHz BUS MIN 5 5 5 4 ns ns ns ns
PARAMETER
UNITS
Table 2.11. Input Hold Times Tcase = 0 to 85 C (See Figu re 2.5.)
5x86-100 33-MHz BUS MIN T10 All inputs 3 5x86-120 40 MHz-BUS MIN 3 5x86-100 50-MHz BUS MIN 2 ns
PARAMETER
UNITS
Figure 2.5. Input Setup and Hold Timing
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Table 2.12. JTAG AC Specifications
ALL BUS FREQUENCIES SYMBOL PARAMETER MIN TCK Frequency (MHz) T37 T38 T39 T40 T41 T42 T43 T44 T45 T47 T48 T49 T50 TCK Period TCK High Time TCK Low Time TCK Rise Time TCK Fall Time TDO Valid Delay Non-test Outputs Valid Delay TDO Float Delay Non-test Outputs Float Delay TDI, TMS Setup Time Non-test Inputs Setup Time TDI, TMS Hold Time Non-test Inputs Hold Time 8 8 7 7 3 3 40 10 10 4 4 25 25 30 36 MAX MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 2.6. Figure 2.6. Figure 2.6. Figure 2.6. Figure 2.6. Figure 2.7. Figure 2.7. Figure 2.7. Figure 2.7. Figure 2.7. Figure 2.7. Figure 2.7. Figure 2.7. UNITS FIGURE
Figure 2.6. TCK Timing and Measurement Points
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Figure 2.7. JTAG Test Timings
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3.0 MECHANICAL SPECIFICATIONS 3.1 168-Pin PGA Package The pin assignments for the 5x86V10HS, 5x86V10PS, 5x86V12HS and 5x86V12PS are shown in Figure 3.1. The pins are listed by signal name and pin number in Table 3.1. and Table 3.2. respectively. Dimensions for the 168-pin CPGA package are shown in Figure 3.2. and Table 3.3. Figure 3.1. 168-Pin PGA Package Pin Assignments
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Table 3.1. 168-Pin PGA Package Pin Numbers Sorted by Signal Name
Signal A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A20M# A21 A22 A23 A24 A25 A26 A27 A28 Pin Q14 R15 S16 Q12 S15 Q13 R13 Q11 S13 R12 S7 Q10 S5 R7 Q9 Q3 R5 Q4 Q8 D15 Q5 Q7 S3 Q6 R2 S2 S1 R1 Signal A29 A30 A31 ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS8# BS16# CACHE# CLK CLKMUL D/C# D0 D1 D2 D3 D4 D5 D6 D7 D8 Pin P2 P3 Q1 S17 A17 K15 J16 J15 F17 R16 D17 H15 Q15 D16 C17 B12 C3 R17 M15 P1 N2 N1 H2 M3 J2 L2 L3 F2 Signal D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 DP0 DP1 DP2 DP3 EADS# Pin D1 E3 C1 G3 D2 K3 F3 J3 D3 C2 B1 A1 B2 A2 A4 A6 B6 C7 C6 C8 A8 C9 B8 N3 F1 H3 A5 B17 Signal FERR# FLUSH# HITM# HLDA HOLD IGNNE# INTR INVAL KEN# LOCK# M/IO# NC NC NC NMI PCD PCHK# PLOCK# PWT RDY# RESET SMADS# SMI# SUSP# SUSPA# TCK TDI TDO Pin C14 C15 A12 P15 E15 A15 A16 A10 F15 N15 N16 B13 C13 J1* B15 J17 Q17 Q16 L15 F16 C16 C12 B10 G15 A13 A3 A14 B16 Signal TMS UP# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VOLDET VSS VSS Pin B14 C11 B7 B9 B11 C4 C5 E2 E16 G2 G16 H16 K2 K16 L16 M2 M16 P16 R3 R6 R8 R9 R10 R11 R14 S4 A7 A9 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W/R# WM_RST Pin A11 B3 B4 B5 E1 E17 G1 G17 H1 H17 K1 K17 L1 L17 M1 M17 P17 Q2 R4 S6 S8 S9 S10 S11 S12 S14 N17 C10
*Note: J1 is an internal no connect and may be connected to an external supply voltage.
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Table 3.2. 168-Pin PGA Package Signal Names Sorted by Pin Number
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 Signal D20 D22 TCK D23 DP3 D24 VSS D29 VSS INVAL VSS HITM# SUSPA# TDI IGNNE# INTR AHOLD D19 D21 VSS VSS VSS D25 VCC D31 VCC SMI# VCC Pin B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D15 D16 Signal CACHE# NC TMS NMI TDO EADS# D11 D18 CLK VCC VCC D27 D26 D28 D30 WM_RST UP# SMADS# NC FERR# FLUSH# RESET BS16# D9 D13 D17 A20M# BS8# Pin D17 E1 E2 E3 E15 E16 E17 F1 F2 F3 F15 F16 F17 G1 G2 G3 G15 G16 G17 H1 H2 H3 H15 H16 H17 J1* J2 J3 Signal BOFF# VSS VCC D10 HOLD VCC VSS DP1 D8 D15 KEN# RDY# BE3# VSS VCC D12 SUSP# VCC VSS VSS D3 DP2 BRDY# VCC VSS NC D5 D16 Pin J15 J16 J17 K1 K2 K3 K15 K16 K17 L1 L2 L3 L15 L16 L17 M1 M2 M3 M15 M16 M17 N1 N2 N3 N15 N16 N17 P1 Signal BE2# BE1# PCD VSS VCC D14 BE0# VCC VSS VSS D6 D7 PWT VCC VSS VSS VCC D4 D/C# VCC VSS D2 D1 DP0 LOCK# M/IO# W/R# D0 Pin P2 P3 P15 P16 P17 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 R1 R2 R3 R4 R5 R6 Signal A29 A30 HLDA VCC VSS A31 VSS A17 A19 A21 A24 A22 A20 A16 A13 A9 A5 A7 A2 BREQ PLOCK# PCHK# A28 A25 VCC VSS A18 VCC Pin R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 Signal A15 VCC VCC VCC VCC A11 A8 VCC A3 BLAST# CLKMUL A27 A26 A23 VOLDET A14 VSS A12 VSS VSS VSS VSS VSS A10 VSS A6 A4 ADS#
*Note: J1 is an internal no connect and may be connected to an external supply voltage.
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Figure 3.2. 168-Pin PGA Package
Table 3.3. 168-Pin PGA Package Dimensions
SYMBOL A A1 B D D1 e1 L MILLIMETERS MIN 3.56 1.14 0.43 44.07 40.51 2.29 2.54 MAX 4.57 1.40 0.51 44.83 40.77 2.79 3.30 MIN 0.140 0.045 0.017 1.735 1.595 0.090 0.100 INCHES MAX 0.180 0.055 0.020 1.765 1.605 0.110 0.130
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3.2 208-Lead QFP Package The pin assignments for the 5x86V10LS and 5x86V12LS are shown in Figure 3.3. Pins are listed by signal name in Table 3.4. and by pin number in Table 3.5. Package dimensions for the 208-lead QFP (Quad Flat Pack) are shown in Figure 3.4. and Table 3.6. Figure 3.3. 208-Lead QFP Package Pin Assignments
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Table 3.4. 208-Lead QFP Package Pins Sorted by Signal Name
Signal A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A20M# A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 ADS# AHOLD BE0# BE1# Pin 202 197 196 195 193 192 190 187 186 182 180 178 177 174 173 171 166 165 164 47 161 160 159 158 154 153 152 151 149 148 147 203 17 31 32 Signal BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# CACHE# CLK CLKMUL D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 Pin 33 34 204 6 5 30 7 8 70 24 11 144 143 142 141 140 130 129 126 124 123 119 118 117 116 113 112 108 103 101 100 99 93 92 91 Signal D24 D25 D26 D27 D28 D29 D30 D31 D/C# DP0 DP1 DP2 DP3 EADS# FERR# FLUSH# HITM# HLDA HOLD IGNNE# INTR INVAL KEN# LOCK# M/IO# NC NC NC NC NMI PCD PCHK PLOCK# PWT RDY# Pin 87 85 84 83 79 78 75 74 39 145 125 109 90 46 66 49 63 26 16 72 50 71 13 207 37 3* 64 96 127 51 41 4 206 40 12 Signal RESET SMADS# SMI# SUSP# SUSPA# TCK TDI TDO TMS UP# Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Pin 48 59 65 73 67 18 168 68 167 194 2 9 14 19 20 22 23 25 29 35 38 42 44 45 54 56 60 62 69 77 80 82 86 89 95 Signal Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss Vss Vss Pin 98 102 106 111 114 121 128 131 133 134 136 137 139 150 155 162 163 169 172 176 179 183 185 188 191 198 200 205 1 10 15 21 28 36 43 Signal Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss WM_RST W/R# Pin 52 53 55 57 61 76 81 88 94 97 104 105 107 110 115 120 122 132 135 138 146 156 157 170 175 181 184 189 199 201 208 58 27
*Note: Pin 3 is an internal no connect and may be connected to an external supply voltage.
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Table 3.5. 208-Lead QFP Package Signals Sorted by Pin Number
Pin 1 2 3* 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Vss Vcc NC PCHK# BRDY# BOFF# BS16# BS8# Vcc Vss CLKMUL RDY# KEN# Vcc Vss HOLD AHOLD TCK Vcc Vcc Vss Vcc Vcc CLK Vcc HLDA W/R# Vss Vcc BREQ BE0# BE1# BE2# BE3# Vcc Pin 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal Vss M/IO# Vcc D/C# PWT PCD Vcc Vss Vcc Vcc EADS# A20M# RESET FLUSH# INTR NMI Vss Vss Vcc Vss Vcc Vss WM_RST SMADS# Vcc Vss Vcc HITM# NC SMI# FERR# SUSPA# TDO Vcc CACHE# Pin 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Signal INVAL IGNNE# SUSP# D31 D30 Vss Vcc D29 D28 Vcc Vss Vcc D27 D26 D25 Vcc D24 Vss Vcc DP3 D23 D22 D21 Vss Vcc NC Vss Vcc D20 D19 D18 Vcc D17 Vss Vss Pin 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Signal Vcc Vss D16 DP2 Vss Vcc D15 D14 Vcc Vss D13 D12 D11 D10 Vss Vcc Vss D9 D8 DP1 D7 NC Vcc D6 D5 Vcc Vss Vcc Vcc Vss Vcc Vcc Vss Vcc D4 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 Signal D3 D2 D1 D0 DP0 Vss A31 A30 A29 Vcc A28 A27 A26 A25 Vcc Vss Vss A24 A23 A22 A21 Vcc Vcc A20 A19 A18 TMS TDI Vcc Vss A17 Vcc A16 A15 Vss Pin 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Signal Vcc A14 A13 Vcc A12 Vss A11 Vcc Vss Vcc A10 A9 Vcc Vss A8 Vcc A7 A6 UP# A5 A4 A3 Vcc Vss Vcc Vss A2 ADS# BLAST# Vcc PLOCK# LOCK# Vss
*Note: Pin 3 is an internal no connect and may be connected to an external supply voltage.
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Figure 3.4. 208-Lead QFP Package
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Table 3.6. 208-Lead QFP Package Dimensions
MILLIMETERS SYMBOL MIN A1 A2 D D1 L 0.28 3.29 30.35 27.90 0.50 MAX 0.41 3.45 30.85 28.10 0.70 MIN 0.011 0.130 1.195 1.095 0.019 MAX 0.017 0.136 1.215 1.107 0.028 0 7 MIN MAX INCHES DEGREES
3.3 Thermal Characteristics The 5x86 processor is designed to operate when the case temperature at the top center of the package is between 0C and 85C. The maximum die (junction) temperature, TJ MAX, and the maximum ambient temperature, TA MAX, can be calculated by substituting thermal resistance and maximum values for case or junction temperature and power dissipation in the following equations: TJ TA where: TA TJ TC P JC JA = Ambient temperature (C) = Average junction temperature (C) = Case temperature at top center of package (C) = Power dissipation (W) = Junction-to-case thermal resistance (C/W) = Junction-to-ambient thermal resistance (C/W). = TC + (P * JC) = TJ - (P * JA)
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PGA Package Table 3.7. lists the junction-to-ambient and junction-to-case thermal resistances for the 5x86 processors in the 168-pin PGA (pin grid array) package. These devices have an "H" or "P" package suffix as shown in the ordering information. Table 3.8. lists the maximum ambient temperatures permitted for various clock frequencies at maximum I CC and VCC = 3.6 volts. The heatsink used to measure the data below is characterized by JA = 10 C/W. Table 3.7. PGA Package Thermal Resistance with No Airflow
PGA THERMAL RESISTANCE (C/W) WITH HEATSINK JA 12.5 JC 2.5 JA 17 WITHOUT HEATSINK JC 2.0
Table 3.8. PGA Package Maximum Ambient Temperature (with Heatsink, Airflow = 0)
CPU INTERNAL CLOCK FREQUENCY 100 MHz 120 MHz (5x86V12HS and 5x86V12PS devices only) AMBIENT TEMPERATURE 42 C 35 C
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QFP Package Table 3.9. lists the junction-to-ambient and junction-to-case thermal resistances for the 5x86 processors in the QFP (quad flat pack) package without a heat sink. These devices have an "L" package suffix as shown in the ordering information. Table 3.9. QFP Package Thermal Resistance (without Heatsink)
AIRFLOW (LFM) QFP THERMAL RESISTANCE (C/W)
JA 0 100
16 14
JC
2 2
Table 3.10. QFP Package Maximum Ambient Temperature
CPU INTERNAL CLOCK FREQUENCY AIRFLOW (LFM) 0 100 MHz 100 120 MHz (5x86V12LS devices only) 0 100 33 14 25 AMBIENT TEMPERATURE (C) 25
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Heatsinking is required for most applications. The appropriate heat sink will have a total case-to-heatsink and heatsink-to-ambient thermal resistance (CH + HA) no larger than the value resulting from the equation below. CH + HA where: TC
MAX
= (TC = 85C
MAX
- TA MAX ) / (VCC MAX * I CC MAX)
VCC MAX ICC MAX TA MAX
= 3.6 V = the appropriate value from Table 2.5 on page 18. = maximum ambient temperature required by the application.
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Ordering Information* Example: ST5X86 V 10 H S
Vcc V = 3.45 V
Speed (internal clock frequency) 10 = 100 MHz 12 = 120 MHz
Package Type H = CPGA Package L = Plastic Quad Package P = PPGA Package
Temperature Range S = Commercial
*Please contact your nearest SGS-THOMSON sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Information furnished is believed to be accurate and reliable. However, SGS-TH OMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as criti cal components in life support devices or systems without express written approval of SGS-THO MSON Microelectronics. (c)SGS-TH OMSON Microelectronics. All rights reserved. SGS-THO MSON Microelectronics GROUP OF COMPANIE S Australia - Brazil - France - Germany - Hong Kong - Italy - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Taiwan - United Kingdom - U.S.A .
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