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M14C64 M14C32
Memory Card IC 64/32 Kbit Serial I Bus EEPROM
2C
DATA BRIEFING
s s
Compatible with I2C Extended Addressing Two Wire I2C Serial Interface Supports 400 kHz Protocol Single Supply Voltage (2.5 V to 5.5 V) Hardware Write Control BYTE and PAGE WRITE (up to 32 Bytes) BYTE, RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behaviour 1 Million Erase/Write Cycles (minimum) 40 Year Data Retention (minimum) 5 ms Programming Time (typical)
2 2 2 2
s s s s
s s s s s s
Micromodule (D20)
Micromodule (D22)
DESCRIPTION Each device is an electrically erasable programmable memory (EEPROM) fabricated with STMicroelectronics's High Endurance, Single Polysilicon, CMOS technology. This guarantees an endurance typically well above one million Erase/Write cycles, with a data retention of 40 years. The memory operates with a power supply as low as 2.5 V for the M14Cxx-W version. The M14C32 is available in wafer form (either sawn or unsawn) and in micromodule form (on film). The M14C64 is available in micro-module
Wafer
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
SDA Serial Data/Address Input/ Output Serial Clock Write Control Supply Voltage Ground
SCL WC M14Cxx
SDA
SCL WC VCC GND
GND
AI02164
September 1998
Complete data available on Data-on-Disc CD-ROM or at www.st.com
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M14C64, M14C32
Figure 2. D20 Contact Connections Figure 3. D22 Contact Connections
VCC WC
GND
VCC WC
GND
SCL
SDA
SCL
SDA
AI02168
AI02204
form only. For availability of the M14C64 in wafer form, please contact your ST sales office. Each memory is compatible with the I2C extended memory standard. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 7-bit unique Device Type Identifier code (1010000) in accordance with the I2C bus definition. Only one memory can be attached to each I2C bus. The memory behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition, generated by the
bus master. The START condition is followed by the Device Select Code which is composed of a stream of 7 bits (1010000), plus one read/write bit (R/W) and is terminated by an acknowledge bit. When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ.
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M14C64, M14C32
Table 2. Ordering Information Scheme
Example 1: M14C64 W D22
Memory Capacity 64 32 64 Kbit 32 Kbit D22 D20
Delivery Form Module on Super 35 mm film (M14C64 only) Module on Super 35 mm film (M14C32 only)
Operating Voltage W 2.5 V to 5.5 V
Example 2:
M14C32
-
W
W2
Memory Capacity 32 32 Kbit W2 W4 Operating Voltage W 2.5 V to 5.5 V S2x S4x
Delivery Form Unsawn wafer (275 m 25 m thickness) Unsawn wafer (180 m 15 m thickness) Sawn wafer (275 m 25 m thickness) Sawn wafer (180 m 15 m thickness) GND at top right GND at bottom right GND at bottom left GND at top left
where "x" indicates the sawing orientation, as follows (and as shown in Figure 4) 1 2 3 4
Devices are shipped from the factory with the memory content set at all `1's (FFh). For a list of available options (speed, package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M14C64, M14C32
Figure 4. Sawing Orientation
VIEW: WAFER FRONT SIDE
GND
GND
GND
GND
ORIENTATION
1
2
3
4
AI02171
Sawn wafers are scribed and mounted in a frame on adhesive tape. The orientation is defined by the position of the GND pad on the die, viewed with active area of product visible, relative to the notches of the frame (as shown in Figure 4). The orientation of the die with respect to the plastic frame notches is specified by the Customer. One further concern, when specifying devices to be delivered in this form, is that wafers mounted on adhesive tape must be used within a limited period from the mounting date: - two months, if wafers are stored at 25C, 55% relative humidity - six months, if wafers are stored at 4C, 55% relative humidity
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