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HB56AW172E Series
1,048,576-word x 72-bit (ECC) High Density Dynamic RAM Module
ADE-203-252A (Z) Rev.1.0 Jun. 13, 1996 Description
The HB56AW172E belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56AW172E is a 1M x 72 dynamic RAM module, mounted 18 pieces of 4-Mbit DRAM (HM51W4400BTT) sealed in TSOP package and 2 pieces of 16-bit BiCMOS line driver (74LVT16244DGG) sealed in TSSOP package. An outline of the HB56AW172E is 168-pin socket type package (dual lead out). Therefore, the HB56AW172E makes high density mounting possible without surface mount technology. The HB56AW172E provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the its module board.
Features
* 168-pin socket type package (dual lead out) Lead pitch: 1.27 mm * Single 3.3 V (0.3 V) supply * High speed Access time: tRAC = 60/70/80 ns (max) Access time: tCAC = 20/25/25 ns (max) * Low power dissipation Active mode: 5.22/4.58/3.93 W (max) Standby mode (TTL): 166 mW (max) * Buffered input except RAS and DQ * 4 byte interleave enabled, dual address input (A0/B0) * Fast page mode capability * 1,024 refresh cycle: 16 ms
HB56AW172E Series
* 2 variations of refresh RAS-only refresh CAS-before-RAS refresh * TTL compatible
Ordering Information
Type No. HB56AW172E-6B HB56AW172E -7B HB56AW172E -8B Access time 60 ns 70 ns 80 ns Package 168-pin dual lead out socket type Contact pad Gold
Pin Arrangement
Front side Back side
1 pin 10 pin 11 pin 85 pin 94 pin 95 pin
40 pin 41 pin 124 pin 125 pin
84 pin 168 pin
Pin Arrangement
Pin No. 1 2 3 4 5 6 7 8 9 10 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 Pin No. 43 44 45 46 47 48 49 50 51 52 Pin name VSS OE2 RE2 CE4 NC WE2 VCC NC NC DQ18 Pin No. 85 86 87 88 89 90 91 92 93 94 Pin name VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 Pin No. 127 128 129 130 131 132 133 134 135 136 Pin name VSS NC NC NC NC PDE VCC NC NC DQ54
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HB56AW172E Series
Pin Arrangement (cont)
Pin No. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin name DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS NC NC VCC WE0 CE0 NC RE0 OE0 VSS A0 A2 A4 A6 A8 NC NC VCC NC NC Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin name DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 NC NC NC NC DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 VSS PD1 PD3 PD5 PD7 ID0 (VSS) VCC Pin No. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Pin name DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 VSS NC NC VCC NC NC NC NC NC VSS A1 A3 A5 A7 A9 NC NC VCC NC B0 Pin No. 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin name DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 NC NC NC NC DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID1 (VSS) VCC
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HB56AW172E Series
Pin Description
Pin name A0 to A9, B0 Function Address input: Row address: Column address: Refresh address: Data-in/Data-out Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground Presence detect ID bit Presence detect enable No connection A0 to A9, B0 A0 to A9, B0 A0 to A9, B0 A0 to A9, B0
DQ0 to DQ71 RE0, RE2 CE0, CE4 WE0, WE2 OE0, OE2 VCC VSS PD1 to PD8 ID0, ID1 PDE NC
Presence Detect Pin Assignment
PDE = Low Pin name PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 Pin No. 79 163 80 164 81 165 82 166 -6B 0 0 1 0 0 1 1 0 -7B 0 0 1 0 0 0 1 0 -8B 0 0 1 0 0 1 0 0 PDE = High All High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
Note: 1: High-Level (Driver Output) 0: Low Level (Driver Output)
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HB56AW172E Series
Block Diagram
RE0 CE0 WE0 OE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 A0 B0 A1 to A9 VCC VSS 0.10 F x 20 pcs 0.68 F x 4 pcs R0 R2 R4 CAS RAS WE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O R6 R7 R8 to R16 D0 OE DQ36 DQ37 DQ38 DQ39 OE DQ40 DQ41 DQ42 DQ43 OE DQ44 DQ45 DQ46 DQ47 OE DQ48 DQ49 DQ50 DQ51 OE DQ52 DQ53 DQ54 DQ55 OE DQ56 DQ57 DQ58 DQ59 OE DQ60 DQ61 DQ62 DQ63 OE DQ64 DQ65 DQ66 DQ67 OE DQ68 DQ69 DQ70 DQ71 PD1 to PD8 VCC or VSS PD1 to PD8 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RE2 CE4 WE2 OE2 R1 R3 R5 CAS RAS WE D9 OE
CAS RAS WE D1
CAS RAS WE D10
OE
CAS RAS WE D2
CAS RAS WE D11
OE
CAS RAS WE D3
CAS RAS WE D12
OE
CAS RAS WE D4
CAS RAS WE D13
OE
CAS RAS WE D5
CAS RAS WE D14
OE
CAS RAS WE D6
CAS RAS WE D15
OE
CAS RAS WE D7
CAS RAS WE D16
OE
CAS RAS WE D8
CAS RAS WE D17
OE
D0 to D8 D9 to D17 D0 to D17 D0 to D17, 74LVT16244 D0 to D17, 74LVT16244
* D0 to D17 : HM51W4400BTT : 74LVT16244DGG R0 to R7 : 33 R8 to R16 : 20
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HB56AW172E Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout Pt Topr Tstg Value -0.5 to +4.6 -0.5 to +4.6 50 19 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to 70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referenced to V SS . VIH VIL Min 0 3.0 2.4 -0.3 Typ 0 3.3 -- -- Max 0 3.6 VCC + 0.3 0.8 Unit V V V V 1 1 1 Note
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HB56AW172E Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V)
-6B Parameter Operating current Standby current Symbol Min I CC1 I CC2 -- -- Max -7B Min Max -8B Min Max Unit Test condition t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH CAS = VIL Dout = enable t RC = min t PC = min 0 V Vin 4.6 V 0 V Vout 4.6 V Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 2 1 Note 1, 2
1450 -- 46 --
1270 -- 46 --
1090 mA 46 mA
--
28
--
28
--
28
mA
RAS-only refresh current I CC3 Standby current I CC5
-- --
1450 -- 82 --
1270 -- 82 --
1090 mA 82 mA
CAS-before-RAS refresh I CC6 current Fast page mode current Input leakage current Output leakage current Output high voltage Output low voltage I CC7 I LI I LO VOH VOL
-- -- -10 -10 2.4 0
1450 -- 1270 -- 10 10 VCC 0.4 -10 -10 2.4 0
1270 -- 1090 -- 10 10 VCC 0.4 -10 -10 2.4 0
1090 mA 910 10 10 VCC 0.4 mA A A V V
Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (CAS, WE, OE ) Input capacitance (RAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI/O Typ -- -- -- -- Max 20 20 78 20 Unit pF pF pF pF Notes 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
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HB56AW172E Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) *1, *14, *15
Test Conditions * Input rise and fall times: 5 ns * Input timing reference levels: 0.8 V, 2.0 V * Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
-6B Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Refresh period Symbol Min t RC t RP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t ODD t DZO t DZC tT t REF 110 40 60 15 5 10 0 15 20 15 20 60 15 20 0 0 3 -- Max -- -- 10000 10000 -- -- -- -- 40 25 -- -- -- -- -- -- 50 16 -7B Min 130 50 70 20 5 10 0 15 20 15 25 70 15 25 0 0 3 -- Max -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 16 -8B Min 150 60 80 20 5 10 0 15 20 15 25 80 15 25 0 0 3 -- Max -- -- Unit Notes ns ns
10000 ns 10000 ns -- -- -- -- 55 35 -- -- -- -- -- -- 50 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7 17 8 9
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HB56AW172E Series
Read Cycle
-6B Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time OE pulse width Symbol Min t RAC t CAC t AA t OAC t RCS t RCH t RRH t RAL t OFF1 t OFF2 t CDD t OEP -- -- -- -- 0 0 0 35 0 0 20 15 Max 60 20 35 20 -- -- -- -- 20 20 -- -- -7B Min -- -- -- -- 0 0 0 40 0 0 25 20 Max 70 25 40 25 -- -- -- -- 25 25 -- -- -8B Min -- -- -- -- 0 0 0 45 0 0 25 20 Max 80 25 45 25 -- -- -- -- 25 25 -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns 6 6 16 16 2, 3 3, 4, 13 3, 5, 13 3
Write Cycle
-6B Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH 0 15 10 20 15 0 20 Max -- -- -- -- -- -- -- -7B Min 0 15 10 25 20 0 20 Max -- -- -- -- -- -- -- -8B Min 0 15 10 25 20 0 20 Max -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 11 11 10
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HB56AW172E Series
Read-Modify-Write Cycle
-6B Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min t RWC t RWD t CWD t AWD t OEH 150 85 35 50 15 Max -- -- -- -- -- -7B Min 180 100 45 60 20 Max -- -- -- -- -- -8B Min 200 110 45 65 20 Max -- -- -- -- -- Unit Notes ns ns ns ns ns 10 10 10
Refresh Cycle
-6B Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time WE hold time RAS precharge to CAS hold time CAS precharge time in normal mode Symbol Min t CSR t CHR t WS t WH t RPC t CPN 15 10 5 10 10 10 Max -- -- -- -- -- -- -7B Min 15 10 5 10 10 10 Max -- -- -- -- -- -- -8B Min 15 10 5 10 10 10 Max -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns
Fast Page Mode Cycle
-6B Parameter Fast page mode cycle time CAS precharge time Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Symbol Min t PC t CP t RASC t ACP t RHCP 40 10 -- -- 40 Max -- -- -7B Min 45 10 Max -- -- -8B Min 50 10 Max -- -- Unit Notes ns ns 12 3, 13
100000 -- 40 -- -- 45
100000 -- 45 -- -- 50
100000 ns 50 -- ns ns
10
HB56AW172E Series
Fast Page Mode Read-Modify-Write Cycle
-6B Parameter Fast page mode read-modify-write cycle time WE delay time from CAS precharge Symbol Min t PCM t CPW 80 55 Max -- -- -7B Min 95 65 Max -- -- -8B Min 100 70 Max -- -- Unit Notes ns ns 10
Notes: 1. AC measurements assume t T = 5 ns. 2. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 4. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 5. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 6. t OFF (max) defines the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modifywrite and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 12. t RASC defines RAS pulse width in Fast page mode cycles. 13. Access time is determined by the longer of t AA or tCAC or tACP . 14. An initial pause of 100 s is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS-before-RAS refresh cycle). If the internal refresh counter is used, aminimum of eight CAS-before-RAS refresh cycle is reguired. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either t RCH or tRRH must be satisfied. 17. t REF is determined by 1,204 refresh cycle.
Timing Waveform
Refer to the HB56G236B/SB Series.
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HB56AW172E Series
Physical Outline
133.35 5.250 3.00 0.118 127.35 5.014
Unit: mm/inch
4.00 max. 0.157 max
4.00 min. 0.157 min.
3.00 0.118
1
84
C 8.89 0.350 11.43 0.450 36.83 1.450
B 54.61 2.150
A 1.270.10 0.0500.004
2- 3.00 2- 0.118
4.00 0.157 17.78 0.700
168 85
Detail A
2.54 min. 0.100 min.
Detail B and C 1.000.05 0.0390.002
0.25 max. 0.010 max.
1.27 0.050
12
3.1250.125 0.1230.005
6.35 0.250 2.000.10 0.0790.004
25.40 1.000
HB56AW172E Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
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Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
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