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HB56AW873E Series
8,388,608-word x 72-bit High Density Dynamic RAM Module 168-pin JEDEC Standard Outline Buffered 8 byte DIMM
ADE-203-685A (Z) Rev. 1.0 Nov. 28, 1996
Description
The HB56AW873E belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56AW873E is a 8M x 72 dynamic RAM module, mounted 9 pieces of 64-Mbit DRAM (HM5165800ATT) sealed in TSOP package and 2 pieces of 16-bit BiCMOS line driver (74LVT16244) sealed in TSSOP package. An outline of the HB56AW873E is 168-pin socket type package (dual lead out). Therefore, the HB56AW873E makes high density mounting possible without surface mount technology. The HB56AW873E provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the its module board.
Features
* * * 168-pin socket type package (Dual lead out) Lead pitch: 1.27 mm Single 3.3 V (0.3 V) supply High speed Access time: tRAC = 60/70 ns (max) Access time: tCAC = 20/23 ns (max) Low power dissipation Active mode: 4.73/4.41 W (max) Standby mode (TTL): 100 mW (max) Buffered input except RAS and DQ 4 byte interleave enabled, dual address input (A0/B0) Fast page mode capability 4,096 refresh cycle: 64 ms 2 variations of refresh RAS-only refresh CAS-before-RAS refresh TTL compatible
*
* * * * *
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HB56AW873E Series
Ordering Information
Type No. HB56AW872E-6A HB56AW872E-7A Access time 60 ns 70 ns Package 168-pin dual lead out socket type Contact pad Gold
Pin Arrangement
Front side Back side
1 pin 10 pin 11 pin 85 pin 94 pin 95 pin
40 pin 41 pin 124 pin 125 pin
84 pin 168 pin
Pin Arrangement
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 49 50 51 52 53 54 Pin Name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS VCC NC NC DQ18 DQ19 VSS Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 79 80 81 82 83 84 Pin Name DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS NC PD1 PD3 PD5 PD7 ID0 (VSS) VCC Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 109 110 111 112 113 114 Pin Name NC VCC WE0 CE0 NC RE0 OE0 VSS A0 A2 A4 A6 NC VCC NC NC NC NC Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 139 140 141 142 143 144 Pin Name A8 A10 NC VCC NC NC VSS OE2 RE2 CE4 NC WE2 DQ56 DQ57 DQ58 DQ59 VCC DQ60
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HB56AW873E Series
Pin Arrangement (cont)
Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Pin Name DQ20 DQ21 DQ22 DQ23 VCC DQ24 NC NC NC NC DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 VSS Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin Name VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 VSS NC Pin No. 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Pin Name NC VSS A1 A3 A5 A7 A9 A11 NC VCC NC B0 VSS NC NC NC NC PDE VCC NC NC DQ54 DQ55 VSS Pin No. 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin Name NC NC NC NC DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID1 (VSS) VCC
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HB56AW873E Series
Pin Description
Pin Name A0 to A11, B0 Function Address Input (D0 to D8) : Row Address (D0 to D8) : Column Address (D0 to D8) : Refresh Address (D0 to D8) : Data-in/Data-out Row Address Strobe (RAS) Column Address Strobe (CAS) Read/Write Enable Output Enable Power Supply Ground Presence Detect ID bit Presence Detect Enable Non Connection A0 to A11, B0 A0 to A11, B0 A0 to A10, B0 A0 to A11, B0
DQ0 to DQ71 RE0, RE2 CE0, CE4 WE0, WE2 OE0, OE2 VCC VSS PD1 to PD8 ID0, ID1 PDE NC
Presence Detect Pin Assignment
PDE = Low Pin Name PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 Pin No. 79 163 80 164 81 165 82 166 60 ns 1 0 1 1 0 1 1 0 70 ns 1 0 1 1 0 0 1 0 PDE = High All High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
1 : High Level (Driver Output) 0 : Low Level (Driver Output)
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HB56AW873E Series
Block Diagram
RE0 CE0 WE0 OE0 CAS RAS WE I/O I/O I/O D0 I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D1 I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D2 I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D3 I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D4 I/O I/O I/O I/O I/O OE DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 OE DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 OE DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 OE DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 OE RE2 CE4 WE2 OE2 CAS RAS I/O I/O I/O I/O I/O I/O I/O I/O WE OE
DQ36 DQ37 DQ38 DQ39 DQ0 DQ1 DQ2 DQ3
D5
DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11
CAS RAS WE I/O I/O I/O D6 I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D7 I/O I/O I/O I/O I/O CAS RAS WE I/O I/O I/O D8 I/O I/O I/O I/O I/O
OE
OE
DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19
OE
DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27
DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35
PD1 to PD8 VCC VSS VCC VCC PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8
A0 B0 A1 to A11 VCC VSS 0.22 F x 11 pcs
D0 to D4 D5 to D8 D0 to D8 D0 to D8, 74LVT16244 D0 to D8,74LVT16244
VSS VCC VSS VCC VSS VSS
* D0 to D8
: HM5165800 : 74LVT16244
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HB56AW873E Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout Pt Topr Tstg Value -0.5 to +4.6 -0.5 to +4.6 50 10 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to 70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referenced to V SS . VIH VIL Min 0 3.0 2.0 -0.5 Typ 0 3.3 -- -- Max 0 3.6 VCC + 0.3 0.8 Unit V V V V 1 1 1 Note
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HB56AW873E Series
DC Characteristics (Ta = 0 to 70C, VCC = 3.3 V 0.3 V, VSS = 0 V)
60 ns Parameter Operating current Standby current Symbol Min I CC1 I CC2 -- -- Max 1675 28 70 ns Min -- -- Max 1495 28 Unit mA mA Test condition t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t PC = min 0 V Vin 4.6 V 0 V Vout 4.6 V Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 2 1 Note 1, 2
--
19
--
19
mA
RAS-only refresh current Standby current CAS-before-RAS refresh current
I CC3 I CC5 I CC6
-- -- -- -- -10 -10 2.4 0
1675 55 1360 1135 10 10 VCC 0.4
-- -- -- -- -10 -10 2.4 0
1495 55 1180 1045 10 10 VCC 0.4
mA mA mA mA A A V V
Fast page mode current I CC7 Input leakage current I LI
Output leakage current I LO Output high voltage Output low voltage VOH VOL
Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tPC.
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (CAS, WE, OE) Input capacitance (RAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI/O Typ -- -- -- -- Max 20 20 55 20 Unit pF pF pF pF Notes 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
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HB56AW873E Series
AC Characteristics (Ta = 0 to 70C, VCC = 3.3 V 0.3 V, VSS = 0 V)*1, *2, *18
Test Conditions * * * * * Input rise and fall times: 5 ns Input levels: VIL = 0 V, V IH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HB56AW873E 60 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Refresh period (4,096 cycle) Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT t REF Min 110 40 10 60 15 5 10 0 10 20 15 20 60 10 20 0 0 3 -- Max -- -- -- 10000 10000 -- -- -- -- 40 25 -- -- -- -- -- -- 50 64 70 ns Min 130 50 10 70 18 5 10 0 15 20 15 23 70 10 23 0 0 3 -- Max -- -- -- 10000 10000 -- -- -- -- 47 30 -- -- -- -- -- -- 50 64 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 5 6 6 7 3 4 Notes
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HB56AW873E Series
Read Cycle
HB56AW873E 60 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Symbol t RAC t CAC t AA t OEA t RCS t RCH t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD Min -- -- -- -- 0 0 0 35 30 2 3 3 -- -- 20 Max 60 20 35 20 -- -- -- -- -- -- -- -- 20 20 -- 70 ns Min -- -- -- -- 0 0 0 40 35 2 3 3 -- -- 23 Max 70 23 40 23 -- -- -- -- -- -- -- -- 20 20 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12 12 Notes 8, 9 9, 10, 16 9, 11, 16 9, 19
Write Cycle
HB56AW873E 60 ns Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 10 10 20 15 0 15 Max -- -- -- -- -- -- -- 70 ns Min 0 15 10 23 18 0 18 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns Notes 14
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HB56AW873E Series
Read-Modify-Write Cycle
HB56AW873E 60 ns Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol t RWC t RWD t CWD t AWD t OEH Min 155 90 40 55 15 Max -- -- -- -- -- 70 ns Min 181 103 46 63 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
Refresh Cycle
HB56AW873E 60 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol t CSR t CHR t WRP t WRH t RPC Min 10 10 5 10 0 Max -- -- -- -- -- 70 ns Min 10 10 5 10 0 Max -- -- -- -- -- Unit ns ns ns ns ns Notes
Fast Page Mode Cycle
HB56AW873E 60 ns Parameter Fast page mode cycle time Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Symbol t PC t RASP t CPA t CPRH Min 40 -- -- 40 Max -- 70 ns Min 45 Max -- Unit ns 15 9, 16 Notes
100000 -- 40 -- -- 45
100000 ns 45 -- ns ns
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HB56AW873E Series
Fast Page Mode Read-Modify-Write Cycle
HB56AW873E 60 ns Parameter Symbol Min 85 60 Max -- -- 70 ns Min 96 68 Max -- -- Unit ns ns 14 Notes
Fast page mode read-modify-write cycle t HPRWC time WE delay time from CAS precharge t CPW
Notes: 1. AC measurements assume tT = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min), and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t RASP defines RAS pulse width in Fast page mode cycles. 16. Access time is determined by the longest among t AA , t CAC and t CPA. 17. All the V CC and VSS pin shall be supplied with the same voltages. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When output buffers are enable once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a vary short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 20. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL.
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HB56AW873E Series
Timing Waveform *20
Refer to the HB56AW1672E Series.
Physical Outline
133.35 5.250 3.00 0.118 127.35 5.014
Unit: mm/inch
4.00 max. 0.157 max
3.00 0.118
1
84
B 8.89 0.350 11.43 0.450 36.83 1.450
B 54.61 2.150
A 1.270.10 0.050.004
2- 3.00 2- 0.118
4.00 0.157
17.78 0.700
4.00 min. 0.157 min.
Detail A Detail B 1.000.05 0.0390.002
2.54 min. 0.100 min.
0.25 max. 0.010 max.
3.1250.125 0.1230.005
6.35 0.250 2.000.10 0.0790.004
1.27 0.050
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31.75 1.250
168
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HB56AW873E Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
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HB56AW873E Series
Revision Record
Rev. 1.0 Date Nov. 28, 1996 Contents of Modification Initial issue Drawn by Approved by
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