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HB56HW164DB Series, HB56HW165DB Series
1,048,576-word x 64-bit High Density Dynamic RAM Module
ADE-203-699A (Z) Rev.1.0 Dec. 27, 1996 Description
The HB56HW164DB is a 1M x 64 dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 4 pieces of 16-Mbit DRAM (HM51W16165) sealed in TSOP package and 1 pieces of serial EEPROM (24C02) for Presence Detect (PD). The HB56HW165DB is a 1M x 64 dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 4 pieces of 16-Mbit DRAM (HM51W18165) sealed in TSOP package and 1 pieces of serial EEPROM (24C02) for Presence Detect (PD). The HB56HW164DB, HB56HW165DB offer Extended Data Out (EDO) Page Mode as a high speed access mode. An outline of the HB56HW164DB, HB56HW165DB is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, the HB56HW164DB, HB56HW165DB make high density mounting possible without surface mount technology. The HB56HW164DB, HB56HW165DB provide common data inputs and outputs. Decoupling capacitors are mounted on the module board.
Features
* 144-pin Zig Zag Dual tabs socket type Outline: 67.60 mm (Length) x 25.40 mm (Height) x 3.80 mm (Thickness) Lead pitch: 0.80 mm * Single 3.3 V (0.3 V) supply * High speed Access time: tRAC = 60/70 ns (max) tCAC = 15/18 ns (max) * Low power dissipation Active mode: 1.44/1.30 W (max) (HB56HW164DB Series) 2.45/2.16 W (max) (HB56HW165DB Series) Standby mode (TTL): 28.8 mW (max) (CMOS): 2.16 mW (max) (L-version) * EDO page mode capability
HB56HW164DB Series, HB56HW165DB Series
* Refresh period 4096 refresh cycles: 64 ms (HB56HW164DB Series) 128 ms (L-version) 1024 refresh cycles: 16 ms (HB56HW165DB Series) 128 ms (L-version) * 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version)
Ordering Information
Type No. HB56HW164DB-6 HB56HW164DB-7 HB56HW164DB-6L HB56HW164DB-7L HB56HW165DB-6 HB56HW165DB-7 HB56HW165DB-6L HB56HW165DB-7L Access time 60 ns 70 ns 60 ns 70 ns 60 ns 70 ns 60 ns 70 ns Package 144-pin small outline DIMM Contact pad Gold
Pin Arrangement
--Front Side--
1 pin 2 pin
59 pin 60 pin
61 pin 62 pin
143 pin 144 pin
--Back Side--
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HB56HW164DB Series, HB56HW165DB Series
Pin Arrangement
Front side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS CE0 CE1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS NC NC NC VCC NC Pin No. 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 Pin name OE VSS NC NC VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC A6 A8 VSS A9 A10 (NC)* VCC CE2 CE3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31
1
Back side Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 Pin name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS CE4 CE5 VCC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VCC DQ44 DQ45 DQ46 DQ47 VSS NC NC NC VCC NC Pin No. 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 Pin name NC VSS NC NC VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VCC A7 A11 (NC)*2 VSS NC NC VCC CE6 CE7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63
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HB56HW164DB Series, HB56HW165DB Series
Pin Arrangement (cont)
Front side Pin No. 67 69 71 Pin name WE RE0 NC Pin No. 139 141 143 Pin name VSS SDA VCC Back side Pin No. 68 70 72 Pin name NC NC NC Pin No. 140 142 144 Pin name VSS SCL VCC
Notes: 1. A10: HB56HW164DB, NC: HB56HW165DB 2. A11: HB56HW164DB, NC: HB56HW165DB
Pin Description
Pin name A0 to A11 (HB56HW164DB) Function Address inputs: Row address: Column address: Refresh address: A0 to A9 (HB56HW165DB) Address inputs: Row address: Column address: Refresh address: DQ0 to DQ63 RE0 CE0 to CE7 WE OE VCC VSS SDA SCL NC Data-in/Data-out Row address strobe (RAS) column address strobe (CAS) Read/Write enable Output enable Power supply Ground Serial data for PD Serial clock for PD No connection A0 to A9 A0 to A9 A0 to A9 A0 to A11 A0 to A7 A0 to A11
4
HB56HW164DB Series, HB56HW165DB Series
Serial PD Matrix (HB56HW164DB)*1
Byte number Function described 0 1 2 3 4 5 6 7 8 9 Number serial PD bytes Serial memory Fundamental memory type Number of rows Number of columns Number of banks Data width Data width (continued) Voltage interface RAS access time 60 ns 70 ns 10 CAS access time 15 ns 18 ns 11 12 Error detection/corraction Refresh period Refresh period (L-version) Note: Bit7 0 0 0 0 0 0 0 0 0 Bit6 0 0 0 0 0 0 1 0 0 Bit5 0 0 0 0 0 0 0 0 0 Bit4 0 0 0 0 0 0 0 0 0 Bit3 1 1 0 1 1 0 0 0 0 Bit2 1 0 0 1 0 0 0 0 0 Bit1 0 0 1 0 0 0 0 0 0 Bit0 1 0 0 0 0 1 0 0 1 Comments 13 256 bytes EDO 12 8 1 64 0 (+) LVTTL (3.3V)
0 0 0 0 0 0 1
0 1 0 0 0 0 0
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 0 0
1 1 1 0 0 0 0
0 1 1 1 0 0 1
0 0 1 0 0 0 1 None Normal (15.625 s) Self refresh (31.3s)
1. Serial-PD data are not protected. 1: High level (serial data) 0: Low level (serial data)
5
HB56HW164DB Series, HB56HW165DB Series
Serial PD Matrix (HB56HW165DB)*1
Byte number Function described 0 1 2 3 4 5 6 7 8 9 Number serial PD bytes Serial memory Fundamental memory type Number of rows Number of columns Number of banks Data width Data width (continued) Voltage interface RAS access time 60 ns 70 ns 10 CAS access time 15 ns 18 ns 11 12 Error detection/corraction Refresh period Refresh period (L-version) Note: Bit7 0 0 0 0 0 0 0 0 0 Bit6 0 0 0 0 0 0 1 0 0 Bit5 0 0 0 0 0 0 0 0 0 Bit4 0 0 0 0 0 0 0 0 0 Bit3 1 1 0 1 1 0 0 0 0 Bit2 1 0 0 0 0 0 0 0 0 Bit1 0 0 1 1 1 0 0 0 0 Bit0 1 0 0 0 0 1 0 0 1 Comments 13 256 bytes EDO 10 10 1 64 0 (+) LVTTL (3.3V)
0 0 0 0 0 0 1
0 1 0 0 0 0 0
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 0 0
1 1 1 0 0 0 1
0 1 1 1 0 0 0
0 0 1 0 0 0 1 None Normal (15.625 s) Self refresh (125 s)
1. Serial-PD data are not protected. 1: High level (serial data) 0: Low level (serial data)
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HB56HW164DB Series, HB56HW165DB Series
Block Diagram
RE0 WE OE RAS CE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UCAS I/O I/O I/O I/O I/O I/O I/O I/O LCAS I/O I/O I/O I/O I/O I/O I/O I/O WE OE CE4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CE5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 RAS LCAS I/O I/O I/O I/O I/O I/O I/O I/O UCAS I/O I/O I/O I/O I/O I/O I/O I/O WE OE
D0
D2
RAS CE2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CE3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UCAS I/O I/O I/O I/O I/O I/O I/O I/O LCAS I/O I/O I/O I/O I/O I/O I/O I/O
WE
OE CE6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CE7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
RAS LCAS I/O I/O I/O I/O I/O I/O I/O I/O UCAS I/O I/O I/O I/O I/O I/O I/O
WE
OE
D1
D3
SDA SCL VCC
SDA SCL NC VCC
U0
VSS A2 A1 A0
A0 to An VCC VSS 0.22 F x 6 pcs
A0 to An (D0 to D3) VCC (D0 to D3, U0) VSS (D0 to D3, U0)
* D0 to D3 U0
: HM51W16165 (HB56HW164DB) : HM51W18165 (HB56HW165DB) : 24C02
7
HB56HW164DB Series, HB56HW165DB Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout Pt Topr Tstg Value -0.5 to +4.6 -0.5 to +4.6 50 4 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to 70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to VSS . VIH VIL Min 0 3.0 2.0 -0.3 Typ 0 3.3 -- -- Max 0 3.6 VCC +0.3 0.8 Unit V V V V 1 1 1 Note
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HB56HW164DB Series, HB56HW165DB Series
DC Characteristics (Ta = 0 to 70C, VCC = 3.3 V 0.3V, VSS = 0 V) (HB56HW164DB)
60 ns Parameter Operating current Standby current Symbol Min ICC1 ICC2 -- -- 70 ns Max Min 400 8 -- -- Max Unit 360 8 mA mA Test conditions tRC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z tRC = min RAS = VIH, CAS = VIL Dout = enable tRC = min tHPC = min CMOS interface Dout = High-Z CBR refresh: tRC = 31.3 s tRAS 0.3 s CMOS interface RAS, CAS 0.2 V Dout = High-Z 0 V Vin 4.6 V 0 V Vout 4.6 V Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 4 2 1 Notes 1, 2
--
4
--
4
mA
Standby current (L-version)
ICC2
--
0.6
--
0.6
mA
RAS-only refresh current Standby current CAS-before-RAS refresh current EDO page mode current
ICC3 ICC5 ICC6 ICC7
-- -- -- -- --
400 20 400 520 1.6
-- -- -- -- --
360 20 360 460 1.6
mA mA mA mA mA
Battery backup current ICC10 (Standby with CBR refresh) (Lversion)
Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
ICC11
--
1
--
1
mA
ILI ILO VOH VOL
-10 -10 2.4 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
A A V V
Notes: 1. ICC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V
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HB56HW164DB Series, HB56HW165DB Series
DC Characteristics (Ta = 0 to 70C, VCC = 3.3 V 0.3V, VSS = 0 V) (HB56HW165DB)
60 ns Parameter Operating current Standby current Symbol Min ICC1 ICC2 -- -- 70 ns Max Min 680 8 -- -- Max Unit 600 8 mA mA Test conditions tRC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z tRC = min RAS = VIH, CAS = VIL Dout = enable tRC = min tHPC = min CMOS interface Dout = High-Z CBR refresh: tRC = 125 s tRAS 0.3 s CMOS interface RAS, CAS 0.2 V Dout = High-Z 0 V Vin 4.6 V 0 V Vout 4.6 V Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 4 2 1 Notes 1, 2
--
4
--
4
mA
Standby current (L-version)
ICC2
--
0.6
--
0.6
mA
RAS-only refresh current Standby current CAS-before-RAS refresh current EDO page mode current
ICC3 ICC5 ICC6 ICC7
-- -- -- -- --
680 20 680 740 1.6
-- -- -- -- --
600 20 600 660 1.6
mA mA mA mA mA
Battery backup current ICC10 (Standby with CBR refresh) (Lversion)
Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
ICC11
--
1
--
1
mA
ILI ILO VOH VOL
-10 -10 2.4 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
A A V V
Notes: 1. ICC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V
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HB56HW164DB Series, HB56HW165DB Series
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (RAS, WE, OE ) Input capacitance (CAS) I/O capacitance (DQ) Symbol CI! CI2 CI3 CI/O Typ -- -- -- -- Max 40 48 22 17 Unit pF pF pF pF Notes 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to 70C, VCC = 3.3 V 0.3 V, VSS = 0 V) *1, *2, *18, *19
Test Conditions * * * * * Input rise and fall times: 2 ns Input levels: 0 V, 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
11
HB56HW164DB Series, HB56HW165DB Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
60 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Refresh period (HB56HW164DB: 4,096 cycles) Refresh period (HB56HW164DB: 4,096 cycles) (L-version) Refresh period (HB56HW165DB: 1,024 cycles) Refresh period (HB56HW165DB: 1,024 cycles) (L-version) Symbol tRC tRP tCP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tOED tDZO tDZC tT tREF tREF tREF tREF Min 104 40 10 60 10 0 10 0 10 20 15 15 40 5 15 0 0 2 -- -- -- -- Max -- -- -- 70 ns Min 124 50 13 Max -- -- -- Unit ns ns ns Notes
10000 70 10000 13 -- -- -- -- 45 30 -- -- -- -- -- -- 50 64 128 16 128 0 10 0 13 20 15 18 45 5 18 0 0 2 -- -- -- --
10000 ns 10000 ns -- -- -- -- 52 35 -- -- -- -- -- -- 50 64 128 16 128 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ms 5 6 6 7 3 4
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HB56HW164DB Series, HB56HW165DB Series
Read Cycle
60 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off time to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time RAS next CAS delay time Symbol tRAC tCAC tAA tOEA tRCS tRCH tRCHR tRRH tRAL tCAL tCLZ tOH tOHO tOFF tOEZ tCDD tOHR tOFR tWEZ tWED tRDD tRNCD Min -- -- -- -- 0 0 60 5 30 18 0 3 3 -- -- 15 3 -- -- 15 15 60 Max 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -- 70 ns Min -- -- -- -- 0 0 70 5 35 23 0 3 3 -- -- 18 3 -- -- 18 18 70 Max 70 18 35 18 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 22 13 5 22 22 22 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9, 21
13
HB56HW164DB Series, HB56HW165DB Series
Write Cycle
60 ns Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol tWCS tWCH tWP tRWL tCWL tDS tDH Min 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- 70 ns Min 0 13 10 13 13 0 13 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14
Read-Modify-Write Cycle
60 ns Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time WE Symbol tRWC tRWD tCWD tAWD tOEH Min 136 79 34 49 15 Max -- -- -- -- -- 70 ns Min 161 92 40 57 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
Refresh Cycle
60 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol tCSR tCHR tRPC Min 5 10 0 Max -- -- -- 70 ns Min 5 10 0 Max -- -- -- Unit ns ns ns Notes
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HB56HW164DB Series, HB56HW165DB Series
EDO Page Mode Cycle
60 ns Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hole time from CAS low CAS hold time refferred OE CAS to OE setup time Read command hold time from CAS precharge Symbol tHPC tRASP tCPA tCPRH tDOH tCOL tCOP tRCHC Min 25 -- -- 35 3 10 5 35 Max -- 70 ns Min 30 Max -- Unit ns Notes 20 16 9, 17
100000 -- 35 -- -- -- -- -- -- 40 3 13 5 40
100000 ns 40 -- -- -- -- -- ns ns ns ns ns ns
9, 17
EDO Page Mode Read-Modify-Write Cycle
60 ns Parameter EDO page mode read-modify-write cycle time WE delay time from CAS precharge Symbol tHPRWC tCPW Min 68 54 Max -- -- 70 ns Min 79 62 Max -- -- Unit ns ns 14 Notes
Self Refresh Mode (L-version)
60 ns Parameter RAS pulse width (Self refresh) RAS precharge time (Self refresh) CAS hold time (Self refresh) Symbol tRASS tRPS tCHS Min 100 110 -50 Max -- -- -- 70 ns Min 100 130 -50 Max -- -- -- Unit s ns ns Notes
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HB56HW164DB Series, HB56HW165DB Series
Notes: 1. AC measurements assume tT = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD tRAD (max) + tAA (max)- tCAC (max), then access time is controlled exclusively by tCAC. 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either tOED or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that tRCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that tRAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. tWCS , tRWD, tCWD, tAWD, and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics onry; if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min) or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. tRASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among tAA , tCAC and tCPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH tCWL, the DQ pin will remain open circuit (high impedance); tOEH < tOEH, invalid data will be out at each DQ. 19. All the VCC and VSS pins shall be supplied with the same voltages. 20. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2tT) becomes greater than the specified tHPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC / VSS line noise, which causes to degrade VIH min./ VIL max level. 22. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between tOHR and tOH, and between tOFR and tOFF.
16
HB56HW164DB Series, HB56HW165DB Series
23. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS 100 s, then RAS precharge time should use tRPS instead of tRP. 24. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 25. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 1024 cycles (4096 cycles: HB56HW164DB Series, 1024 cycles: HB56HW165DB Series) of distributed CBR refresh with 15.6 s interval should be executed within 64 or 16 ms (64 ms: HB56HW164DB Series, 16 ms: HB56HW165DB Series) immediately after exiting from and before entering into the self refresh mode. 26. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 27. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
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HB56HW164DB Series, HB56HW165DB Series
Notes concerning 2CAS control
Please do not separate the 2CASs (CAS0 and CAS1 (or CAS2, CAS4, CAS6 and CAS3, CAS5, CAS7)) operation timing intentionally. However skew between 2CASs are allowed under the following conditions. 1. Each of the 2CASs should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed: such as following.
RAS CAS0 (CAS2, CAS4, CAS6) CAS1 (CAS3, CAS5, CAS7) Early write Delayed write
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP tUL) is satisfied, page mode can be performed.
RAS
CAS0 (CAS2, CAS4, CAS6) CAS1 (CAS3, CAS5, CAS7) t UL
4. Byte control operation by remaining CAS0 (CAS2, CAS4, CAS6) or CAS1 (CAS3, CAS5, CAS7) high is guaranteed.
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HB56HW164DB Series, HB56HW165DB Series
Timing Waveforms*27
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS
t RAD t ASR t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCHR t RCS t RCH
WE t WED t DZC t CDD t RDD Din High-Z
t DZO
t OEA
t OED
OE t OEZ t OHO t OFF t OH t OFR t OHR t WEZ Dout Dout
t CAC t AA t RAC t CLZ
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HB56HW164DB Series, HB56HW165DB Series
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT CAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z* * t WCS t WCS (min)
20
HB56HW164DB Series, HB56HW165DB Series
Delayed Write Cycle*18
t RC t RAS
t RP
RAS t CSH t RCD tT CAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
Address
Row
Column t CWL t RCS t RWL t WP
WE
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED
t DZO

OE t OEZ t CLZ Dout High-Z Invalid Dout 21
HB56HW164DB Series, HB56HW165DB Series
Read-Modify-Write Cycle*18
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
CAS t RAD t ASR t RAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
WE t DZC t DS Din
High-Z Din
t DH
t DZO
t OED t OEA
t OEH
OE t CAC t AA t RAC t OEZ t OHO
High-Z
Dout t CLZ
Dout
22
HB56HW164DB Series, HB56HW165DB Series
RAS-Only Refresh Cycle
t RC t RAS RAS tT t CRP t RPC t CRP t RP
CAS
t ASR Address t OFR t OFF Dout Row
t RAH
High-Z
23
HB56HW164DB Series, HB56HW165DB Series
CAS-Before-RAS Refresh Cycle
t RC t RP t RAS t RP t RAS t RC t RP
RAS tT t RPC t CP t CSR t CHR t RPC t CP t CRP t CSR t CHR

Address t OFR t OFF Dout High-Z 24
CAS
HB56HW164DB Series, HB56HW165DB Series
Hidden Refresh Cycle
t RC t RAS t RC t RAS t RC t RP t RAS t RP
t RP
RAS tT t RSH t RCD t CHR t CRP
CAS
t RAD t ASR t RAH Address Row t ASC t RAL t CAH
Column
t RCS WE
t RRH t RCH
t DZC High-Z Din
t WED t CDD t RDD
t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout t OFR t OHR
t OED
t OFF t OH
t OEZ t WEZ t OHO
25
HB56HW164DB Series, HB56HW165DB Series
EDO Page Mode Read Cycle
t RP t RASP tT CAS t RCS
WE
t RNCD
RAS
t HPC t HPC tCAS t RCHC t CPRH t CP t t CRP
t CSH t CAS t RCHR
t CP
t HPC t CAS
t CP
RSH
tCAS t RRH t RCH
t RCH t RCS
tASR
Address
tRAH tASC Row
tCAH
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL tRDD tCDD
Din
High-Z tDZO tCOL tCOP tOED

OE
tOEA
tCPA
tCPA
tCAC tAA
tAA tCAC
tOEZ
tWEZ
tOHO
tCPA tAA tCAC
tAA
tOEZ
tOFR tOHR tOEZ
tCAC
tRAC
tOEA
tDOH
tOHO
tOEA
tOHO tOFF tOH
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
26
HB56HW164DB Series, HB56HW165DB Series
EDO Page Mode Early Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
CAS
t ASR t RAH
t ASC
t CAH
t ASC
tCAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z*
* t WCS
t WCS (min)
27
HB56HW164DB Series, HB56HW165DB Series
EDO Page Mode Delayed Write Cycle*18
t RASP t RP RAS tT t CSH t RCD t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
CAS
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL

t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z
Invalid Dout Invalid Dout Invalid Dout
28
HB56HW164DB Series, HB56HW165DB Series
EDO Page Mode Read-Modify-Write Cycle*18
t RASP t RP RAS tT t CP t RCD t CAS t CAS t HPRWC t CP t RSH t CAS
t CRP
CAS
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO
t OED
t ASC t CAH Column 2 t CWL t RCS t CPW t AWD t CWD t RCS t CWL
t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
t WP t DZC t DS t DH Din 2 t OED t OEH t DZO t OED
t WP t DZC t DS t DH Din N
Din 1 t DZO t OEH
t OEH
*
OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
29
HB56HW164DB Series, HB56HW165DB Series
EDO Page Mode Mix Cycle (1)
t RP RAS tT CAS t RCD t WCS WE t ASC tRAH Row t WCH t RCS tCPW tAWD tCAH t ASC t CAH Column 2 t CAL t DS
Din
t RASP t CRP tCAS tRSH t RCS tWP t RAL t CAH Column 4 t CAL t DS High-Z tOED t DH Din 3 tWED tRDD tCDD t RRH t RCH
t CP t CAS t CSH t CAS
t CP tCAS
t CP
tASR Address
tASC t CAH Column 3
tASC
Column 1
t DH Din 1

tCPA tAA tOEA tCPA tCPA tAA t OEZ tAA tOFR tWEZ tOEZ tCAC tOHO tOFF tOH tCAC t DOH tCAC t OHO tOEA Dout Dout 2
Dout 3
OE
Dout 4
30
HB56HW164DB Series, HB56HW165DB Series
EDO Page Mode Mix Cycle (2)
t RP t RASP
t RNCD
RAS
tT CAS
t CSH t CAS t RCD t RCS t RCHR
t CP t CAS
t CP tCAS
t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 tOED tCOP tRSH
t CRP
t RCH tWCS t WCH
t RCS
t RRH t RCH
WE
tASR
Address
tRAH Row
t ASC
tCAH
t ASC t CAH Column 2
t ASC t CAH Column 3 t CAL
Column 1 t CAL
t DS
Din
t DH Din 2
tRDD tCDD
High-Z
tOED
OE
tWED
tCOL t OEA tOEZ t OHO tCPA tAA tCAC tOEZ t OHO
Dout 3
tAA tOEA tCAC tRAC
tCPA tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
Dout
Dout 1
31
HB56HW164DB Series, HB56HW165DB Series
Self Refresh Cycle (L-version)* 23, 24, 25, 26
t RASS
t RP
t RPS
RAS tT t RPC t CP t CRP t CHS t CSR
+ * $
t OFR t OFF Dout High-Z 32
,
CAS
HB56HW164DB Series, HB56HW165DB Series
Physical Outline
Unit: mm/inch
67.60 2.661 24.50 0.965
,,,,,,,,,,,,,,,,,,,,,,,,, 2R0.118Min. ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,, (front) ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,
23.20 0.913 2.50 0.098 B 32.80 4.60 1.291 0.181 A
143 1
63.60 2.504 (Datum -A-)
3.80Max. 0.150Max. 2R3.00Min
,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, ,
3.20Min. 0.126Min.
20.00 0.787
3.30 0.130
2- o1.80 2- o0.071 2-R2.00 2-R0.079
,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,, (back) ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,
(Datum -A-)
144 2
2.00Min. 0.079Min.
Detail A
Detail B
(DATUM -A-) 0.60 0.05 0.024 0.002 2.5 0.098 R0.75 R0.030
0.25 Max. 0.010 Max.
0.80 0.031
4.00 0.10 0.157 0.004
2.55 Min. 0.100 Min.
4.00 0.10 0.157 0.004
3.70 0.146
2.10 0.083 23.20 0.913
4.60 0.181 32.80 1.291
1.50 0.10 0.059 0.004
4.00Min. 0.157Min.
1.00 0.10 0.039 0.004
25.40 1.000 6.00 0.236
33
HB56HW164DB Series, HB56HW165DB Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
34
HB56HW164DB Series, HB56HW165DB Series
Revision Record
Rev. Date 1.0 Dec. 27, 1996 Contents of Modification Initial issue Drawn by Approved by
35

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