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| HB56S1636 Series, HB56S1632 Series 16,777,216-word x 36-bit High Density Dynamic RAM Module 16,777,216-word x 32-bit High Density Dynamic RAM Module ADE-203-694A (Z) Rev. 1.0 May. 16, 1997 Description The HB56S1636 is a 16M x 36 dynamic RAM module, mounted 36 pieces of 16-Mbit DRAM (HM5116105) sealed in TCP package. The HB56S1632 is a 16M x 32 dynamic RAM module, mounted 32 pieces of 16-Mbit DRAM (HM5116105) sealed in TCP package. An outline of the HB56S1636, HB56S1632 is 72-pin single in-line package. Therefore, the HB56S1636, HB56S1632 make high density mounting possible without surface mount technology. The HB56S1636, HB56S1632 provide common data inputs and outputs. Decoupling capacitors are mounted on the module board. Features * 72-pin single in-line package Lead pitch: 1.27 mm * Single 5 V (5%) supply * High speed Access time: tRAC = 60 ns (max) * Low power dissipation Active mode: 15.12 W (max) (HB56S1636 Series) 13.44 W (max) (HB56S1632 Series) Standby mode (TTL): 378 mW (max) (HB56S1636 Series) (TTL): 336 mW (max) (HB56S1632 Series) (CMOS): 189 mW (max) (HB56S1636 Series) (CMOS): 168 mW (max) (HB56S1632 Series) * EDO page mode capability * 4,096 refresh cycles: 64 ms * 2 variations of refresh RAS-only refresh CAS-before-RAS refresh * TTL compatible HB56S1636 Series, HB56S1632 Series Ordering Information Type No. HB56S1636BSC-6 HB56S1632BSC-6 Access time 60 ns 60 ns Package 72-pin SIP socket type Contact pad Gold 2 HB56S1636 Series, HB56S1632 Series Pin Arrangement 1Pin 36Pin 37Pin 72Pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Notes: 1. 2. 3. 4. Pin name VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VCC NC A0 A1 A2 A3 A4 A5 A6 Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin name A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 A11 VCC A8 A9 NC RAS2 DQ26 (NC)* DQ8 (NC)* 1 3 Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Pin name DQ17 (NC)* DQ35 (NC)* VSS CAS0 CAS2 CAS3 CAS1 RAS0 NC NC WE NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 2 4 Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin name DQ12 DQ30 DQ13 DQ31 VCC DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC VSS DQ8: HB56S1636, NC: HB56S1632 DQ17: HB56S1636, NC: HB56S1632 DQ26: HB56S1636, NC: HB56S1632 DQ35: HB56S1636, NC: HB56S1632 3 HB56S1636 Series, HB56S1632 Series Pin Description Pin name A0 to A11 Function Address inputs Row address: Column address: Refresh address: DQ0 to DQ35 RAS0, RAS2 CAS0 to CAS3 WE VCC VSS PD1 to PD4 NC Data-in/Data-out Row address strobe Column address strobe Read/Write enable Power supply Ground Presence detect pin No connection A0 to A11 A0 to A11 A0 to A11 Presence Detect Pin Arrangement Pin No. 67 68 69 70 Pin name PD1 PD2 PD3 PD4 60 ns VSS VSS NC NC 4 HB56S1636 Series, HB56S1632 Series Block Diagram (HB56S1636) CAS0 RAS0 CAS2 RAS2 DQ0 RAS Din Dout RAS D0 CAS DQ18 RAS Din Dout RAS CAS D18 CAS D1 DQ19 Din Dout DQ1 Din Dout CAS D19 DQ7 RAS Din Dout RAS Din Dout D8 D7 CAS DQ25 Din Dout RAS CAS D25 DQ8 CAS DQ26 RAS Din Dout CAS D26 CAS1 RAS DQ9 Din Dout RAS Din Dout D9 CAS CAS3 RAS DQ27 Din Dout RAS Din Dout CAS D27 DQ10 CAS D10 DQ28 CAS D28 DQ16 RAS Din Dout RAS CAS D16 DQ34 RAS Din Dout RAS CAS D34 DQ17 Din Dout CAS D17 DQ35 Din Dout CAS D35 A0 to A11 WE VCC VSS 12 D0 to D35 D0 to D35 D0 to D35 C0 to C17 D0 to D35 * D0 to D35 : HM5116105 5 HB56S1636 Series, HB56S1632 Series Block Diagram (HB56S1632) CAS0 RAS0 CAS2 RAS2 DQ0 RAS Din Dout RAS D0 CAS DQ18 RAS Din Dout RAS CAS D16 CAS D1 DQ19 Din Dout DQ1 Din Dout CAS D17 DQ7 RAS Din Dout D7 CAS DQ25 Din Dout RAS CAS D23 CAS1 RAS DQ9 Din Dout RAS Din Dout D9 D8 CAS CAS3 RAS DQ27 Din Dout RAS Din Dout CAS D24 DQ10 CAS DQ28 CAS D25 DQ16 RAS Din Dout CAS D15 DQ34 RAS Din Dout CAS D31 A0 to A11 WE VCC VSS 12 D0 to D31 D0 to D31 D0 to D31 C0 to C15 D0 to D31 * D0 to D31 : HM5116105 6 HB56S1636 Series, HB56S1632 Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation (HB56S1636) Power dissipation (HB56S1632) Operating temperature Storage temperature Symbol VT VCC Iout Pt Pt Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 36 32 0 to +70 -55 to +125 Unit V V mA W W C C Recommended DC Operating Conditions (Ta = 0 to 70C) Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to VSS . VIH VIL Min 0 4.75 2.4 -1.0 Typ 0 5.0 -- -- Max 0 5.25 5.5 0.8 Unit V V V V 1 1 1 Note 7 HB56S1636 Series, HB56S1632 Series DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HB56S1636) 60 ns Parameter Operating current Standby current Symbol I CC1 I CC2 Min -- -- Max 2880 72 Unit mA mA Test conditions t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t HPC = min 0 V Vin 5.5 V 0 V Vout 5.5 V, Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 2 1 Notes 1, 2 -- 36 mA RAS-only refresh current Standby current CAS-before-RAS refresh current EDO page mode current Input leakage current Output leakage current Output high voltage Output low voltage I CC3 I CC5 I CC6 I CC7 I LI I LO VOH VOL -- -- -- -- -10 -10 2.4 0 2880 180 2880 3600 10 10 VCC 0.4 mA mA mA mA A A V V Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 8 HB56S1636 Series, HB56S1632 Series DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HB56S1632) 60 ns Parameter Operating current Standby current Symbol I CC1 I CC2 Min -- -- Max 2560 64 Unit mA mA Test conditions t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t HPC = min 0 V Vin 5.5 V 0 V Vout 5.5 V, Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 2 1 Notes 1, 2 -- 32 mA RAS-only refresh current Standby current CAS-before-RAS refresh current EDO page mode current Input leakage current Output leakage current Output high voltage Output low voltage I CC3 I CC5 I CC6 I CC7 I LI I LO VOH VOL -- -- -- -- -10 -10 2.4 0 2560 160 2560 3200 10 10 VCC 0.4 mA mA mA mA A A V V Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 9 HB56S1636 Series, HB56S1632 Series Capacitance (Ta = 25C, VCC = 5 V 5%) (HB56S1636) Parameter Input capacitance (Address) Input capacitance (WE) Input capacitance (RAS) Input capacitance (CAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI4 CI/O Typ -- -- -- -- -- Max 195 267 146 83 25 Unit pF pF pF pF pF Notes 1 1 1 1 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. Capacitance (Ta = 25C, VCC = 5 V 5%) (HB56S1632) Parameter Input capacitance (Address) Input capacitance (WE) Input capacitance (RAS) Input capacitance (CAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI4 CI/O Typ -- -- -- -- -- Max 175 239 132 76 25 Unit pF pF pF pF pF Notes 1 1 1 1 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 10 HB56S1636 Series, HB56S1632 Series AC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) *1, *2, *18 Test Conditions * * * * * Input rise and fall times: 2 ns Input level: 0 V, 3.0V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, and Refresh Cycles (Common parameters) 60 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time CAS delay time from Din Transition time (rise and fall) Refresh period (4,096 cycles) Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t DZC tT t REF Min 104 40 10 60 10 0 10 0 10 20 15 15 48 5 0 2 -- Max -- -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- 50 64 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 5 3 4 Notes 11 HB56S1636 Series, HB56S1632 Series Read Cycle 60 ns Parameter Access time from RAS Access time from CAS Access time from address Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output buffer turn-off time CAS to Din delay time Output data hold time from RAS Output buffer turn-off time to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time RAS to next CAS delay time Symbol t RAC t CAC t AA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OFF t CDD t OHR t OFR t WEZ t WED t RDD t RNCD Min -- -- -- 0 0 60 5 30 18 0 3 -- 15 3 -- -- 15 15 60 Max 60 15 30 -- -- -- -- -- -- -- -- 15 -- -- 15 15 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19 19 19 11, 19 10 10 Notes 6, 7 7, 8, 15 7, 9, 15 Write Cycle 60 ns Parameter Write command setup time Write command hold time Write command pulse width Data-in setup time Data-in hold time Symbol t WCS t WCH t WP t DS t DH Min 0 10 10 0 10 Max -- -- -- -- -- Unit ns ns ns ns ns 13 13 Notes 12 12 HB56S1636 Series, HB56S1632 Series Refresh Cycle 60 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol t CSR t CHR t WRP t WRH t RPC Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes EDO Page Mode Cycle 60 ns Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low Read command hold time from CAS precharge Symbol t HPC t RASP t CPA t CPRH t DOH t RCHC Min 25 -- -- 35 3 35 Max -- 100000 35 -- -- -- Unit ns ns ns ns ns ns 7, 15 Notes 16 14 7, 15 13 HB56S1636 Series, HB56S1632 Series Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD tRCD (max) + tAA (max) - tCAC (max), then access time is controlled exclusively by t CAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 6. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 8. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 9. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 10. Either t RCH or tRRH must be satisfied for a read cycles. 11. t OFF (max) defines the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 12. Early write cycle only (tWCS tWCS (min)). 13. These parameters are referred to CAS leading edge in early write cycles. 14. t RASP defines RAS pulse width in EDO page mode cycles. 15. Access time is determined by the longest among t AA , t CAC and t CPA. 16. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. 17. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC / VSS line noise, which causes to degrade V IH min./ V IL max level. 18. All the V CC and VSS pins shall be supplied with the same voltages. 19. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH, and between tOFR and t OFF. 20. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 14 HB56S1636 Series, HB56S1632 Series Timing Waveforms*20 Read Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t RAD t ASR t ASC t RAL t CAL t CAH t RAH Address Row Column t RRH t RCHR t RCS t RCH WE t WED t DZC t CDD t RDD Din High-Z t CAC t AA t RAC t CLZ t OFF t OH t OFR t OHR t WEZ Dout Dout 15 HB56S1636 Series, HB56S1632 Series Early Write Cycle t RC t RAS t RP RAS t CSH t RCD tT CAS t RSH t CAS t CRP t ASR t RAH t ASC t CAH Address Row Column t WP t WCS t WCH WE t DS t DH Din Din Dout High-Z* * t WCS t WCS (min) 16 HB56S1636 Series, HB56S1632 Series RAS-Only Refresh Cycle t RC t RAS RAS tT t CRP t RPC t CRP t RP CAS t ASR Address t OFR t OFF Dout Row t RAH High-Z 17 HB56S1636 Series, HB56S1632 Series CAS-Before-RAS Refresh Cycle t RC t RP RAS t RPC CAS t CSR tT t CHR t RPC t CRP t RAS t RP , t CP t WRP t WRH t CP WE Address t OFR t OFF Dout High-Z 18 HB56S1636 Series, HB56S1632 Series EDO Page Mode Read Cycle t RP t RASP tT CAS t RCS WE t RNCD RAS t HPC t HPC tCAS t RCHC t CPRH t CP t t CRP t CSH t CAS t RCHR t CP t HPC t CAS t CP RSH tCAS t RRH t RCH t RCH t RCS tASR Address tRAH tASC Row tCAH t ASC t CAH Column 2 t CAL t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED Column 1 t CAL tDZC t CAL tRDD tCDD Din High-Z " ! tCAC tAA tAA tCAC tWEZ tCPA tAA tCAC t AA t CAC tRAC tDOH tDOH tOFF tOH Dout tCPA tCPA tOFR tOHR Dout 1 Dout 2 Dout 3 Dout 4 19 HB56S1636 Series, HB56S1632 Series EDO Page Mode Early Write Cycle t RASP t RP RAS tT t CSH t RCD t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC tCAH t ASC t CAH Address Row Column 1 t WP t WCS t WCH Column 2 t WP t WCS t WCH Column N t WP t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din 1 Din 2 Din N Dout High-Z* * t WCS t WCS (min) 20 HB56S1636 Series, HB56S1632 Series Physical Outline Unit: mm inch Front side 107.95 4.25 101.19 3.98 2-O 3.175 0.125 R1.57 R0.062 6.35 0.25 2.03 0.08 6.35 0.25 9.14 max 0.36 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 72 A 1.27 typ. 0.05 44.45 1.75 R1.57 R0.062 6.35 0.25 44.45 1.75 ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,, 2.54 min. 0.10 10.16 0.40 25.40 1.00 1.27 typ 0.05 Back side 1 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Deteil A 2.54 min 0.10 1.04 0.03 0.041 0.0012 0.25 max 0.01 Note: Tolerance on all dimensions 0.13/0.005 unless otherwise specified. 3.175 min 0.125 5.72 min 0.225 72 21 HB56S1636 Series, HB56S1632 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 22 HB56S1636 Series, HB56S1632 Series Revision Record Rev. Date 0.0 1.0 Contents of Modification Drawn by T. Sugano Approved by K. Inoue Dec. 25, 1996 Initial issue May. 16, 1997 DC Characteristics ILI test conditions: 0 V Vin 7.0 V to 0 V Vin 5.5 V ILO test conditions: 0 V Vout 7.0 V to 0 V Vout 5.5 V V OH test conditions: -5 mA to -2 mA V OL test conditions: 4.2 mA to 2 mA AC Characteristics tRRH min: 0 ns to 5 ns Addition of tRNCD tRPC min: 0 ns to 5 ns Addition of notes12, 16, 17, 18 and 19 Timing Waveforms Deletion of Hidden refresh Addition of tRNCD for EDO Page Mode Read 23 |
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