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L5995
ACCURATE 4 BIT PROGRAMMABLE POWER SUPPLY CONTROLLER FOR MOBILE CPU
PROGRAMMABLE OUTPUT FROM 1.3V TO 2.0V WITH 0.05V BINARY STEPS OUTPUT VOLTAGE RANGE EXTENDIBLE FROM 2V TO 3.5V ULTRA HIGH EFFICIENCY SEPARATE 5V BIAS SUPPLY AVAILABLE FOR HIGH EFFICIENCY PERFORMANCE EXCELLENT OUTPUT ACCURACY 1% OVER LINE, LOAD AND TEMPERATURE VARIATIONS HIGH PRECISION INTERNAL REFERENCE DIGITALLY TRIMMED OPERATING SUPPLY VOLTAGE FROM 4.75V TO 25V VERY FAST LOAD TRANSIENT REMOTE SENSING INPUTS INTERNAL LINEAR REGULATOR 2.5V /150mA, 2% PRECISION POWER MANAGEMENT - PROGRAMMABLE POWER-UP TIME - POWER GOOD OUTPUT, SKIP MODE - OUTPUT OVERVOLTAGE PROTECTION - OUTPUT UNDERVOLTAGE LOCKOUT OPERATING FREQUENCY UP TO 1MHz MEETS INTEL MOBILE PENTIUM II
TQFP32 (7mm x 7mm)
Application ADVANCED MICROPROCESSOR SUPPLIES POWER SUPPLY FOR PENTIUM II INTEL MOBILE DESCRIPTION The L5995 is a power supply controller that offers a complete power management for notebook CPUs of the next generation especially for mobile Pentium II. A high precise 4 bit digital to analog converter (DAC) allows to adjust the output voltage from 1.3V to 2.0V with 0.05V binary steps. The reference can be programmed with an auxiliary bit between 2.1V and 3.5V with 0.1V steps. The high precision internal reference, digitally trimmed, assures the selected output voltage to
TYPICAL APPLICATION CIRCUIT
L5995
4.75V to 25V POWER SECTION PWM SECTIONS VO 1.3V to 2.0V CPU CORE
FREQ SETTING SYNC
DAC
D0 D1 D2 D3 POWER GOOD ENABLE
Pentium II Mobile
NOSKIP
POWER MANAGEMENT & SYSTEM SUPERVISOR 2.5V LIN. REG.
CPU CLK 2.5V
D97IN670B
3.3V
May 1999
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L5995
DESCRIPTION (Continued) within +/-1% over temperature and battery voltage variations. Thanks to the remote sensing inputs and to the window comparator system, embedded in the error summing structure, the device provides excellent load transient performance. The high peak current gate drive affords to have fast switching to the external power mos, performing an high efficiency. A complete power management include on board a programmable power-up sequencing, power good signal, skip mode operation and undervoltege detection. The L5995 assures a fast protection against load overvoltage and load overcurrent. Linear regulator on-board is available with an output voltage of 2.5V (+/-2%) and a current capability of 150mA, useful for CPU CLOCK BUS.
PWRGND RSTRAP HSTRAP NOSKIP 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 SNSGND VPROG VBG VFB COMP VIN2.5 VO2.5 VSS
PIN CONNECTION
POWERGOOD RGATE HGATE
32 31 30 29 28 27 26 25 ENABLE VIN REG5 V5SW CRST SSTART HRSNS LRSNS 1 2 3 4 5 6 7 8 VSS1 VID3 VID2 VID1 VID0 OVP OSC FREQ
HSRC
D97IN671C
BLOCK DIAGRAM
CSOFT VIN3.3V SSTART 6 WINDOW COMP SOFT START VID0 20 VID1 21 VID2 22 VID3 23 VIN2.5 13
VFB
9 SLOPE
+ + + ERROR SUMMING
PROGRAMMABLE BANDGAP & REFERENCE
14 2.5V LIN. REG. 15
VO2.5
VCPUCLK
LRSNS HRSNS COMP REG5 RSTRAP HSTRAP VIN Cboot HGATE HSRC
8 7 10
VBG
24
VSS1
29 28
VPROG
HRSNS OVER CURRENT COMPARATOR
LRSNS INTERNAL SUPPLY
11
VPROG
27 26
Hside
+ ZERO CROSSING COMPARATOR
3
REG5 C5
Rsense L C Load PWRGND SNSGND RGATE 30 31
CONTROL LOGIC Lside
+ PULSE SKIPPING COMPARATOR + -
LINEAR REGULATOR
4 2
V5SW VIN Vdc 5.5V to 25V
12 OSCILLATOR and SYNC 18 OSC 17 FREQ OVER/UNDER VOLTAGE COMPARATOR
VPROG POWER MANAGEMENT
32 1
PWGOOD
VSS
16
ENABLE 19 OVP
D97IN672B
25 NOSKIP
5 CRST Ccrst
5V
ABSOLUTE MAXIMUM RATINGS
Symbol VIN to PWRGND PWRGND to VSS VREFS to PWRGND HSTRAP, HGATE to PWRGND RSTRAP, RGATE to PWRGND EABLE, FREQ, OSC, COMP, VFB, HRSNS, LRSNS VID0-3, NOSKIP, VSS1 Tj Tstg Junction Temperature Range Storage Temperature Range Parameter Value -0.5 to 27 0.5 5 -0.5V to VIN+14V -0.5V to 14V 5 7 -40 to 150 -55 to 150 V V C C Unit V V V
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L5995
THERMAL DATA
Symbol RTh j-amb Parameter Thermal Resistance Junction to Ambient Value 60 Unit C/W
ELECTRICAL CHARACTERISTICS ( VIN = 12V; Ti = 25C, OSC = GND, unless otherwise specified) * = specifications referred to TJ from 0 to 70C.
Symbol VIN IOP ISB Parameter Input Supply Voltage Operating Quiescent Current Stand-By Current RGATE = HGATE = OPEN ENABLE = REG5 ENABLE = GND VIN = 12V VIN = 25V VIN = 6V to 25V ILOAD = 0 to 5mA, C REG5 = 4.7F CREG5 = 4.7F VIN = 5.5V VIN 6V V5SW = 4.5 to 5.5V VREG5 4.4V VIN 2.5 = 3.3V C VO 2.5 = 47F IO 2.5 = 10mA Test Conditions Min. Typ. Max. 25 650 800 Unit V A A A V DC CHARACTERISTICS
* * *
4.75
80 100 4.9 5.0
150 180 5.1
INTERNAL REGULATOR (VREG5) VREG5 Output Voltage
IREG5
Total Current Capability
25 60 4.3 25 4.5 4.7
mA mA V mA
Switch-Over Threshold Voltage Current Capability (internal switch on) 2.5V REFERENCE VOLTAGE VO 2.5 Regulated Voltage
* *
2.45
2.5
2.55
V
Regulation over Line and Load 6V < VIN < 25V VIN 2.5 = 3.3V IO 2.5 = 0-150mA IVO 2.5 MAX Current Limit VIN 2.5 = 3.3V PROGRAMMABLE REFERENCE VOLTAGE AND VBG VPROG VFB Accuracy Ouput Voltage Accuracy VID0, VID1, VID2, VID3, VSS1 see Table 1. Line and Load Regulation included, VID0, VID1, VID2, VID3, VSS1, see Table 1. C VBG = 220nF HIGH LEVEL LOW LEVEL C RST = 10nF 16 cycles C RST = 10nF 16 cycles
2.425
2.5
2.575
V
500
mA V V
* * *
-0.5% -1%
VPROG VPROG
+0.5% +1%
VBG Band Gap reference POWER MANAGEMENT Enable Voltage Disable Voltage Power Good Delay Shutdown Delay Time before Low side activation (Except Over-Voltage Fault) CRST Timing Rate Power Good Saturation Voltage NOSKIP Mode (Active high)
1.240 2.4
1.246
1.252
V V
0.8 120 120 160 160 200 200
V ms ms
16 Isink = 400A High Level Low Level 0.4 0.8 2.4
ms/nF V V V
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L5995
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Output UVLO Threshold Output UVLO Lockout Time PROTECTION FUNCTIONS V8-V7 Over-Current Threshold Voltage Pulse Skipping Mode Threshold Voltage Zero Crossing Threshold Under-Voltage Threshold Over-Voltage Threshold Over-Voltage Propagation Time Under-Voltage Propagation Time SOFT START Soft start source current Soft start clamp voltage OSCILLATOR AND SYNC fosc f
SINK MIN
Test Conditions OVP = GND Depending on CSS value VSSTART = 3.1V NOSKIP = HIGH
Min. 60
Typ. 70 775
Max. 80
Unit % ms/F
*
31 3 -2 Vprog -13%
35 6
39 10 +2
mV mV mV V V s s
Vprog -10% Vprog +10%
Vprog -7% Vprog +13% 1.5 1.5
OVP = GND
Vprog +7%
3.2
4 3.1
4.8
A V
Fixed frequency Minimum Synchronizzable external frequency Sync pulse width Sync pulse amplitude
OSC =0V; FREQ = REG5 OSC = REG5 FREQ = REG5 FREQ = REG5 OSC = EXTERNAL SIGNAL Rising edge mode
* *
225 180
250 200
275 220 120
KHz KHz KHz ns
200
Operating switching frequency Rext connected between FREQ and GND, Osc connect to REG5 or GND Rext = 680k Rext = 40k HIGH AND LOW SIDE GATE DRIVERS IOH5 R H5 IOH12 R H12 IOL5 RL5 IOL12 R L12 TCC Output high source peak current Output high sink impedance Output high source peak current Output high sink impedance Output low peak current Output low impedance Output low peak current Output low Impedance Dead Time HSTRAP = RSTRAP = REG5 Itest = 100mA, HSTRAP = RSTRAP = REG5 HSTRAP = RSTRAP = 12V Itest = 100mA, HSTRAP - RSTRAP = 12V HSTRAP = RSTRAP = 5V Itest = 100mA, HSTRAP = RSTRAP = 5V HSTRAP = RSTRAP = 12V Itest = 100mA, HSTRAP = RSTRAP = 12V GATE low to high
fosc
*
3
5.5
V
100 1 550 3.5 2 2 500 3 2 2 60
kHz MHz mA A mA A ns
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FUNCTIONAL PIN DESCRIPTION ENABLE(pin1): Enable input. A high level (>2.4V) enables the device, a low level (<0.8V) shuts it down. As ENABLE drops below 0.8V, the drivers are turned off and all internal functions are disabled except REG5. In this condition the stand by current is less than 80A at VIN = 12V. VIN(pin2): Device supply voltage. Input voltage range at this pin is 4.75V to 25V and the operating current requirement at 12V is 650A. REG5(pin3): 5V Regulator supply. Used also to supply the bootstrap capacitor. A minimum 2.2F ceramic capacitor connected to PWRGND is required. V5SW(pin4): 5V supply line. Connecting to 5V bus(4.75V to 5.5V) the device is no longer powered by VIN but by this pin and the internal linear regulator is disconnected increasing the efficiency. CRST(pin5): Control start up. An external capacitor connected to this pin defines the delay between the output voltage Vo has reached 90% of VPROG and POWERGOOD leading edge signal will start to go high. This delay could be calculated using the follows formula: Tst(ms)=16*C(F). SSTART(pin6): Soft Start. The soft-start time is programmed by an external capacitor connected between this pin and SGND. The internal current generator forces 4A through the capacitor implementing the soft start function. HRSNS(pin7): Error summing current sense non inverting input. LRSNS(pin8): Error summing current sense inverting input. VFB(pin9): Regulator voltage feedback input. Connect close to the CPU input supply pin realise an accurate voltage regulation. VFB internally is connected to the window comparator that is used to increase the performance during the load transient. COMP(pin10): Regulator stability compensation pin. The compensation is realised internally and normally it is not necessary to connect any external components to this pin .
VPROG(pin11): Reference voltage test pin. This pin provides the DAC output and should be decoupled to ground using a 0.22F ceramic capacitor. No load has to be connected. SNSGND(pin12): Remote ground sense. This pin is internally connected to the low power circuitry and for a precise output voltage regulation can be connected to the output capacitor negative terminal. VIN2.5(pin13): 2.5V linear supply voltage. Is available on-chip a linear regulator useful for the 2.5V bus. A max input voltage of 3.3V is recommended at Iomax (150mA). VO2.5(pin14): 2.5V linear regulator output. The linear regulator is realised with an internal NPN transistor with +/-2% output accuracy. A minimum of 47F capacitor connected versus PWRGND is required. VBG(pin15): Band-gap reference voltage. A min 220nF ceramic capacitor is required to assure the band gap stability and noise immunity. VSS(pin16): Signal ground. This pin could be connected to the PWRGND pin. FREQ(pin17): Connecting an external resistor versus ground is possible to select the switching frequency between 100kHz and 1MHz. Using an Rext=680k the fsw is 100kHz, using an Rext = 40k the fsw is 1MHz. In this condition is recommended to connect the OSC pin to REG5 or to VSS. OSC(pin18): Connecting to REG5 is able to set the switching frequency at 250kHz, connecting to VSS is able to set the switching frequency at 300kHz. An external pulsed signal, with an amplitude higher than 2.4V, could synchronise the device. In all these conditions pin FREQ has to be connected to REG5. OVP(pin19): Over voltage protection pin. If connected ti GND the device works in normal operation activating OVP and UVLO output controls. If connected to REG5 the OVP and UVLO controls are disabled. If OVP = GND and ENABLE = GND or the NO-CPU condition is set the high side is maintained off and the low side is on. If OVP = REG5 and ENABLE = GND or the NO-CPU condition is set the high side and the low side are maintained off.
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L5995
VID0-3(pin20-23): Voltage Identification code input. These open collector compatible inputs are used to program the output voltage as specified in Table 1. Every pin has an internal pull up. If all four pins are high or floating, the output voltage and the 2.5V regulator are suspended and the POWERGOOD is low. VSS1(pin24): SeeTable 1. NOSKIP(pin25): Pulse skipping mode control. A high level (>2.4V) disables pulse skipping in low load condition, a low level (>0.8V) enables it. HSRC(pin26): High side N-Channel switch source connection. This pin provides the return path for the high side driver. HGATE(pin27): Gate driver output, high side NChannel switch. The driver internal impedance is about 4 at VIN=12V. HSTRAP(pin28):Bootstrap capacitor pin. This pin provide to supply the high side driver sinking the RGATE(pin30): Gate driver output, low side NChannel switch. The driver internal impedance is about 3 at VIN=12V. PWRGND(pin31): Power ground. This pin has to be connected closely to the low side mosfet source in order to reduce the noise injected into the IC. POWER GOOD(pin32): Open drain power good output. This pin is pulled low if the output voltage is not within 10% and the 2.5V output is lower than 2.175V (-13%). The pin is pulled low also if REG5, VPROG and VBG have not reached the expected values. This test could be useful in an assembling fault condition current by the bootstrap capacitor. RSTRAP(pin29): Synchronous rectifier gate driver supply voltage. This pin could be connected to REG5 to reduce the switching losses due to the external mosfets gate capacitance. This is useful to maintain an high efficiency at light load.
Table 1. Output voltage.
OUTPUT VOLTAGE (VFB) VID3 (PIN 23) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 (PIN 22) 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 (PIN 21) 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 (PIN 20) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VSS1 = GND NO CPU 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 VSS1 = REG5 NO CPU 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
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L5995
Figure 1. Application Circuit
Vin 5.5V to 25V
REG5 SSTART VBG 6 3 2
VIN 29
RSTRAP HSTRAP HGATE
28 27
15
NOSKIP VSS OSC FREQ CRST VPROG
25 16 18 17 5 11 26
HSRC
Vo 1.3V to 2.0V
L5995
30
RGATE
31
PWRGND
Pentium II Mobile
24 5V BUS Vin2 3.3V V5SW
7 8
HRSNS LRSNS SNSGND VFB Vo2.5 Vo2 2.5V/150mA PWRGOOD 4 BIT
4
12 9
13 19 20/23 1
14 32
OVP
ENABLE VID0-VID3
D98IN858B
Figure 2. Application Circuit (Supply by 5V bus)
5V BUS
V5SW SSTART VBG 6 4 3
REG5 2
VIN 29
RSTRAP HSTRAP HGATE
28 27
15
NOSKIP VSS OSC FREQ CRST VPROG
25 16 18 17 5 11 26
HSRC
Vo 1.3V to 2.0V
L5995
30
RGATE
31
PWRGND
Pentium II Mobile
24 OVP
7 8
HRSNS LRSNS SNSGND VFB Vo2.5 Vo2 2.5V/150mA PWRGOOD ENABLE VID0-VID3 4 BIT
19
12 9
13 Vin2 3.3V 20/23 1
14 32
D98IN865B
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L5995
Figure 3. Start up, enable and disable signals.
VIN 5.5V
REG5
EN
VPROG
Vo2.5V
Vo
SOFT START
Drivers OFF
Driver LOW ON
CRST
16 cycles 16 cycles
Powergood
D98IN859A
Figure 4. Overcurrent and overvoltage protection.
Vo
Driver Low Latched ON
Io
Powergood
CRST
16 cycles
VPROG
Vo2.5V
D98IN860A
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L5995
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09
mm TYP. MAX. 1.60 0.15 1.40 0.37 1.45 0.45 0.20 9.00 7.00 5.60 0.80 9.00 7.00 5.60 0.60 1.00 0(min.), 7(max.) 0.75 0.018 0.002 0.053 0.012 0.004 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.015 0.057 0.018 0.008 0.354 0.276 0.220 0.031 0.354 0.276 0.220 0.024 0.039 0.030
OUTLINE AND MECHANICAL DATA
TQFP32
D D1 D3
24 25 17 16
0.10 mm .004 Seating Plane
A A2 A1
E3
E1
B
32 1 8
9
E
B
e
L1 L
C
K
TQFP32
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L5995
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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