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6812 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
PRELIMINARY INFORMATION
(subject to change without notice) August 28, 1998 A6812xA
LOAD SUPPLY SERIAL DATA OUT OUT 20 OUT 19 OUT 18 OUT 17 OUT 16 OUT 15 OUT 14 OUT 13 OUT 12 OUT 11 BLANKING GROUND 1 2 3 4 5 6 REGISTER REGISTER LATCHES LATCHES 7 8 9 10 11 12 13 14 BLNK ST CLK VBB VDD 28 27 26 25 24 23 22 21 20 19 18 17 16 28 27 15 LOGIC SUPPLY SERIAL DATA IN OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT 10 STROBE CLOCK
6812
DABiC-IV, 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
The A6812- devices combine a 20-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuumfluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6812- features an increased data input rate (compared with the older UCN/UCQ5812-F) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, typical serial-data input rates are up to 33 MHz. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as the A6809- and A6810- (10 bits), A6811- (12 bits), and A6818- (32 bits). The A6812- output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA. Three temperature ranges are available for optimum performance in commercial (suffix S-), industrial (suffix E-), or automotive (suffix K-) applications. Package styles are provided for through-hole DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logic-power dissipation, and low output-saturation voltages allow these drivers to source 25 mA from all outputs continuously to more than +43C (suffix -LW), +61C (suffix -EP), or +77C (suffix -A).
Data Sheet 26182.126
Dwg. PP-029-7
ABSOLUTE MAXIMUM RATINGS
at TA = 25C
Logic Supply Voltage, VDD ................... 7.0 V Driver Supply Voltage, V BB ................... 60 V Continuous Output Current Range, IOUT ......................... -40 mA to +15 mA Input Voltage Range, VIN ....................... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD ........................................ See Graph Operating Temperature Range, TA (Suffix `E-') .................. -40C to +85C (Suffix `K-') ................ -40C to +125C (Suffix `S-') .................. -20C to +85C Storage Temperature Range, TS ............................... -55C to +125C
Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges.
FEATURES
s Controlled Output Slew Rate s Low Output-Saturation Voltages s High-Speed Data Storage s Low-Power CMOS Logic s 60 V Minimum and Latches Output Breakdown s Improved Replacements s High Data Input Rate for TL5812-, UCN5812-, s PNP Active Pull-Downs and UCQ5812- Complete part number includes a suffix to identify operating temperature range (E-, K-, or S-) and package type (-A, -EP, or -LW). Always order by complete part number, e.g., A6812SLW .
6812 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
A6812xEP
SERIAL DATA OUT LOGIC SUPPLY LOAD SUPPLY SERIAL DATA IN OUT20 OUT19 OUT 1
LOAD SUPPLY SERIAL DATA OUT OUT 20 1 2 3 4 5 6
REGISTER REGISTER LATCHES LATCHES
A6812xLW
VBB VDD 28 27 26 25 24 23 22 21 20 19 18 17 BLNK ST CLK 16 28 27 15 LOGIC SUPPLY SERIAL DATA IN OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT 10 STROBE CLOCK
V DD 28
VBB
27
26
4
3
2
1
OUT18
5 6
25 24
OUT 2
OUT 19 OUT 18 OUT 17 OUT 16 OUT 15 OUT 14
REGISTER
REGISTER
LATCHES
LATCHES
7 8 9 10 OUT12 11
23 22 21 20 19 OUT 8
7 8 9 10 11 12 13 14
OUT 13 OUT 12
CLK 12 14
ST 17
13
15
16
18
OUT11
GROUND
BLANKING
STROBE
CLOCK
OUT 10
OUT9
OUT 11 BLANKING
Dwg. PP-059-1
GROUND
TYPICAL INPUT CIRCUIT
Dwg. PP-029-8
VDD
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
SU FF IX
IN
2.0
'E P' ,R
1.5
SU FF IX
IX FF SU ', R 'A
A J
J
=
55 C /W
A
= /W C 45
Dwg. EP-010-5
'LW ', R
J
A
TYPICAL OUTPUT DRIVER
V BB
1.0
=
66 C /W
0.5
OUTN
0 25 50 75 100 125 AMBIENT TEMPERATURE IN C 150
Dwg. EP-021-19
Dwg. GP-024-2
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 1998, Allegro MicroSystems, Inc.
6812 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
FUNCTIONAL BLOCK DIAGRAM
CLOCK SERIAL DATA IN STROBE V DD LOGIC SUPPLY SERIAL DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
BLANKING MOS BIPOLAR LOAD SUPPLY
VBB
GROUND
OUT 1 OUT 2 OUT 3
OUT N
Dwg. FP-013-1
TRUTH TABLE
Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L R1 R2 ... R1 R2 ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X Serial Data Strobe Output Input RN-1 RN-1 RN X PN L H R1 R2 R3 ... P1 P2 P3 ... X
L = Low Logic Level H = High Logic Level X = Irrelevant
Latch Contents I1 I2 I3 ... IN-1 IN Blanklng
Output Contents I1 I2 I3 ... IN-1 I N
R1 R2 R3 ... X X X ...
RN-1 RN PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L
P1 P2 P3 ...
PN-1 PN
X
X
...
P = Present State
R = Previous State
6812 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25C (A6812S-) or over operating temperature range (A6812E- and A6812K-), VBB = 60 V unless otherwise noted.
Limits @ VDD = 3.3 V Characteristic Output Leakage Current Output Voltage Symbol I CEX VOUT(1) VOUT(0) Output Pull-Down Current Input Voltage IOUT(0) VIN(1) VIN(0) Input Current IIN(1) IIN(0) Input Clamp Voltage Serial Data Output Voltage VIK VOUT(1) VOUT(0) Maximum Clock Frequency Logic Supply Current fc IDD(1) IDD(0) Load Supply Current IBB(1) IBB(0) Blanking-to-Output Delay tdis(BQ) t en(BQ) Strobe-to-Output Delay tp(STH-QL) tp(STH-QH) Output Fall Time Output Rise Time Output Slew Rate tf tr dV/dt All Outputs High All Outputs Low All Outputs High, No Load All Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% RL = 2.3 k, C L 30 pF RL = 2.3 k, C L 30 pF RL = 2.3 k, C L 30 pF RL = 2.3 k, C L 30 pF RL = 2.3 k, C L 30 pF IOUT = 200 A VIN = VDD VIN = 0 V IIN = -200 A IOUT = -200 A IOUT = 200 A Test Conditions VOUT = 0 V IOUT = -25 mA IOUT = 1 mA VOUT = 5 V to VBB Mln. -- 57.5 -- 2.5 2.2 -- -- -- -- 2.8 -- 10 -- -- -- -- -- -- -- -- 2.4 2.4 4.0 -- Typ. <-0.1 58.3 1.0 5.0 -- -- <0.01 <-0.01 -0.8 3.05 0.15 33 0.25 0.25 3.0 0.2 0.7 1.8 0.7 1.8 -- -- -- 50 Max. -15 -- 1.5 -- -- 1.1 1.0 -1.0 -1.5 -- 0.3 -- 0.75 0.75 6.0 20 2.0 3.0 2.0 3.0 12 12 20 -- Limits @ VDD = 5 V Min. -- 57.5 -- 2.5 3.3 -- -- -- -- 4.5 -- 10 -- -- -- -- -- -- -- -- 2.4 2.4 4.0 -- Typ. <-0.1 58.3 1.0 5.0 -- -- <0.01 Max. -15 -- 1.5 -- -- 1.7 1.0 Units A V V mA V V A A V V V MHz mA mA mA A s s s s s s V/s ns
<-0.01 -1.0 -0.8 4.75 0.15 33 0.3 0.3 3.0 0.2 0.7 1.8 0.7 1.8 -- -- -- 50 -1.5 -- 0.3 -- 1.0 1.0 6.0 20 2.0 3.0 2.0 3.0 12 12 20 --
Clock-to-Serial Data Out Delay tp(CH-SQX)
Negative current is defined as coming out of (sourcing) the specified device terminal. Typical data is is for design information only and is at TA = +25C.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6812 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are V DD and Ground)
C CLOCK A SERIAL DATA IN DATA
50%
B
50%
t p(CH-SQX) SERIAL DATA OUT D STROBE
50% 50%
DATA E
BLANKING
LOW = ALL OUTPUTS ENABLED t p(STH-QH) t p(STH-QL)
90%
OUT N
DATA
10%
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED) BLANKING
50%
t dis(BQ) t en(BQ) OUT N tr
90% 10%
tf
DATA
A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) ......................................... 25 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) ............................................... 25 ns C. Clock Pulse Width, tw(CH) ............................................... 50 ns D. Time Between Clock Activation and Strobe, t su(C) ....... 100 ns E. Strobe Pulse Width, tw(STH) ............................................. 50 ns NOTE - Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable.
Dwg. WP-030
Information present at any register is transferred to the respective latch when the STROBE is high (serial-toparallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches.
Serial Data present at the input is transferred to the shift register on the logic "0" to logic "1" transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
6812 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
A6812EA, A6812KA, & A6812SA
Dimensions in Inches (controlling dimensions)
28 15 0.015 0.008
0.700
MAX
0.580 0.485
0.600
BSC
1
2 0.070 0.030
3
4 1.565 1.380
14 0.100
BSC
0.005
MIN
0.250
MAX
0.015
MIN
0.200 0.115 0.022 0.014
Dwg. MA-003-28 in
Dimensions in Millimeters (for reference only)
28 15 0.381 0.204
17.78
MAX
14.73 12.32
15.24
BSC
1
2 1.77 0.77
3
4 39.7 35.1
2.54
BSC
14
0.13
MIN
6.35
MAX
0.39
MIN
5.08 2.93 0.558 0.356
Dwg. MA-003-28 mm
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6812 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
A6812EEP, A6812KEP, & A6812SEP
Dimensions in Inches (controlling dimensions)
18 12
0.013 0.021 0.219 0.191
19
11
0.050
BSC
0.026 0.032 0.456 0.450 0.495 0.485
INDEX AREA
0.219 0.191
25
5
26 0.020
MIN
28
1
4
0.165 0.180
0.456 0.450 0.495 0.485
Dwg. MA-005-28A in
Dimensions in Millimeters (for reference only))
18 12
0.331 0.533 5.56 4.85
19
11
1.27
BSC
0.812 0.661 11.58 11.43 12.57 12.32
INDEX AREA
5.56 4.85
25
5
26 0.51
MIN
28
1
4
4.57 4.20
11.582 11.430 12.57 12.32
Dwg. MA-005-28A mm
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative.
6812 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER
A6812ELW, A6812KLW, & A6812SLW
Dimensions in Inches (for reference only)
28 15 0.0125 0.0091
0.2992 0.2914
0.491 0.394 0.050 0.016
0.020 0.013
1
2
3 0.7125 0.6969
0.050 BSC
0 TO 8
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-28 in
Dimensions in Millimeters (controlling dimensions)
28 15 0.32 0.23
7.60 7.40
10.65 10.00 1.27 0.40
0.51 0.33
1
2
3 18.10 17.70
1.27 BSC
0 TO 8
2.65 2.35 0.010 MIN.
Dwg. MA-008-28 mm
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

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