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Si9990ACS
Vishay Siliconix
Si9990A
5-V VCM Driver/Spindle Motor Driver For 1.8- and 2.5-Hard Disk Drives
FEATURES
* On-Board Half-Bridge Drivers - Spindle = 2.3 Total at 1 A - VCM = 3.3 Total at 0.3 A * Spindle Driver Features: - Back EMF Commutation - Linear Current Control - Internal Current Sense Resistor - Start-Up Current Limit (10% Accurate)
BENEFITS
* Single 5-V Supply * Rail-to-Rail Output Voltage Swing * VCM Driver Features: - Class AB Linear Operation - Externally Programmable Gain and Bandwidth - Programmable Retract Current and Fixed Voltage Clamp
APPLICATIONS
* * * * * * Over-Temperature Protection System Voltage Monitor Undervoltage Head Retract Sleep Mode and Idle Mode Reference Generator Two Uncommitted Amplifiers
DESCRIPTION
The Si9990ACS has a 3-phase brushless dc (spindle) motor driver and a linear transconductance amplifier suitable for driving a voice coil motor (head actuator). and a 300-mA power amplifier featuring four MOSFETs in an H-bridge configuration. The output crossover protection ensures no cross-conducting current and Class AB operation during linear tracking. Externally programmable gain switching at the input summing junction increases the resolution and dynamic range for a given DAC. The head retract circuitry can be activated by either an undervoltage condition or an external command. An external resistor is required to set the VCM current during retract. The retract voltage clamp is set at 0.44 V. A reference generator and two uncommitted amplifiers are also provided for analog interface. In sleep mode, internal logic initiates a head retract operation followed by spindle brake and shutdown of all analog circuitry except the supply monitor. The standby power dissipation is less than 6 mW. The VCM may also be disabled without disabling spindle operation (idle mode). All controls from the microprocessor are communicated via the serial interface. Additional housekeeping functions of the driver include thermal shutdown and undervoltage lockout. The Si9990ACS is manufactured using a self-isolated BiC/ DMOS process and is available in a 64-pin SQFP package for operation over the commercial (0 to 70C) temperature range.
Spindle Motor Driver The spindle driver features three 1-A, 2.3- (total) all n-channel MOSFET half-bridge output stages. The spindle driver uses internal back EMF sensing circuitry that eliminates the need for hall sensors. An internal charge pump allows rail-to-rail output voltage swing with a nominal 5-V supply. A unique output structure eliminates the need for an external Schottky diode to isolate the system 5-V supply if it fails during operation. This makes the output half-bridge drive capability equivalent to drivers with 1-A, 1.9- specifications in series with the required Schottky diode.
VCM Driver The VCM driver provides all necessary functions including a motor current sense amplifier, a loop compensation amplifier
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FUNCTIONAL BLOCK DIAGRAM
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ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to Common Pin VDD Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to 7 V Pin (Output A, B and C) . . . . . . . . . . . . . . . . -0.3 V to VCLAMP + 0.3 V Pin (Output + and -) . . . . . . . . . . . . . . . . . . . . . . -0.3 to VMOT + 0.3 V Pin (CHS, CP1H, CP2H) . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to 16 V Maximum Output Currenta Output A, B and C (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output A, B, and C (Continuous) . . . . . . . . . . . . . . . . . . . . . . Output + and - (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output + and - (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 A 0.4 A 0.5 A 0.3 A VMOT to VCLAMP Diode (Peak) . . . . . . . . . . . . . . . . . . . . . . . 100 mA VMOT to VCLAMP Diode (Continuous) . . . . . . . . . . . . . . . . . . . 50 mA VMOT to CHS Diode (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA VMOT to CHS Diode (Continuous) . . . . . . . . . . . . . . . . . . . . . 25 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipationc -- 64-Pin SQFP . . . . . . . . . . . . . . . . . . . . . 2.0 W Thermal Impedance (JA)c -- 64-Pin SQFP . . . . . . . . . . . . 62.5C/W Notes a. Output current rating is dependent on the system duty cycle, startup timing and heat dissipation capability. b. Diode currents depend on power supply start-up transient and bypass capacitor values. c. Device mounted with all leads soldered or welded to PC board.
Pin (All Others) . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to VDD + 0.3 V Maximum Clamp Currentb Output A, B and C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 A Output + and -. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 A (Pulsed 10 ms at 10% duty cycle) All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
SPECIFICATIONS
Test Conditions Unless Specified Parameters Supply
Static, No Load, Sleep Mode Supply Current IDD + IMOT VDD, VMOT Static, No Load, Normal Operation Static, No Load, Idle Mode VDD, VMOT Operating Range 4.5 0.9 20 14 5 1.2 41 19 5.5 V mA
Limits
Symbol
VADIN = VDD = VMOT = 5 V 10% RS(VCM) = 1.67 RSPIN = 17 k, TA = 0 to 70C
Min
Typ
Max
Unit
Control Logic
Low Input Voltage (G/S, DATA, CLK, CS, PU, PD) High Input Voltage Low Input Current High Input Current Mode Pin Pull Down Current Low Output Voltage (FCOM, FAULT, POUT) High Output Voltage POUT Off-State Leakage Current EMF Comparator Offset Maximum EMF Comparator Input Common Mode Voltage CST Current CD Current (CD1 or CD2) ICD (Discharging)/ICD (Charging) CWD Current ICWD VTL VTH ICST ICST1 or ICST2 Charging or Discharging Charging Discharging CD1 or CD2 Charging Discharging VOS VIL VIH IIL IIH IPD VOL VOH VIN = 0 V VIH = 5 V VIN = 5 V IOUT = 500 A IOUT = -500 A VOUT = 2.5 V 4 -1 20 40 4.3 5 10 -20 2.0 5 -25 0.5 2.50 A A 1 70 -0.3 3.5 -1 1 100 0.5 V A mV V A 1.5 5.3 V
CWD Threshold Voltage
V
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SPECIFICATIONS
Test Conditions Unless Specified Parameters Symbol
VADIN = VDD = VMOT = 5 V 10% RS(VCM) = 1.67 RSPIN = 17 k, TA = 0 to 70C
Limits
Min
Typ
Max
Unit
Spindle Transconductance Amplifier (A1)
Voltage Gain Gain-Bandwidth Slew Rate Output Voltage Swing Input Bias Current Offset Voltage Power Supply AV Fo SR VOUT Ib VOS PSRR f = 10 kHz RLOAD = 4 to VMOT RLOAD = 4 to VMOT, CLOAD = 100 pF Measured at OA1 with respect to GND 2.70 50 RLOAD = 50 k to VR Bits D2 D3 = 00 to 11 RLOAD = 50 k to VR (See Note a) Measured at 1.2 to 2.9 V RLOAD = 50 k, CLOAD = 100 pF to VR 0.5 0.8 3.1 50 10 60 1 dB MHz V/s V nA mV dB
Spindle Transconductance Amplifier (A6 and A7)
Transconductance Output Current Limit Accuracy -3 dB Bandwidth Slew Rate Output Current Cutoff Voltage Fo SR Gms 0.4 -20 70 1 2.85 3.0 0.5 0.6 20 A/V % kHz V/s V
Spindle Half-Bridge
IOUT = 1 A On-Resistance (Sink or Source) rDS(on) IOUT = 1 A including 0.23 RS (Sink + Source), IOUT = 1 A Output Leakage Current Clamp Diode IDS(off) Vf(on) VOUT = VMOT VOUT = 0 V IOUT = 1 A -100 -1.5 0.6 0.7 2.3 100 A V
VCM Transconductance Amplifier (A3, A4, A5, A9, A10 and DMOS FETs)
Transconductance Output Offset Current, High Gain Output Offset Current, Low Gain Output Compliance Clamp Diode Voltage Feedback Resistance A4, A5 3 dB Bandwidth PSRR Output Swing A3, A5 A4 A9 , A10 @ 10 kHz RLOAD = 50 k to VR 0.2 1.2 GMVH GMVL I OS, HG IOS, LG VOH VOL VCL RF Gain Select = High, IOUT = 300 mA Gain Select = Low, IOUT = 75 mA Gain Select = High IOS (G/Sel = High)-IOS (G/Sel = Low) IOH = 0.3 A, VMOT = 4.5 V, Output IOL = 0.3 A, VMOT = 4.5 V, Output IF = 0.3 A From ISENSE(OUT) to IA4 10 1 0.4 50 VDD -0.2 VDD -1.2 MHz dB V 142 35.6 -5 -5 3.9 150 37.5 0 0 4.2 0.2 0.4 1.5 k V 158 39.4 +5 +5 mA/V
mA
Reference Generator (A8)
Input Resistance Output Voltage VR Measured at VADIN Pin IOUT = 2 mA 2.37 72 2.5 2.63 k V
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SPECIFICATIONS
Test Conditions Unless Specified Parameters Power Supply Monitor
VDD Undervoltage Threshold Hysteresis 3.7 3.9 70 4.1 V mV
Limits
Symbol
VADIN = VDD = VMOT = 5 V 10% RS(VCM) = 1.67 RSPIN = 17 k, TA = 0 to 70C
Min
Typ
Max
Unit
Overtemperature Protection
Trip Point Hystersis 165 20
V RET I RET = -------------- , I OUT = - ( 200 x I RET ) R RET
C
Head Retract Function (Undervoltage Or Sleep Mode; CDLY tied to VCLAMP)
IRET Bias Voltage Retract Output Current Limit Retract Output Voltage Limit Emergency Retract Supply Current Retract Supply Voltage Range CHS Leakage VRET IOUT+ VOUTICLAMP VCLAMP ICHS VDD = 0 V, VCLAMP = 3 V, VCHS = 10 V 0.25 14 0.31 20 0.44 2 1.41 5 26 0.5 4 5.5 2 V mA V mA V A
RRET = 2.5 k, VOUT+ = 0.2 V IOUT- = -20 mA VCLAMP = 3 V, RRET = 2.5 k VDD = 0 V, Static, No Load
dc to dc Converter (Charge Pump)
Output Voltage CHS ICHS = -5 mA, VDD = VMOT = 4.5 V 11 V V
Flyback Clamp
Flyback Clamp Switch Resistance Clamp Zener Voltage VZ Normal Mode, ICLAMP = 0.1 A ICLAMP = 0.1 A 4 9.1
Uncommitted Amplifier (A2 )
Input Offset Voltage Input Bias Current Unity Gain Bandwidth Slew Rate Power Supply Rejection Ratio Open Loop Voltage Gain Output Voltage Swing SR PSRR AVOL VO @ 10 kHz RLOAD = 50 k to VR, Measured at VR 1.8 V RLOAD = 50 k to VR 0.2 VOS IB RLOAD = 50 k, CLOAD = 100 pF to VR 1 50 60 VDD 0.2 dB 1 -15 0 +15 50 mV nA MHz V/s
V
Timing
Chip Select to Clock Setup Time Data Setup Time Data Hold Time Head Retract Time-Out (Brake Delay) Notes a. 50-k load is in addition to the RSPIN load. tCS tDS tDH tDLY tDLY = 514 k x CDLY, CDLY = 0.18 F, VDD = 0 V, VCLAMP = 1.41 to 5.5 V See Timing Diagram, Figure 1. 160 160 160 55 100 240 ms ns
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DETAILED DESCRIPTION
Serial Port A 6-bit word at the serial port DATA pin is used to program basic operating conditions. The function of each bit is shown in Tables 1 and 2. To write data to the serial port, CS is pulled low during CLOCK low. This holds the existing word while new data is written into the shift registers on a positive CLOCK edge. The new data becomes valid on the rising edge of CS. When CS is high, CLOCK is disabled and data cannot be shifted. D0 is the last bit written to the serial port. It enters sleep mode (D0 = 0) upon power up. When D0 is written "0", a head retract is automatically initiated and tDLY applies following the next CS rising edge. The Mode pin is used for production testing only. It should be tied low during normal operation.
TABLE 1. Serial Port Definitions Function Bit
D0 D1 D2 D3 D4 D5
Name
Sleep Mode/System Enable Spindle Brake Spindle Current Limit Spindle Current Limit Idle Mode/VCM Enable Spindle Step Mode
0
Sleep Mode: VCM retracted, spindle and VCM brake applied after period tDLY Normal Operation
1
Normal Operation Spindle Disabled and Brake Applied, VCM Enabled See Table 2. See Table 2.
Idle: VCM Disabled and Brake Applied, Spindle Running Normal Operation
Normal Operation Test Pin Becomes Single Step Commutation Clock
TABLE 2. Spindle Current Limit D2
0 0 1 1
D3
0 1 0 1
Current Limit
1.85 V e Gms 1.45 V e Gms 1.05 V e Gms 0.65 V e Gms
Current Limit (RSPIN = 17 k)
925 mA 725 mA 525 mA 325 mA
Current Limit (RSPIN = 15.7 k)
1A 780 mA 570 mA 350 mA
Gms = Transconductance (Refer to VCM Design Equations)
FIGURE 1. Write Cycle Timing Diagram
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Motor Shutdown Sequence The Si9990ACS executes a motor shutdown sequence whenever VDD drops below 3.9 V (emergency retract), or serial bit D0 is set low (sleep mode). The shutdown sequence is terminated by a programmable one-shot (brake delay). During the time-out (tDLY), both the spindle and VCM outputs are turned off. Simultaneously, a separate VCM retract circuit is activated. As shown in Figure 2, the all-bipolar design enables retract function all the way down to a supply of 1.41 V at VCLAMP pin. The retract current typically is 20 mA, adjustable with an external resistor, RRET. To limit retract velocity, a fixed clamp limits the voltage across VCM to no more than 440 mV. After the time-out, the retract circuitry is shut off while the spindle motor and VCM brake is activated by turning on all low-side DMOS drivers. To brake faster (i.e., with lower impedance short across the motor windings) the low-side drivers are powered by the residual charges on the CHS bypass capacitor.
FIGURE 2. Simplified Retract Circuit
Spindle Driver TABLE 3. Spindle PWM Speed Control (Double Integrator) System State
Run Run Run Run Spindle Brake/ Sleep
TABLE 4. Spindle Commutation Sequence Sequencer State
Reset * 1 2 3
PU
0 0 1 1 X
PD
0 1 0 1 X
POUT
1 Z Z 0 0
State
Decel Hold Hold Accel Accel
OUTA
Z High High Z Low Low Z
OUTB
Z Low Z High High Z Low
OUTC
Z Z Low Low Z High High
4 5 6
*Reset is the state after exiting sleep or spindle brake mode. Note: X = Don't Care, Z = High Impedance
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PIN DESCRIPTION POWER SUPPLIES
Function
VDD VMOT VCLAMP AGND GND
Pin Number
61 7, 8, 57, 58 53 24 3, 4, 11, 12, 36, 37, 38, 39, 42, 43
Description
+5-V supply for VCM and spindle controller logic. +5-V supply for VCM and spindle drivers. Inductive flyback clamp and emergency head retract power supply. This pin is shorted to VMOT by an on-chip switch during normal operation. The switch eliminates the need for an external Schottky diode. Low noise ground return for critical analog functions Ground return for the entire chip. All ground pins are connected to each other through the die substrate and lead frame. The large number of direct connections to the lead frame lowers thermal impedance and improves power dissipation. Output of the dc-todc converter, used to power VCM and spindle drive MOSFETs. The converter is a 3X charge pump capable of sourcing 5 mA. An external >0.1 F capacitor between Pin 56 and ground is necessary. Positive side of the external 3X charge pump capacitor. Positive side of the external 2X charge pump capacitor. 500-kHz oscillator output, used to drive the 3X charge pump. Inverted output of the on-chip 500-kHz oscillator, used to drive the external 2X charge pump capacitor. Low noise +5-V supply pin for the on-chip reference generator. Output of the on-chip reference generator: VR = VADIN/2. This is used as the dc reference level for all analog signals.
CHS CP2H CP1H CP2 CP1 VADIN VR
56 59 60 54 55 23 22
VOICE COIL MOTOR DRIVER
Function
GAIN SELECT VDAC OA3 IA4 OA4 ISENSE IN+ ISENSE INISENSE OUT OUT+ OUTIRET CDLY
Pin Number
2 16 15 14 13 62 63 64 5, 6 9, 10 1
Description
Input pin used to select VCM transconductance. A high input sets the gain to the maximum and a low input sets the gain to be 1/4 of the maximum. Inverting input of servo PWM filter amplifier. Output of servo PWM filter amplifier. Connect RC network from this pin to VDAC to set filter bandwidth. A positive OA3 relative to VR will set VCM output current positive. Inverting input of VCM loop compensation amplifier. Output of VCM loop compensation amplifier. Connect lead-lag network from this pin to IA4 to set desired loop bandwidth. Positive input terminal for VCM current sense amplifier. This pin connects to external sense resistor and VCM. Negative input terminal for VCM current sense amplifier. This pin connects to the other side of sense resistor and OUT+ pin. Output terminal of VCM current sense amplifier. VCM power amplifier positive output terminal. Current from OUT+ is positive. VCM power amplifier negative output terminal. During head retract, VCM output current will be negative, or flowing from this pin into the VCM load. Control pin for head retract current (nominally 0.25 V). An external resistor is connected to this pin. The current is amplified 200 times at the VCM driver. An external capacitor is connected to this pin to set the maximum head retract time, tDLY = 514 k x CDLY. At the end of the delay, the spindle motor is set to brake. A head retract may also be forced, by asserting this pin low.
21
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MICROCONTROLLER INTERFACE
Function
DATA CLK CS FAULT
Pin Number
18 19 20 17 Data input for the serial port. Clock input for serial port data.
Description
Strobe input for data word. System commands are executed at the rising edge of CS. Undervoltage flag output. Forced low if 5-V supply drops below 3.9 V, or the internal power-on reset timer (approximately 0.5 ms) is timing out.
DIAGNOSTIC FUNCTIONS
Function
MODE TEST
Pin Number
51 52
Description
Control input used for manufacture testing only. Grounded or left open during normal operation. Used as temperature test or step mode clock input. Controlled by serial port.
SPINDLE MOTOR DRIVER
Function
FCOM PU PD POUT IA2 OA2 IA1 OA1 RSPIN OUTA OUTB OUTC CST CWD CD1 CD2 CT
Pin Number
27
Description
Spindle commutation clock output. A positive going pulse is generated whenever a valid back EMF zero crossing is detected. The external speed control, working in either phase or frequency domain, compares this signal against a reference clock and feedbacks a PWM servo signal to the spindle driver via the PWM decoder and low-pass filter (A2). Pulse width modulation pull-up command from speed control. Pulse width modulation pull-down command from speed control. Pulse width modulation output from speed control. This pin is connected to the external integrating resistor of A2. POUT is low, or accelerating, if PU = high and PD = high. POUT is high, or decelerating, if PU = low and PD = low. POUT is tri-state, or holding, otherwise. Inverting input of spindle PWM low-pass filter amplifier. Output of spindle PWM low-pass filter amplifier. Connect RC network from this pin to IA2 to set desired cutoff frequency. Inverting input of spindle loop compensation amplifier. Output of spindle loop compensation amplifier. Connect RC lead-lag network from this pin to IA1 to set compensation. Connect an accurate external resistor from this pin to OA1 to set spindle transconductance and current limit. The recommended resistance is 17 k. Spindle phase A output terminal. Spindle phase B output terminal. Spindle phase C output terminal. An external capacitor connected to this pin will generate commutation pulses to start up the spindle motor. An external capacitor connected to this pin will disable the back EMF comparators during diode recirculation, detect incorrect motor rotation or stall. Connect at this pin one of the two external capacitors used to generate the ideal commutation point from the back EMF zero crossing points. Connect a second capacitor identical to CD1 at this pin to generate the optimum commutation delay. Spindle motor center tap input for back EMF sensing.
49 50 48 25 26 35 34 33 46, 47 44, 45 40, 41 31 30 29 28 32
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APPLICATION
64-Pin SQFP test board for typical 21/2" or smaller HDD (shown with external phase detector for spindle speed control and external PWM for VCM DAC)
VCM Design Equations:
(1) Transconductance (Gmv) 1 High Gain = ------------- ; G/SEL = High 4 RS 1 Low Gain = --------------- ; G/SEL = Low 16 R S (2) Output Retract Current 0.25 V I OUT = 200 x I RET = 200 x ---------------R RET
Spindle Design Equation:
8700 Transconductance ( G ms ) = --------------R SPIN (3) Transconductance Loop Compensation RS 4 ( 16 ) Closed-Loop BW = ---------------------------------- --------------------- 2 ( 10 K ) C L R M + R S RS 64 C L = ------------------------------------- --------------------- 2 ( 10 K ) BW R M + R S LM R L = --------------------------------C L ( RM + RS ) R M = Motor Resistance L M = Motor Inductance
or
(4) Refer to AN93-1 for all servo equations.
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APPLICATION
TABLE 5. Components for Test Board
Name
R1 R2 R3 R4 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 C1 C2 C3
Value
100 k 100 k 100 k 2.61 k 39 k 110 k 5.6 M 910 k 470 k 17 k 1.67 2.5 k 30 30 62 62 62 1.2 nF 100 pF 18 nF
Comments
VCM PWM Low Pass Filter VCM PWM Low Pass Filter VCM PWM Low Pass Filter VCM Transconductance Amplifier Compensator Spindle PWM Low Pass Filter Spindle PWM Low Pass Filter Spindle Speed Control Lead-Lag Compensator Spindle Speed Control Lead-Lag Compensator Spindle Speed Control Lead-Lag Compensator RSPIN Resistor VCM Sense Resistor VCM Retract Bias Resistor (RRET) VCM Snubber Resistor VCM Snubber Resistor Spindle Snubber Resistor Spindle Snubber Resistor Spindle Snubber Resistor VCM PWM Low Pass Filter VCM PWM Low Pass Filter VCM Transconductance Amplifier Compensator
Name
C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22
Value
27 nF 680 pF 1.8 nF 1.8 nF 0.22 nF 2.7 nF 2.2 nF 10 nF 82 nF 82 nF 100 nF 100 nF 180 nF 180 nF 180 nF 0.1 F 0.1 F 0.1 F 180 nF
Comments
Spindle Start-Up Capacitor Spindle Watch-Dog Capacitor Spindle Commutation Delay Capacitor #1 Spindle Commutation Delay Capacitor #2 Spindle Loop `Zero' Capacitor Spindle PWM Low Pass Filter Spindle Speed Control Lead-Lag Compensator Spindle Speed Control Lead-Lag Compensator Charge Pump Capacitor #1 Charge Pump Capacitor #2 VCM Snubber Capacitor VCM Snubber Capacitor Spindle Snubber Capacitor Spindle Snubber Capacitor Spindle Snubber Capacitor Bypass Capacitor Bypass Capacitor Bypass Capacitor Brake Delay Capacitor (CDLY)
Note: These values are entirely dependent on motor characteristics.
PACKAGE OUTLINE: SQFP 64-PIN
Millimeters Dim
A A1 b C D D1 e L L1 L2 S
Inches* Min
0.053 0.002 0.006 0.005 0.390 0.461 0.016 0.425 0.012 0
Min
1.35 0.04 0.14 0.117 9.90 11.7 0.40 10.80 0.30 0
Max
1.60 0.16 0.26 0.177 10.10 12.3 0.60 10.80 11.20 0.70 1.20 4
Max
0.063 0.006 0.010 0.007 0.398 0.484 0.024 0.425 0.441 0.028 0.047 4
*For Reference Only
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