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18Mb Pipelined QDRTMII SRAM Burst of 2
Features
x x x x x x
Description
Advance Information IDT71P72204 IDT71P72104 IDT71P72804 IDT71P72604
x x x
x x x
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36) Separate, Independent Read and Write Data Ports Supports concurrent transactions Dual Echo Clock Output 2-Word Burst on all SRAM accesses DDR (Double Data Rate) Multiplexed Address Bus One Read and One Write request per clock cycle DDR (Double Data Rate) Data Buses Two word burst data per clock on each port Four word transfers per clock cycle (2 word bursts on 2 ports) Depth expansion through Control Logic HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V to 1.9V. Scalable output drivers Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V. Output Impedance adjustable from 35 ohms to 70 ohms 1.8V Core Voltage (VDD) 165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package JTAG Interface
The IDT QDRIITM Burst of two SRAMs are high-speed synchronous memories with independent, double-data-rate (DDR), read and write data ports. This scheme allows simultaneous read and write access for the maximum device throughput, with two data items passed with each read or write. Four data word transfers occur per clock cycle, providing quad-data-rate (QDR) performance. Comparing this with standard SRAM common I/O (CIO), single data rate (SDR) devices, a four to one increase in data access is achieved at equivalent clock speeds. Considering that QDRII allows clock speeds in excess of standard SRAM devices, the throughput can be increased well beyond four to one in most applications. Using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses. All buses associated with the QDRII are unidirectional and can be optimized for signal integrity at very high bus speeds. The QDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. The QDRII has a single DDR address bus with multiplexed read and write addresses. All read addresses are received on the first half of the clock cycle and all write addresses are received on the second half of the clock cycle. The read and write enables are received on the first half of the clock cycle. The byte and nibble write signals are received on both halves of the clock cycle simultaneously with the data they are controlling on the data input bus. The QDRII has echo clocks, which provide the user with a clock
Functional Block Diagram
( N o te 1 ) D (N o te 1 ) D A TA REG DAT A REG (N o te 1 )
W R IT E D R IV E R A
R W BWx
(N o te 3 )
CTRL L O G IC
18M MEMORY ARRA Y
(N o te 4 )
(N o te 4 )
OUTPUT SELECT
(N o te 2 )
SENSE AMPS
OUTPUT REG
ADD REG
(N o te 2 )
W RITE/READ DECODE
(N o te 1 )
Q
K K C C
CLK GEN S E LE CT O UT P UT CO N TRO L
61 09 drw 16
CQ
CQ
Notes 1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36 2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36. 3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a "nibble write" and there are 2 signal lines. 4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36. AUGUST 2003 1
(c)2003 Integrated Device Technology, Inc. "QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. " DSC-6109/00
IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
that is precisely timed to the data output, and tuned with matching impedance and signal quality. The user can use the echo clock for downstream clocking of the data. Echo clocks eliminate the need for the user to produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture. Since the echo clocks are generated by the same source that drives the data output, the relationship to the data is not significantly affected by voltage, temperature and process, as would be the case if the clock were generated by an outside source. All interfaces of the QDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. The device is capable of sustaining full bandwidth on both the input and output ports simultaneously. All data is in two word bursts, with addressing capability to the burst level.
Echo Clock
The echo clocks, CQ and CQ, are generated by the C and C clocks (or K, K if C, C are disabled). The rising edge of C generates the rising edge of CQ, and the falling edge of CQ. The rising edge of C generates the rising edge of CQ and the falling edge of CQ. This scheme improves the correlation of the rising and falling edges of the echo clock and will improve the duty cycle of the individual signals. The echo clock is very closely aligned with the data, guaranteeing that the echo clock will remain closely correlated with the data, within the tolerances designated.
Read and Write Operations
QDRII devices internally store the two words of the burst as a single, wide word and will retain their order in the burst. There is no ability to address to the single word level or reverse the burst order; however, the byte and nibble write signals can be used to prevent writing any individual bytes, or combined to prevent writing one word of the burst. Read operations are initiated by holding the read port select (R) low, and presenting the read address to the address port during the rising edge of K which will latch the address. The data will then be read and will appear at the device output at the designated time in correspondence with the C and C clocks. Write operations are initiated by holding the write port select (W) low and designating with the Byte Write inputs (BWx) which bytes are to be written (or NWx on x8 devices). The first word of the data must also be present on the data input bus D[X:0]. Upon the rising edge of K the first word of the burst will be latched into the input register. After K has risen, and the designated hold times observed, the second half of the clock cycle is initiated by presenting the write address to the address bus A[X:0], the BWx (or NWx) inputs for the second data word of the burst, and the second data item of the burst to the data bus D[X:0]. Upon the rising edge of K, the second word of the burst will be latched, along with the designated address. Both the first and second words of the burst will then be written into memory as designated by the address and byte write enables.
Clocking
The QDRII SRAM has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the QDRII has an output "echo" clock, CQ, CQ. The K and K clocks are the primary device input clocks. The K clock is, used to clock in the control signals (R, W and BWx or NWx), the read address, and the first word of the data burst during a write operation. The K clock is used to clock in the control signals (BWx or NWx), write address and the second word of the data burst during a write operation. The K and K clocks are also used internally by the SRAM. In the event that the user disables the C and C clocks, the K and K clocks will also be used to clock the data out of the output register and generate the echo clocks. The C and C clocks may be used to clock the data out of the output register during read operations and to generate the echo clocks. C and C must be presented to the SRAM within the timing tolerances. The output data from the QDRII will be closely aligned to the C and C input, through the use of an internal DLL. When C is presented to the QDRII SRAM, the DLL will have already internally clocked the data to arrive at the device output simultaneously with the arrival of the C clock. The C and second data item of the burst will also correspond.
Output Enables
The QDRII SRAM automatically enables and disables the Q[X:0] outputs. When a valid read is in progress, and data is present at the output, the output will be enabled. If no valid data is present at the output (read not active), the output will be disabled (high impedance). The echo clocks will remain valid at all times and cannot be disabled or turned off. During power-up the Q outputs will come up in a high impedance state.
Single Clock Mode
The QDRII SRAM may be operated with a single clock pair. C and C may be disabled by tying both signals high, forcing the outputs and echo clocks to be controlled instead by the K and K clocks.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output drive impedance. The value of RQ must be 5X the value of the intended drive impedance of the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of +/- 10% is between 175 ohms and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted every 1024 clock cycles to correct for drifts in supply voltage and temperature. If the user wishes to drive the output impedance of the SRAM to it's lowest value, the ZQ pin may be tied to VDDQ.
DLL Operation
The DLL in the output structure of the QDRII SRAM can be used to closely align the incoming clocks C and C with the output of the data, generating very tight tolerances between the two. The user may disable the DLL by holding Doff low. With the DLL off, the C and C (or K and K if C and C are not used) will directly clock the output register of the SRAM. With the DLL off, there will be a propagation delay from the time the clock enters the device until the data appears at the output.
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IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Pin Definitions
Symbol Pin Function Input Synchronous Description Data input signals, sampled on the rising edge of K and K clocks during valid write operations 2M x 8 -- D[7:0] 2M x 9 -- D[8:0] 1M x 18 -- D[17:0] 512K x 36 -- D[35:0] Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks d uring write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding b yte of data to be ignored and not written in to the device. 2M x 9 -- BW0 controls D[8:0] 1M x 18 -- BW0 controls D[8:0] and BW1 controls D[17:9] 512K x 36 -- BW0 controls D[8:0], BW1 controls D[17:9], BW2 controls D[26:18] and BW3 controls D[35:27] Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects. Sampled on the rising edge of the K and K clocks during write operations. Used to select which nibble is written into the device during the current portion of the write operations. Nibbles not written remain unaltered. All the nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written in to the device. Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations. Write addresses are sampled on the rising edge of K clock during active write operations. These address inputs are multiplxed, so that both a read and write operation can occur on the same clock cycle. These inputs are ignored when the appropriate port is deselected. Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when operating in single clock mode. When the Read port is deselected, Q[X:0] are automatically three-stated.
D[X:0]
BW0, BW1 BW2, BW3
Input Synchronous
NW0 NW1
Input Synchronous
A
Input Synchronous
Q[X:0]
Output Synchronous
W
Input Synchronous
Write Control Logic active Low. Sampled on the rising edge of the positive input clock (K). When asserted active, a write operation in initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[X:0] to be ignored. Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfer. Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data thro ugh Q[X:0] when in single clock mode. Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals are free running and do not stop when the output data is tri-stated. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
6109 tbl 02a
R
Input Synchronous
C
Input Clock
C
Input Clock
K
Input Clock
K
Input Clock
CQ, CQ
Output Clock
ZQ
Input
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IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Pin Definitions continued
Symbol Pin Function Description DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be different from those listed in this data sheet. There will be an increased propagation delay from the incidence of C and C to Q, or K and K to Q as configured. The propagation delay is not a tested parameter, but will be similar to the propagation delay of other SRAM devices in this speed grade. TDO pin for JTAG TCK pin for JTAG. TDI pin for JTAG. An internal resistor will pull TDI to VDD when the pin is unconnected. TMS pin for JTAG. An internal resistor will pull TMS to VDD when the pin is unconnected. No connects inside the package. Can be tied to any voltage level Input Reference Power Supply Ground Power Supply Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Power supply inputs to the core of the device. Should be connected to a 1.8V power supply. Ground for the device. Should be connected to ground of the system. Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the desired output voltage.
6109 tbl 02b
Doff
Input
TDO TCK TDI TMS NC
Output Input Input Input
VREF
VDD
VSS
VDDQ
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IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Pin Configuration 2M x 8
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO
2 VSS NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK
3 A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A
4 W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5 NW1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A
A
6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7 NC
NW0
8 R A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10 VSS NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS
6109 tbl 12
11 CQ Q3 D3
NC
A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
165-ball FBGA Pinout TOP VIEW
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IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Pin Configuration 2M x 9
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO
2 VSS NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK
3 A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A
4 W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5 NC NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C
7 NC BW A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8 R A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10 VSS NC NC NC D2 NC NC VREF Q1 NC NC NC NC D8 TMS
11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC Q8 TDI
6109 tb l 12a
165-ball FBGA Pinout TOP VIEW
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IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Pin Configuration 1M x 18
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 VSS Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 NC D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A 4 W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BW1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC BW0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 R A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 VSS NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
6109 tbl 12b
165-ball FBGA Pinout TOP VIEW
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IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Pin Configuration 512K x 36
1 A B C D E F G H J K L M N P R CQ Q27 D27 D28 Q29 Q30 D30 Doff D31 Q32 Q33 D33 D34 Q35 TDO 2 VSS Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 NC D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A 4 W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BW2 BW3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 BW1 BW0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 R A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 NC D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A 10 VSS Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
6109 tb l 12c
165-ball FBGA Pinout TOP VIEW
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IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Absolute Maximum Ratings(1)
Symbol VTERM VTERM VTERM TBIAS TSTG IOUT Rating Supply Voltage on VDD with Respect to GND Supply Voltage on VDDQ with Respect to GND Voltage on Input, Output and I/O terminals with respect to GND Temperature Under Bias Storage Temperature Continuous Current into Outputs Value -0.5 to +2.9 -0.5 to VDD+0.3 -0.5 to VDDQ+0.3 -55 to +125 -65 to +150 + 20 Unit V V V C C mA
6109 tbl 05
Capacitance (TA = +25C, f = 1.0MHz)(1)
Symbol CIN CCLK CO Parameter Input Capacitance Clock Input Capacitance Output Capacitance VDD = 1.8V VDDQ = 1.5V Conditions Max. 5 6 7 Unit pF pF pF
6109 tbl 06
NOTE: 1. Tested at characterization and retested after any design or process change that may affect these parameters.
Recommended DC Operating Conditions
Symbol VDD VDDQ VSS VREF VIH VIL Parameter Power Supply Voltage I/O Supply Voltage Ground Input Reference Voltage Input High Voltage Input Low Voltage Ambient Temperature Min. 1.7 1.4 0 VREF+0.1 -0.3 0 Typ. 1.8 1.5 0 VDDQ/2 - - 25 Max. 1.9 1.9 0 VDDQ+0.3 VREF-0.1 +70 Unit V V V V V V
o
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Write Descriptions
Signal Write Byte 0 Write Byte 1 Write Byte 2 Write Byte 3 Write Nibble 0 Write Nibble 1 BW0 L X X X X X BW1 X L X X X X
(1,2)
TA
c
6109 tbl 04
BW2 X X L X X X
BW3 X X X L X X
NW0 X X X X L X
NW1 X X X X X L
6109 tbl 09
Notes:
1) All byte write (BWx) and nibble write (NWx) signals are sampled on the rising edge of K and again on K. The data that is present on the data bus in the designated byte/nibble will be latched into the input if the corresponding BWx or NWx is held low. The rising edge of K will sample the first byte/nibble of the two word burst and the rising edge of K will sample the second byte/ nibble of the two word burst. 2) The availability of the BWx or NWx on designated devices is described in the pin description table. 3) The QDRII Burst of two SRAM has data forwarding. A read request that is initiated on the same cycle as a write request to the same address will produce the newly written data in response to the read request.
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IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Application Example
W
SRAM #1 D SA R W B W 0 B W 1 C C ZQ Q KK 250
SRAM #4
VT R Data In Data Out Address R W BW0- 7 MEMORY CONTROLLER Return CLK Source CLK Return CLK Source CLK R = 50 VT VT R R
D SA R W BW0 BW1 C C
ZQ Q KK R R
250
VT
VT = VREF
6109 drw 20
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IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8 100mV, VDDQ = 1.4V to 1.9V)
Parameter Input Leakage Current Output Leakage Current Symbol IIL IOL Test Conditions VDD = Max VIN = VSS to VDDQ Output Disabled 250MHZ Operating Current (x36,x18,x9,x8) DDR IDD VDD = Max, IOUT = 0mA Cycle Time > tKHKH Min 200MHZ 167MHZ 133MHZ Device Deselected, IOUT = 0mA, f=Max, All Inputs <0.2V or > VDD -0.2V 250MHZ 200MHZ 167MHZ 133MHZ Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Input Low Voltage Input High Voltage VOH1 VOL1 VOH2 VOL2 VIL VIH See Note 2 See Note 3 IOH = -0.1mA IOL = 0.1mA Min -10 -10 VDDQ/2-0.12 VDDQ/2-0.12 VDDQ-0.2 VSS -0.3 VREF+0.1 Max +10 +10 TBD TBD mA TBD TBD TBD TBD mA TBD TBD VDDQ/2+0.12 VDDQ/2+0.12 VDDQ 0.2 VREF-0.1 VDDQ+0.3 V V V V V V 2,7 3,7 4 4 8,9 8,10
6109 tbl 10c
Unit A A
Note
1,5
1,6
Standby Current (NOP): DDR
ISB1
Notes:
1. Minimum cycle. IOUT = 0mA. 2. IOH = -(VDDQ/2)/(RQ/5) for 175 < RQ < 350. 3. IOL = (VDDQ/2)/(RQ/5) for 175 < RQ < 350. 4. Minimum Impedance Mode when ZQ pin is connected to VDDQ. 5. Operating Current is calculated with 50% read cycles and 50% write cycles. 6. Standby Current is only after all pending read and write burst operations are completed. 7. Programmable Impedance Mode. 8. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 9. VIL (Min) DC = -0.3V, VIL (Min) AC = -1.5V (pulse width <3ns). 10. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDDQ+0.85V (pulse width<3ns)
AC Test Conditions AC Test Loads
Parameter Core Power Supply Voltage Output Power Supply Voltage Input High/Low Level Input Reference Level Symbol VDD VDDQ VIH/VIL VREF TR/TF Value 1.7-1.9 1.4-1.9 1.25/0.25 0.75 0.6/0.6 VDDQ/2 Unit V V V V ns V
6109tbl 11a
VREF OUTPUT Device Under Test ZQ
0.75V
Input Rise/Fall Time Output Timing Reference Level
Z0 =50 RQ = 250
RL = 50 VDDQ/2
NOTE: 1. Parameters are tested with RQ=250
6109 drw 04
1.25V 0.75V 0.25V
6109 drw 06
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IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
AC Electrical Characteristics
Symbol Clock Parameters tKHKH tKC var tKHKL tKLKH tKHKH tKHKH tKHCH tKC lock tKC reset Average clock cycle time (K,K,C,C) Clock Phase Jitter (K,K,C,C) Clock High Time (K,K,C,C) Clock LOW Time (K,K,C,C) Clock to clock (KK,CC) Clock to clock (KK,CC) Clock to data clock (KC,KC) DLL lock time (K, C) K static to DLL reset Parameter
(VDD = 1.8 100mV, VDDQ = 1.4V to 1.9V)(3)
250MHz Min. Max 200MHz Min. Max 167MHz Min. Max 133MHz
Min Max
Unit
Notes
4.00 1.60 1.60 1.80 1.80 0.00 1024 30
5.25 0.20 1.80 -
5.00 2.00 2.00 2.20 2.20 0.00 1024 30
6.30 0.20 2.30 -
6.00 2.40 2.40 2.70 2.70 0.00 1024 30
7.88 0.20 2.80 -
7.50 3.00 3.00 3.38 3.38 0.00 1024 30
8.40 0.20 3.55 -
ns ns ns ns ns ns ns cycles ns 6 5
Output Parameters tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCHQZ tCHQX1 C,C HIGH to output valid C,C HIGH to output hold C,C HIGH to echo clock valid C,C HIGH to echo clock hold CQ,CQ HIGH to output valid CQ,CQ HIGH to output hold C HIGH to output High-Z C HIGH to output Low-Z -0.45 -0.45 -0.30 -0.45 0.45 0.45 0.30 0.45 -0.45 -0.45 -0.35 -0.45 0.45 0.45 0.35 0.45 -0.50 -0.50 -0.40 -0.50 0.50 0.50 0.40 0.50 -0.50 -0.50 -0.40 -0.50 0.50 0.50 0.40 0.50 ns ns ns ns ns ns ns ns 7 7 3 3 3 3
Set-Up Times tAVKH tIVKH tDVKH Address valid to K,K rising edge Control inputs valid to K,K rising edge Date-in valid to K, K rising edge 0.40 0.40 0.40 0.40 0.40 0.40 0.50 0.50 0.50 0.50 0.50 0.50 ns ns ns 2
Hold Times tKHAX tKHIX tKHDX K,K rising edge to address hold K,K rising edge to control inputs hold K, K rising edge to data-in hold 0.40 0.40 0.40 0.40 0.40 0.40 0.50 0.50 0.50 0.50 0.50 0.50 ns ns ns
6109 tbl 11
NOTES: 1. All address inputs must meet the specified setup and hold times for all latching clock edges. 2. Control signals are R, W,BW0,BW1 and (NW0,NW1, for x8) and (BW2,BW3 also for x36) 3. If C,C are tied high, K,K become the references for C,C timing parameters. 4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. 5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable. 7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a + 0.1 ns variation from echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
6.42 12
IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Timing Waveform of Combined Read and Write Cycles
Read A0 1 Write A1 2 Read A2 3 Write A3 4 Read A4 5 Write A5 6 NOP 7 Write A6 8 NOP 9 NOP 10
K
tKHKL tKLKH tKHKH tKHKH
K
R
tIVKH tKHIX
W
A
A0
A1
A2
A3
A4
A5
A6
tAVKH tKHAX
tAVKH tKHAX
D
D10
D11
D30
D31
D50
D51
D60
D61
tDVKH tKHDX
tDVKH tKHDX
Q
tCHQX1
Q00
Q01
Q20
Q21
Q40
Q41
tCHQZ
tCHQX tKHCH tKLKH tCHQV
tCHQX tCHQV
tCQHQV
C
tKHKL tKHCH tKHKH tKHKH
C
tCHCQV tCHCQX
CQ
tCHCQV tCHCQX
CQ
6109 drw 09a
6.42 13
IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up; therefore, the TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may also be tied to VDD through a register. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 0 0 IR1 0 0 1 1 0 0 1 1 IR0 0 1 0 1 0 1 0 1 Instruction EXTEST IDCODE SAMPLE-Z RESERVED TDO Output Boundary Scan Register Identification register Boundary Scan Register Do Not Use 2 1 5 4 5 5 3
6109tbl 13
Notes
A,D K,K C,C Q CQ CQ
0
SRAM CO RE
0 1 1
SAMPLE/PRELOAD Boundary Scan register RESERVED RESERVED BYPASS Do Not Use Do Not Use Bypass Register
TDI
BYPASS Re g. Iden tifica tion Re g. Ins tru ction Re g. C ontrol Signals
1
TDO
1
NOTE:
1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. Bypass register is initiated to Vss when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 4. SAMPLE instruction does not place Qs in Hi-Z. 5. This instruction is reserved for future use.
1
TMS TCK
T AP Co ntroller
6109 drw 18
TAP Controller State Diagram
1
Test Logic Reset 0 Run Test Idle 1 Select DR 0 1 Capture DR 0 Shift DR 1 1 Exit 1 DR 0 Pause DR 1 Exit 2 DR 1 1 Update DR 0 1 1 Select IR 0 Capture IR 0 Shift IR 1 1 Exit 1 IR 0 Pause IR 1 Exit 2 IR 1 Update IR 1 0
0
0
0
0 0
0 0
6109 drw 17
6.42 14
IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Scan Register Definition
Part 512Kx36 1Mx18 2Mx8/x9 Instruction Register 3 bits 3 bits 3 bits Bypass Register 1 bit 1 bit 1 bit ID Register 32 bits 32 bits 32 bits Boundary Scan 109 bits 109 bits 109 bits
6109 tbl 14
Identification Register Definitions
INSTRUCTION FIELD Revision Number (31:29) Device ID (28:12) 0010 0010 0010 0010 ALL DEVICES 000 0100 0100 0100 0101 0100 0110 0100 0111 0x33 1 Revision Number 512Kx36 1Mx18 2Mx9 2Mx8 QDRII Burst of 2 71P72604S 71P72804S 71P72104S 71P72204S DESCRIPTION PART NUMBER
IDT JEDEC ID CODE (11:1)
Allows unique identification of SRAM vendor. Indicates the presence of an ID register.
ID Register Presence Indicator (0)
6109 tbl 15
6.42 15
IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Boundary Scan Exit Order
ORDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PIN ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E
6109 tbl 16
ORDER 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN ID 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A VSS 1A 2B 3B 1C 1B 3D 3C 1D
6109 tbl 17
ORDER 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
PIN ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R
6109 tbl 18
6.42 16
IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
JTAG DC Operating Conditions
P aram e te r Outp ut P o w e r S up p ly P o we r S up p ly Vo ltag e Inp ut H ig h Le v e l Inp ut Lo w Le v e l Outp ut Hig h Vo ltag e (IO H = -1m A ) Outp ut Lo w Vo ltag e (IO L = 1m A ) Symbol V DD Q V DD V IH V IL V OH VOL M in 1.4 1.7 1.3 -0.3 V D DQ - 0.2 VSS Ty p 1.8 M ax 1.9 1.9 V DD + 0.3 0.5 V DD 0.2 Unit V V V V V V 1 1
6109 tb l 1 9
No te
Note: 1. ZQ = VDDQ2
JTAG AC Test Conditions
Parameter Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level Symbol VIH/VIL TR/TF Min 1.3/0.5 1.0/1.0 VDDQ/2 Unit V ns V
6109 tbl 20
Note
JTAG AC Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time SRAM Input Setup Time SRAM Input Hold Time Clock Low to Output Valid Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLQV Min 50 20 20 5 5 5 5 5 5 0 Max 10 Unit ns ns ns ns ns ns ns ns ns ns
6109 tbl.21
Note
JTAG Timing Diagram
TCK
tCH C H tM V C H
tC H C L tC H M X
tCLC H
TMS
tDV C H
tC H D X
TDI
tS V C H
tC H S X
TD O
tCLQ V 6 1 0 9 d rw 1 9
6.42 17
IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
6.42 18
IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Ordering Information
IDT 71P72XXX Device Type S Power XXX Speed BQ X
Package Process Temperature Range
Blank BQ
Commercial (0oC to +70oC) 165 Fine Pitch Ball Grid Array (fBGA)
133 167 200 250
Clock Frequency in MegaHertz
IDT71P72204 IDT71P72104 IDT71P72804 IDT71P72604
2M x 8 QDR II SRAM 2M x 9 QDR II SRAM 1M x 18 QDR II SRAM 512K x 36 QDR II SRAM
6109 drw 15
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: sramhelp@idt.com 800-544-7726, x4033
"QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. "
6.42 19
IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18 x -Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range
Revision History
Revision O Date 8/1/03 Pages 1-20 Description Initial Advance Information Data Sheet Release

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