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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT153 Dual 4-input multiplexer Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Dual 4-input multiplexer FEATURES * Non-inverting output * Separate enable for each output * Common select inputs * See `253" for 3-state version * Permits multiplexing from n lines to 1 line * Enable line provided for cascading (n lines to 1 line) * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT153 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT153 have two identical 4-input multiplexers which select two bits of data from up to four sources selected by common data select inputs (S0, S1). The two 4-input multiplexer circuits have individual active LOW output enable inputs (1E, 2E) which can be used to strobe the outputs independently. The outputs (1Y, 2Y) are forced LOW when the corresponding output enable inputs are HIGH. The "153" is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels applied to S0 and S1. 74HC/HCT153 The logic equations for the outputs are: 1Y = 1E.(1I0.S1.S0+1I1.S1.S0+ +1I2.S1.S0+1I3.S1.S0) 2Y = 2E.(2I0.S1.S0+2I1.S1.S0+ +2I2.S1.S0+2I3.S1.S0) The "153" can be used to move data to a common output bus from a group of registers. The state of the select inputs would determine the particular register from which the data came. An alternative application is a function generator. The device can generate two functions or three variables. This is useful for implementing highly irregular random logic. The "153" is similar to the "253" but has standard outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay 1In, 2In to nY Sn to nY nE to nY CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V (CL x VCC2 x fo) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". input capacitance power dissipation capacitance per multiplexer notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 14 15 10 3.5 30 16 17 11 3.5 30 ns ns ns pF pF HCT UNIT December 1990 2 Philips Semiconductors Product specification Dual 4-input multiplexer PIN DESCRIPTION PIN NO. 1, 15 14, 2 6, 5, 4, 3 7 8 9 10, 11, 12, 13 16 SYMBOL 1E, 2E S0, S1 1I0 to 1I3 1Y GND 2Y 2I0 to 2I3 VCC NAME AND FUNCTION output enable inputs (active LOW) common data select inputs data inputs from source 1 multiplexer output from source 1 ground (0 V) multiplexer output from source 2 data inputs from source 2 positive supply voltage 74HC/HCT153 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. Fig.4 Functional diagram. December 1990 3 Philips Semiconductors Product specification Dual 4-input multiplexer FUNCTION TABLE SELECT INPUTS S0 X L L H H L L H H Note 1. H = HIGH voltage level L = LOW voltage level X = don't care S1 X L L L L H H H H nI0 X L H X X X X X X DATA INPUTS nI1 X X X L H X X X X nI2 X X X X X L H X X nI3 X X X X X X X L H OUTPUT ENABLE nE H L L L L L L L L 74HC/HCT153 OUTPUT nY L L H L H L H L H Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification Dual 4-input multiplexer DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH propagation delay 1In to nY; 2In to nY propagation delay Sn to nY propagation delay nE to nY 47 17 14 50 18 14 33 12 10 19 7 6 max. 145 29 25 150 30 26 100 20 17 75 15 13 -40 to+85 min. max. 180 36 31 190 38 33 125 25 21 95 19 16 -40 to+125 min. max. 220 44 38 225 45 38 150 30 26 110 22 19 ns UNIT 74HC/HCT153 TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 tPHL/ tPLH ns Fig.7 tPHL/ tPLH ns Fig.7 tTHL/ tTLH output transition time ns Figs 6 and 7 December 1990 5 Philips Semiconductors Product specification Dual 4-input multiplexer DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types 74HC/HCT153 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT 1In, 2In nE Sn UNIT LOAD COEFFICIENT 0.45 0.60 1.35 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. tPHL propagation delay 1In to nY; 2In to nY propagation delay 1In to nY; 2In to nY propagation delay Sn to nY propagation delay nE to nY output transition time typ. 19 -40 to+85 max. min. 34 max. 43 -40 to+125 min. max. 51 ns 4.5 Fig.6 UNIT VCC (V) WAVEFORMS TEST CONDITIONS tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH 13 24 30 36 ns 4.5 Fig.6 20 14 7 34 27 15 43 34 19 51 41 22 ns ns ns 4.5 4.5 4.5 Fig.7 Fig.7 Figs 6 and 7 December 1990 6 Philips Semiconductors Product specification Dual 4-input multiplexer AC WAVEFORMS 74HC/HCT153 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (1In, 2In) to output (1Y, 2Y) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the select input (S0, S1) and the output enable input (E) to output (1Y, 2Y) propagation delays and the output transition times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 7 |
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