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TSA1201
12-BIT, 50MSPS, 150mW A/D CONVERTER
s 40mW @5Msps, 150mW @ 50Msps s 2.5V supply voltage with 2.5V/3.3V compatibility for digital I/O Input range: 2Vpp differential SFDR up to 77dB @ 50Msps, Fin=15MHz ENOB up to10.5 bits @ 50Msps, Fin=15MHz Built-in reference voltage with external bias capability s Pinout compatibility with TSA0801, TSA1001 and TSA1002 ORDER CODE
Part Number TSA1201IF TSA1201IFT EVAL1201/AA Temperature Range -40C to +85C -40C to +85C Package TQFP48 TQFP48 Conditioning Tray Tape & Reel Marking SA1201I SA1201I
s s s s
Evaluation board
PIN CONNECTIONS (top view)
DESCRIPTION The TSA1201 is a 12-bit, 50MHz maximum sampling frequency Analog to Digital converter using a CMOS technology combining high performances and very low power consumption. The TSA1201 is based on a pipeline structure and digital error correction to provide excellent static linearity and achieve 10.5 effective bits at Fs=50Msps, and Fin=15MHz, with a global power consumption of 150mW. The TSA1201 features adaptive behavior to the application. Its architecture allows to sample from 0.5Msps up to 50Msps, with a programmable power consumption which makes the application board even more optimized. It integrates a proprietary track-and-hold structure to ensure an high analog bandwidth of 1GHz and enable IF-sampling. Several features are available on the device. A voltage reference is integrated in the circuit. Differential or single-ended analog inputs can be applied. The output data can be coded into two differential formats. A Data Ready signal is raised as the data is valid on the output and can be used for synchronization purposes. The TSA1201 is available in extended (-40C to +85C) temperature range, in small 48 pins TQFP package. APPLICATIONS
GNDBE VCCBE VCCBI AVCC AGND AVCC DFSB
OEB
SRC
DR
NC
NC
index corner
48 IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM 1 2 3 4 5 6 7 8 9
47 46
45
44 43
42
41
40
39
38 37 36 NC 35 D0 (LSB) 34 D1 33 D2 32 D3 31 D4
TSA1201
30 D5 29 D6 28 D7 27 D8 26 D9 25 D10
AGND 10 AVCC 11 AVCC 12 13 14 15 16 17 18 19 20 21 22 23 24
DVCC
DVCC
DGND
CLK
DGND
NC
DGND
GNDBI
GNDBE
VCCBE
OR
D11 (MSB)
PACKAGE
7 x 7 mm TQFP48
s s s s s s
High speed data acquisition High End cameras Medical imaging and ultrasound Portable instrumentation High speed DSP interface Digital communication - IF sampling
September 2002
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TSA1201
ABSOLUTE MAXIMUM RATINGS
Symbol AVCC DVCC VCCBI VCCBE Tstg ESD Analog Supply voltage Digital Supply voltage
1)
Parameter
Values 0 to 3.3 0 to 3.3
Unit V V V V C KV
1) 1) 1)
Digital buffer Supply voltage Digital buffer Supply voltage Storage temperature Electrical Static Discharge - HBM - CDM-JEDEC Standard
0 to 3.3 0 to 3.6 +150 2 1.5
1. All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must never exceed -0.3V or VCC+0V
OPERATING CONDITIONS
Symbol AVCC DVCC VCCBI VCCBE VREFP Analog Supply voltage Digital Supply voltage Internal buffer Supply voltage External buffer Supply voltage Forced top reference voltage
1)
Parameter
Min 2.25 2.25 2.25 2.25 0.5 0 0.2
Typ 2.5 2.5 2.5 2.5 1 0 0.5
Max 2.7 2.7 2.7 3.5 1.8 0.5 1.1
Unit V V V V V V V
VREFM Forced bottom reference voltage 1) INCM
1)
Forced input common mode voltage
Condition VRefP-VRefM>0.3V
BLOCK DIAGRAM
+2.5V +2.5V/3.3V VREFP
GNDA VIN INCM VINB stage 1 stage 2 stage n Reference circuit IPOL VREFM DFSB Sequencer-phase shifting CLK SRC OEB
Timing
Digital data correction DR DO TO D11 OR GND
Buffers
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TSA1201
PIN CONNECTIONS (top view)
GNDBE VCCBE VCCBI AVCC AGND
AVCC
DFSB
OEB
SRC
DR
NC
NC
index corner
48 IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM 1 2 3 4 5 6 7 8 9
47 46
45
44 43
42
41
40
39
38 37 36 NC 35 D0 (LSB) 34 D1 33 D2 32 D3 31 D4
TSA1201
30 D5 29 D6 28 D7 27 D8 26 D9 25 D10
AGND 10 AVCC AVCC 11 12 13 14 15 16 17 18 19 20 21 22 23 24
DVCC
DVCC
DGND
CLK
DGND
NC
DGND
GNDBI
GNDBE
VCCBE
OR
D11 (MSB)
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM AGND AVCC AVCC DVCC DVCC DGND CLK DGND NC DGND GNDBI GNDBE VCCBE OR Description Analog bias current input Top voltage reference Bottom voltage reference Analog ground Analog input Analog ground Inverted analog input Analog ground Input common mode Analog ground Analog power supply Analog power supply Digital power supply Digital power supply Digital ground Clock input Digital ground Non connected Digital ground Digital buffer ground Digital buffer ground Digital buffer power supply Out Of Range output 0V 0V 0V 2.5V/3.3V CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) 1V 0V 0V 1Vpp 0V 1Vpp 0V 0.5V 0V 2.5V 2.5V 2.5V 2.5V 0V 2.5V compatible CMOS input 0V Observation Pin No 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0(LSB) NC NC DR VCCBE GNDBE VCCBI NC SRC OEB DFSB AVCC AVCC AGND Description Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Least Significant Bit output Non connected Non connected Data Ready output Digital Buffer power supply Digital Buffer ground Digital Buffer power supply Non connected Slew rate control input Output Enable input Data Format Select input Analog power supply Analog power supply Analog ground 2.5V/3.3V CMOS input 2.5V/3.3V CMOS input 2.5V/3.3V CMOS input 2.5V 2.5V 0V CMOS output (2.5V/3.3V) 2.5V/3.3V 0V 2.5V Observation CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V) CMOS output (2.5V/3.3V)
D11(MSB) Most Significant Bit output
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TSA1201
CONDITIONS AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2MHz, Vin@ -1dBFS, VREFM=0V Tamb = 25C (unless otherwise specified) TIMING CHARACTERISTICS
Symbol FS DC TC1 TC2 Tod Tpd Ton Toff Parameter Sampling Frequency Clock Duty Cycle Clock pulse width (high) Clock pulse width (low) Data Output Delay (Fall of Clock 6pF load capacitance to Data Valid) Data Pipeline delay Falling edge of OEB to digital output valid data Rising edge of OEB to digital output tri-state Test conditions Min 0.5 45 9 9 50 10 10 8 5.5 1 1 Typ Max 50 55 Unit MHz % ns ns ns cycles ns ns
TIMING DIAGRAM
N+2 N+1 N+3 N+4
N N-3 N-2 N-1
N+5 N+6
CLK
Tpd + Tod OEB Tod DATA OUT N-9 N-8 N-7 N-6 N-5 Toff N-4 N-3 Ton N-1 N
DR
HZ state
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TSA1201
CONDITIONS AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2MHz, Vin@ -1dBFS, VREFM=0V Tamb = 25C (unless otherwise specified) ANALOG INPUTS
Symbol Parameter Test conditions Min Typ 2.0 7.0 5 Vin@Full Scale, Fs=50Msps 1000 90 Max Unit Vpp pF k MHz MHz
VIN-VINB Full scale reference voltage Cin Req BW ERB Input capacitance Differential input resistance Analog Input Bandwidth Effective Resolution Bandwidth1)
1. See parameters definition for more information.
REFERENCE VOLTAGE
Symbol VREFP Parameter Top internal reference voltage Test conditions Min 0.79 Tmin= -40C to Tmax= 85C1) 0.79 1.08 Vpol Analog bias voltage Tmin= -40C to Tmax= 85C1) 1.07 0.40 VINCM Input common mode voltage Tmin= -40C to Tmax= 85C1) 0.4 0.55 1.15 Typ 1.0 Max 1.16 1.16 1.22 1.23 0.65 0.65 Unit V V V V V V
1. Not fully tested over the temperature range. Guaranteed by sampling.
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TSA1201
CONDITIONS AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2MHz, Vin@ -1dBFS, VREFP=1V, VREFM=0V Tamb = 25C (unless otherwise specified) POWER CONSUMPTION
Symbol ICCA Parameter
1)
Test conditions
Min
Typ 46
Max 51 55
Unit mA mA mA mA mA mA mA mA mA mW mW C/W
Analog Supply current Tmin= -40C to Tmax=
1)
85C2) 1.9
2.2 2.2
ICCD
Digital Supply Current
Tmin= -40C to Tmax= 85C2)
1)
0.3
0.4 0.4
ICCBI
Digital Buffer Supply Current
Tmin= -40C to Tmax= 85C2)
1)
9.8
2)
10.8 10.8
ICCB
Digital Buffer Supply Current Digital Buffer Supply Current in High Impedance Mode Power consumption in normal operation mode Junction-ambient thermal resistance (TQFP48)
1)
Tmin= -40C to Tmax= 85C ICCBZ
4 150
5 158 165
Pd
Tmin= -40C to Tmax= 85C2) 80
Rthja
1. Equivalent load: Rload= 470 and Cload= 6pF 2. Not fully tested over the temperature range. Guaranteed by sampling.
DIGITAL INPUTS AND OUTPUTS
Symbol Clock input VIL VIH Logic "0" voltage Logic "1" voltage 2.0 0 2.5 0.8 V V Parameter Test conditions Min Typ Max Unit
Digital inputs VIL VIH Logic "0" voltage Logic "1" voltage 0 0.75 x VCCBE VCCBE 0.25 x VCCBE V V
Digital Outputs VOL VOH IOZ CL Logic "0" voltage Logic "1" voltage Iol=10A Ioh=10A 0 0.9 x VCCBE VCCBE -2.5 2.5 15 0.1 x VCCBE V V A pF
High Impedance leakage current OEB set to VIH Output Load Capacitance
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TSA1201
CONDITIONS AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps, Vin@ -1dBFS, VREFP=1V, VREFM=0V Tamb = 25C (unless otherwise specified) ACCURACY
Symbol OE DNL INL Parameter Offset Error Differential Non Linearity Integral Non Linearity Monotonicity and no missing codes Test conditions
Fin= 2MHz, VIN@+1dBFS Fin= 2MHz, VIN@+1dBFS Fin= 2MHz, VIN@+1dBFS
Min
Typ 2.45 0.6 1.7
Max
Unit mV LSB LSB
Guaranteed
DYNAMIC CHARACTERISTICS
Symbol SFDR Parameter Spurious Free Dynamic Range Fin= 15MHz2) Fin= 15MHz1) SNR Signal to Noise Ratio Fin= 15MHz2) Fin= 15MHz1) THD Total Harmonics Distortion Fin= 15MHz2) SINAD Signal to Noise and Distortion Ratio Fin= 15MHz1) Fin= 15MHz2) Fin= 15MHz1) Fin= 15MHz2) 61 60 10 9.9 10.5 64.4 -64 dB dB dB bits bits 60.7 -74.3 -68 dB dB 61.6 64.9 -67 dBc dB Test conditions Fin= 15MHz1) Min Typ -77.2 Max -68 Unit dBc
ENOB
Effective Number of Bits
1. Equivalent load: Rload= 470 and Cload= 6pF 2. Tmin= -40C to Tmax= 85C. Not fully tested over the temperature range. Guaranteed by sampling.
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TSA1201
DEFINITIONS OF SPECIFIED PARAMETERS STATIC PARAMETERS Static measurements are performed through method of histograms on a 2MHz input signal, sampled at 50Msps, which is high enough to fully characterize the test frequency response. The input level is +1dBFS to saturate the signal. Differential Non Linearity (DNL) The average deviation of any output code width from the ideal code width of 1LSB. Integral Non linearity (INL) An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. DYNAMIC PARAMETERS Dynamic measurements are performed by spectral analysis, applied to an input sinewave of various frequencies and sampled at 50Msps. Spurious Free Dynamic Range (SFDR) The ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in dBc. Total Harmonic Distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Signal to Noise and Distortion Ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 x ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD= 6.02 x ENOB + 1.76 dB + 20 log (2A0/FS) The ENOB is expressed in bits. Analog Input Bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels. Effective Resolution Bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output,on the output bus. Also called data latency. It is expressed as a number of clock cycles.
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TSA1201
Static parameter: Integral Non Linearity
Fs=50MSPS; Fin=1MHz; Icca=45mA; N=131072pts
3
2
1 INL (LSBs)
0
-1
-2
-3 0 500 1000 1500 2000 O u tp u t C o d e 2500 3000 3500 4000
Static parameter: Differential Non Linearity
Fs=50MSPS; Fin=1MHz; Icca=45mA; N=131072pts
2 1 .5 1 0 .5 0 - 0 .5 -1 - 1 .5 -2 0 500 1000 1500 2000 O u tp u t C o d e 2500 3000 3500 4000
Linearity vs. Fs Fin=10MHz; Rpol adjustment
90 12 11.5 ENOB 11 10.5 SNR SINAD 10 9.5 9 8.5 8 15 25 35 45 55 ENOB (bits)
DNL (LSBs)
Distortion vs. Fs Fin=10MHz; Rpol adjustment
-40
Dynamic parameters (dB)
85 80 75 70 65 60 55 50
Dynamic parameters (dB)
-50 -60 -70 -80 -90 -100 -110 -120 15 25 35 45 55 SFDR THD
Fs (MHz)
Fs (MHz)
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TSA1201
Linearity vs. Fin Fs=50MHz; Icca=45mA
80 75 70 65 60 55 50 0 20 40 60 80
SNR
Distortion vs. Fin Fs=50MHz; Icca=45mA
12 11.5 11 10.5 10 9.5 9 SINAD 8.5 8 7.5 7
-60
Dynamic parameters (dB)
Dynamic parameters (dB)
-65 -70 -75 -80 -85 -90 0 20 40 60 80 SFDR
ENOB
THD
Fin (MHz)
Fin (MHz)
Linearity vs.Temperature Fs=49.7MSPS; Icca=45mA; Fin=15MHz
12
69 67 65 63 61 59 57 55 -40 10 60 110 ENOB SNR
Distortion vs. Temperature Fs=49.7MSPS; Icca=45mA; Fin=15MHz
90
Dynamic Parameters (dB)
Dynamic Parameters (dB)
85 THD 80 75 SFDR 70 65 60 55 50 -40 10 60 110
11.5 11
SINAD
10.5 10 9.5 Temperature (C)
Temperature (C)
Linearity vs. AVCC Fs=50MSPS; Icca=45mA; Fin=10MHz
70 12 11.8 SNR SINAD 11.6 11.4 11.2 11 10.8 ENOB 10.6 10.4 10.2 10 2.35 2.45 2.55 2.65
Distortion vs. AVCC Fs=50MSPS; Icca=45mA; Fin=10MHz
-60
Dynamic parameters (dB)
68 66 64 62 60 58 56 54 52 50 2.25
Dynamic Parameters (dB)
-65 -70 -75 -80 -85 -90 -95 -100 2.25 THD SFDR
ENOB (bits)
2.35
2.45
2.55
2.65
AVCC (V)
AVCC (V)
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TSA1201
Linearity vs. DVCC Fs=50MSPS; Icca=45mA; Fin=10MHz
66 12 11.8 11.6 11.4 11.2 SINAD 11 10.8 10.6 ENOB 10.4 10.2 10 2.35 2.45 2.55 2.65
Distortion vs. DVCC Fs=50MSPS; Icca=45mA; Fin=10MHz
-60
Dynamic parameters (dB)
65.5 65 SNR 64.5 64 63.5 63 62.5 62 2.25
Dynamic parameters (dB)
-65 -70 -75 -80 -85 -90 -95 -100 2.25 THD SFDR
ENOB (bits)
s=1
2.35
2.45
2.55
2.65
DVCC (V)
DVCC (V)
Linearity vs. VCCBE Fs=50MSPS; Icca=45mA; Fin=10MHz
70 12
Distortion vs. VCCBE Fs=50MSPS; Icca=45mA; Fin=10MHz
-50
Dynamic parameters (dB)
Dynamic Parameters (dB)
68 66 64 62 60 58 56 54 52 50 2.25
SNR
-55 -60 -65 -70 -75 -80 -85 -90 -95 -100 2.25 2.35 2.45 2.55 2.65 SFDR THD
11.5 11 10.5
SINAD
ENOB 10 9.5 9 2.35 2.45 2.55 2.65
VCCBE (V)
ENOB (bits)
VCCBE (V)
Single-tone 16K FFT at 50Msps Fin=94.5MHz; Icca=45mA, Vin@-0.5dBFS
0 -20 -40 -60 -80
Power Spectrum (dB)
-100 -120 -140 0
5
10
15
20
Frequency (MHz)
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TSA1201 APPLICATION NOTE
DETAILED INFORMATION The TSA1201 is a High Speed analog to digital converter based on a pipeline architecture and the latest deep submicron CMOS process to achieve the best performances in terms of linearity and power consumption. The pipeline structure consists of 11 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. Each 10 first stages consists of an Analog to Digital converter, a Digital to Analog converter, a Sample and Hold and a gain of 2 amplifier. A 1.5-bit conversion resolution is achieved in each stage. The latest stage simply is a comparator. Each resulting LSB-MSB couple is then time shifted to recover from the delay caused by conversion. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB) couple for each stage. The OPERATIONAL MODES DESCRIPTION Inputs Analog input differential level (VIN-VINB) > RANGE -RANGE > (VIN-VINB) RANGE> (VIN-VINB) >-RANGE (VIN-VINB) > RANGE -RANGE > (VIN-VINB) RANGE> (VIN-VINB) >-RANGE X X X Data Format Select (DFSB) When set to low level (VIL), the digital input DFSB provides a two's complement digital output MSB. This can be of interest when performing some further signal processing. When set to high level (VIH), DFSB provides a standard binary output coding. DFSB OEB H H H L L L X X X L L L L L L H X X SRC X X X X X X X H L OR H H L H H L HZ X X DR CLK CLK CLK CLK CLK CLK HZ CLK CLK Outputs Most Significant Bit (MSB) D11 D11 D11 D11 Complemented D11 Complemented D11 Complemented HZ 25Msps compliant slew rate 50Msps compliant slew rate corrected data are outputted through the digital buffers. Signal input is sampled on the rising edge of the clock while digital outputs are delivered on the falling edge of the clock. The advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. The highest dynamic performances are achieved while consumption remains at the lowest level. Some functionalities have been added in order to simplify as much as possible the application board. These operational modes are described in the following table. The TSA1201 is pin to pin compatible with the 8bits/40Msps TSA0801, the 10bits/25Msps TSA1001 and the 10bits/50Msps TSA1002. This ensures a conformity within the product family and above all, an easy upgrade of the application
Output Enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state while the converter goes on sampling. When OEB is set to a low level again, the data are then present on the output with a very short Ton delay. Therefore, this allows the chip select of the device. The timing diagram summarizes this functionality.
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TSA1201
Slew Rate Control (SRC) When set to high level (VIH), all digital outputs currents are limited to a clamp value so that digital noise power is reduced to its minimum. Rise and fall times just match 25MHz sampling rate assuming the load capacitance on each digital output remains below 10pF. When set to low level (VIL), the maximum digital output current increases so that rise and fall times just match the 50MHz sampling rate assuming the load capacitance on each digital output remains below 10pF. Out of Range (OR) This function is implemented on the output stage in order to set up an "Out of Range" flag whenever the digital data is over the full scale range. Typically, there is a detection of all the data being at '0' or all the data being at '1'. This ends up with an output signal OR which is in low level state (VOL) when the data stay within the range, or in high level state (VOH) when the data are out of the range. Data Ready (DR) The Data Ready output is an image of the clock being synchronized on the output data (D0 to D11). This is a very helpful signal that simplifies the synchronization of the measurement equipment or the controlling DSP. As digital output, DR goes into high impedance state when OEB is asserted to high level as described in the timing diagram. REFERENCES AND COMMON MODE CONNECTION It is advised to always connect VREFM externally. Internal reference and common mode In the default configuration, the ADC operates with its own reference and common mode voltages generated by its internal bandgap. VREFM pin is connected externally to the Analog Ground while VREFP (respectively INCM) is set to its internal voltage of 1.03V (respectively 0.57V). It is recommended to decouple the VREFP in order to
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minimize low and high frequency noise (refer to Figure 1) Figure 1 : Internal reference and common mode setting
1.03V
330pF 10nF 4.7uF
VIN
VREFP 0.57V
330pF 10nF 4.7uF
TSA1201
VINB INCM VREFM
External reference and common mode Each of the voltages VREFM, VREFP and INCM can be fixed externally to better fit to the application needs (Refer to table 'OPERATING CONDITIONS' page 2 for min/max values). The VREFP, VREFM voltages set the analog dynamic at the input of the converter that has a full scale amplitude of 2*(VREFP-VREFM). In case of analog dynamic lower than 2Vpp, the best linearity and distortion performance is achieved while increasing the VREFM voltage instead of lowering the VREFP one. The INCM is the mid voltage of the analog input signal. It is possible to use an external reference voltage device for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. Using the STMicroelectronics TS821 or TS4041-1.2 Vref leads to optimum performances when configured as shown on Figure 2. Figure 2 : External reference setting
1k
330pF 10nF 4.7uF
VCCA VREFP VIN
TSA1201
VINB VREFM
TS821 TS4041 external reference
This can be very helpful for example for multichannel application to keep a good matching among the sampling frequency range.
TSA1201
DRIVING THE ANALOG INPUT Differential inputs The TSA1201 has been designed to obtain optimum performances when being differentially driven. An RF transformer is a good way to achieve such performances. Figure 3 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. Figure 3 : Differential input configuration with transformer
Analog source ADT1-1 1:1 VIN
50 100pF
Figure 4 represents the biasing of a differential input signal in AC-coupled differential input configuration. Both inputs VIN and VINB are centered around the common mode voltage, that can be let internal or fixed externally. Figure 5 shows a DC-coupled configuration with forced INCM to the DC analog input (mid-voltage) while VREFM is connected to ground and VREFP is let internal (1V); we achieve a 2Vpp differential amplitude. Figure 5 : DC-coupled 2Vpp differential analog input
analog DC analog AC+DC VIN
TSA1201
VINB INCM
VREFP
TSA1201
VINB
VREFM
INCM DC
330pF 10nF
4.7uF
330pF
10nF
4.7uF
VREFP-VREFM = 1 V
The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.57V. The INCM is decoupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from Minicircuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. For example, with internal references, each analog input can drive a 1Vpp amplitude input signal, so the resultant differential amplitude is 2Vpp. Figure 4 : AC-coupled differential input
Single-ended input configuration The single-ended input configuration of the TSA1201 requires particular biasing and driving. The structure being fully differential, care has to be taken in order to properly bias the inputs in single-ended mode. Figure 6 summarizes the link from the differential configuration to the single-ended one; a wrong configuration is also presented. - With differential driving, both inputs are centered around the INCM voltage. - The transition to single-ended configuration implies to connect the unused input (VINB for instance) to the DC component of the single input (VIN) and also to the input common mode in order to be well balanced. The mid-code is achieved at the crossing between VIN and VINB, therefore inputs are conveniently biased. - Unlikely other structures of converters in which the unused channel can be grounded; in our case it will end with unbalanced inputs and saturation of the internal amplifiers leading to a non respect of the output codes.
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50 common mode
10nF 100k 33pF 100k 10nF
VIN INCM
TSA1201
VINB
50
TSA1201
Figure 6 : Input dynamic range for the various configurations
Differential configuration +FS: code 1023 VIN - VINB +FS: code 1023 VIN - VINB VINB VIN INCM VIN 0: code 511 0: code 511 INCM VIN Single-ended configuration: balanced inputs Single-ended configuration: unbalanced inputs +FS + offset: code > 1023 VIN - VINB
INCM
-FS: code 0 -FS: code 0 Ao + ac VIN VINB Ao + ac VIN VINB Ao
-FS + offset: code > 0
Ao + ac
VIN VINB
Ao + ac
INCM Ao
INCM
INCM
Ao Wrong configuration!
The applications requiring single-ended inputs can be configured like reported on Figure 7 for an AC-coupled input or on Figure 8 and 9 for a DC-coupled input. In the case of AC-coupled analog input, the analog inputs VIN and VINB are biased to the same voltage that is the common mode voltage of the circuit (INCM). The INCM and reference voltages may remain at their internal level but can also be fixed externally. Figure 7 : AC-coupled Single-ended input
let internal; we achieve a 2Vpp differential amplitude. Figure 8 : DC-coupled 2Vpp analog input
Analog DC
AC+DC VIN
VREFP
TSA1201
VINB
VREFM
INCM
330pF
10nF
4.7uF
Signal source
10nF 50 common mode 33pF 100k
VREFP-VREFM = 1 V
VIN INCM
100k
TSA1201
VINB
Figure 9 describes a configuration for a 1Vpp analog signal with a 0.5V DC input. In this case, while VREFP is kept internal at 1V, VREFM is connected to VINB and INCM, externally to 0.5V; the dynamic is then 1Vpp (VREFP-VREFM=0.5V).
In the case of DC-coupled analog input with 1V DC signal, the DC component of the analog input set the common mode voltage. As an example figure 8, INCM is set to the 1V DC analog input while VREFM is connected to ground and VREFP
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TSA1201
Figure 9 : DC-coupled 1Vpp analog input
Analog DC AC+DC VIN
TSA1201
VINB VREFM INCM
The clock power supplies must be separated from the ADC output ones to avoid digital noise modulation at the output. It is recommended to always keep the circuit clocked, to avoid random states, before applying the supply voltages. Power consumption optimization The internal architecture of the TSA1201 enables to optimize the power consumption according to the sampling frequency of the application. For this purpose, a resistor is placed between IPOL and the analog Ground pins. The TSA1201 will combine highest performances and lowest consumption at 50Msps when Rpol is equal to 12k. At lower sampling frequency, this value of resistor may be changed and the consumption will decrease as well. The figure 10 sums up the relevant data. Figure 10 : Analog Current consumption vs. Fs According value of Rpol polarization resistance
200 180 160 Rpol(kOhms) 140 120 100 80 60 40 20 0 5 25 45 Fs(MHz) 65 85
RPOL ICCA
0.5V power supply
330pF
10nF
4.7uF
VREFP-VREFM = 0.5 V
Dynamic characteristics, while not being as remarkable as for differential configuration, are still of very good quality. Measurements done at 50Msps, 2MHz input frequency, -1dBFS input level sum up these performances. A SNR of 63.5dB and an ENOB full Scale of 10.2 bits are achieved. IF-sampling Software radio has become a common mode for receiving data through RF receivers. Its main advantage being to digitally implement what was originally done with analog functions such as discriminators, demodulation and filtering. Originally, bipolar process was mainly used because they provided high transistor transit frequency, while pure CMOS technology showed a lower one. With new CMOS process and circuit topology, higher frequencies are now achieved. The TSA1201 has been specifically designed to meet the requirement of sampling at Intermediate Frequency. For this purpose, the Track-and-Hold of the first pipeline stage has been built to ensure the global linearity of the overall ADC to perform the right characteristics. Our proprietary Track-and-Hold has a patented switch control system to enable the performances not to be degraded as input signal frequency increases. As a result, an analog bandwidth of 1GHz is achieved. Clock input The converter quality is very dependant on clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator is recommended. The duty cycle must be between 45% and 55%.
70 60 50 40 30 20 10 0 Icca(mA)
Layout precautions To use the ADC circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: - First of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is recommended for high speed circuit applications to provide low inductance and low resistance common return. The separation of the analog signal from the digital part is essential to prevent noise from coupling onto the input signal. - Power supply bypass capacitors must be placed as close as possible to the IC pins in order to
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TSA1201
improve high frequency bypassing and reduce harmonic distortion. - Proper termination of all inputs and outputs is needed; with output termination resistors, the amplifier load will be only resistive and the stability of the amplifier will be improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. - To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output capacitance, buffers or latches close to the output pins will relax this constraint. - Choose component sizes as small as possible (SMD). EVAL1201 evaluation board The characterization of the board has been made with a fully ADC devoted test bench as shown on Figure 11. The analog signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers 74LCX573. All characterization measurements have been made with: - SFSR=+0.5dB for static parameters. - SFSR=-0.5dB for dynamic parameters.
Figure 11 : Analog to Digital Converter characterization bench
Power
HP8644B Sine wave Generator
Vin
ADC evaluation board
ck
data
Logic Analyzer
dataready
TLA704 HP8133A Pulse Generator
HP8644B
Sine Wave Generator
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J9 DFSB J11 1 2 1 2 1 2 VCCB2 C34
+
J10 OEB J13 1 2
J17 VDDBUFF3V
R10 47K R11 47K R12 47K R13 47K C16 AVCC 470nF C15 470nF C27 470nF C39 C28 VCCB1 47 C37
J2 Raj1 47K 10nF C14 R2 1K 330pF 330pF R14 R15 R16 R17 R18 R19 47K 47K 47K 47K 47K 47K 330pF 10nF C25 10nF C26
1 2
VrefP
1 2
J6 DR DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
J5
1 2
VrefM C32 470nF AGND AVCC AVCC DFSB OEB NC NC 2.5VCCBUFF GNDBUFF 2.5VCCBUFF DR D0 C1 100pF 10nF C30 330pF 470nF 10nF 330pF C31 C13 C12 C11 48 47 46 45 44 43 42 41 40 39 38 37
J1 Vin
1
T2
6
Figure 12 : TSA1201 Evaluation board schematic
R1 50 3
2
4 T2-AT1-1WT C9 330pF C5 C3 330pF AVCC 470nF 10nF 330pF C4 C2 8-14bits ADC TSA1002 TSA1201 74LCX573 C8
1 2 3 4 5 6 7 8 9 10 OEB VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 U2 D5 Q5 D6 Q6 D7 Q7 GND LE
20 19 18 17 16 15 14 13 12 11
J7
C10
1 2 C6
470nF 10nF
Regl com mode J8
C7
1 2 13 14 15 16 17 18 19 20 21 22 23 24
Mes com Mode J12
DVCC DVCC DGND CLK DGND NC DGND GNDBUFF GNDBUFF 2.5VCCBUFF OR D13
470nF 10nF
1 2 3 4 5 6 7 8 9 10 11 12 Ipol VrefP VrefM AGND Vin AGND VINB AGND INCM AGND AVCC AVCC 1 2 3 4 5 6 7 8 9 10 74LCX573 C38 C29 6 2 4
+
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 OEB VCC D0 Q0 D1 Q1 U3 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 20 19 18 17 16 15 14 13 12 11
36 35 34 33 32 31 30 29 28 27 26 25
2 1 C41 10F
AVCC
+
C42 47F
D13 OR
J19 C20 10F C17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 470nF C40 32PIN
1 2
AGND
J20 1 330pF C21 3 R3 50 10nF C22 470nF C23 10
+
1 2
T1 T2-AT1-1WT 330pF C18 10nF C19 470nF C24 10
+
10nF C33 330pF
DGND
J21
1 2
GndB2 C36 47 2 2 1 1 J4 CLJ/SMB C35 47 VCCB1
J22
1 2 2 1
J15 DVCC
J16 CON2
J18 VccB1
2 1
GndB1
TSA1201
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TSA1201
Figure 13 : Printed circuit of evaluation board.
Printed circuit board - List of components
P a rt T yp e 10 uF 10 uF 10 uF 10 uF 10 0 p F 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 1K 3 2 P IN 3 3 0 pF 3 3 0 pF D e s ig n F o o t p rin t a to r C24 C23 C41 C29 C1 C 12 C39 C 15 C40 C27 C4 C21 C31 C6 C9 C 18 R2 J6 C25 C26 12 10 12 10 12 10 12 10 603 603 603 603 603 603 603 603 603 603 603 603 603 ID C 3 2 603 603 P a rt Typ e 33 0 pF 33 0 pF 33 0 pF 33 0 pF 33 0 pF 33 0 pF 33 0 pF 33 0 pF 33 0 pF 47 uF 47 uF 47 uF 47 uF 47 0 nF 47 0 nF 47 0 nF 47 0 nF 47 0 nF 47 0 nF 47 0 nF D e s ig n F o o t prin t a to r C33 C20 C8 C2 C5 C 11 C30 C 17 C 14 C36 C34 C35 C42 C22 C32 C37 C38 C 13 C28 C 10 603 603 603 603 603 603 603 603 603 CAP CAP CAP CAP 805 805 805 805 805 805 805 P a rt Typ e 4 70 nF 4 70 nF 4 70 nF 4 70 nF 4 7K 4 7K 4 7K 4 7K 4 7K 4 7K 4 7K 4 7K 4 7K 4 7K 4 7K 50 50 D e s ig n F o o t p rint ato r C7 C 16 C 19 C3 R 12 R 14 R 11 R a j1 R 10 R 19 R 13 R 15 R 16 R 17 R 18 R3 R1 805 805 805 805 603 603 603 VR 5 603 603 603 603 603 603 603 603 603 T S S OP 2 0 T S S OP 2 0 S IP 2 P a rt T yp e A VC C C LJ / S M B A GN D D FS B D GN D D VC C G n dB 1 G n dB 2 D e s ig n ato r J 12 J4 J 19 J9 J20 J 15 J22 J21 F IC H E2 M M SMB /H F IC H E2 M M F IC H E2 M M F IC H E2 M M F IC H E2 M M F IC H E2 M M F IC H E2 M M F IC H E2 M M F IC H E2 M M F IC H E2 M M ADT ADT F IC H E2 M M F IC H E2 M M SMB /H F IC H E2 M M F IC H E2 M M TQ F P 4 8 F o o t p rin t
M e s c o m m o de J 8 O EB J 10
R e gl c o m m o de J7 T 2 - A T 1- 1WT T 2 - A T 1- 1WT Vc c B 1 VD D B UF F 3 V Vin Vre f M Vre f P T S A 10 0 2 TSA1201 T2 T1 J 18 J 17 J1 J5 J2 U1
7 4 LC X5 7 3 U3 7 4 LC X5 7 3 U2 CON2 J 16
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TSA1201
PACKAGE MECHANICAL DATA 48 PINS - PLASTIC PACKAGE
A A2 48 1 e A1 37 36 0,10 mm .004 inch SEATING PLANE
12 13 24
25
E3 E1 E
D3 D1 D
L1
L
K
Millimeters Dim. Min. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.05 1.35 0.17 0.09 Typ. Max. 1.60 0.15 1.45 0.27 0.20
0,25 mm .010 inch GAGE PLANE
B
c
Inches Min. 0.002 0.053 0.007 0.004 Typ. Max. 0.063 0.006 0.057 0.011 0.008 1.40 0.22 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039 0.45 0.75 0.018
0.030
0 (min.), 7 (max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States (c) http://www.st.com
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