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CY7C123
256 x 4 Static RAM
Features
* 256 x 4 static RAM for control store in high-speed computers * CMOS for optimum speed/power * High speed -- 7 ns (commercial) -- 10 ns (military) * Low power -- 660 mW (commercial) -- 825 mW (military) * Separate inputs and outputs * 5-volt power supply 10% tolerance both commercial and military * TTL-compatible inputs and outputs * 24 pins * 300-mil package
Functional Description
The CY7C123 is a high-performance CMOS static RAM organized as 256 words by 4 bits. Easy memory expansion is provided by an active LOW chip select one (CS1) input, an active HIGH chip select two (CS2) input, and three-state outputs. Writing to the device is accomplished when the chip select one (CS1) and write enable (WE) inputs are both LOW and the chip select two input is HIGH. Data on the four data inputs (D 0 through D3) is written into the memory location specified on the address pins (A0 through A 7). The outputs are preconditioned so that the write data is present at the outputs when the write cycle is complete. This precondition operation ensures minimum write recovery times by eliminating the "write recovery glitch." Reading the device is accomplished by taking the chip select one (CS1) and output enable (OE) inputs LOW, while the write enable (WE) and chip select two (CS 2) inputs remain HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the four output pins (O0 through O 3). The output pins remain in high-impedance state when chip select one (CS1) or output enable (OE) is HIGH, or write enable (WE) or chip select two (CS2) is LOW. A die coat is used to insure alpha immunity.
Logic Block Diagram
D0 D1 D2 D3 CS2 CS1 DATA INPUT CONTROL WE OE ROW DECODER SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 O0 O1 O2 O3
Pin Configuration
DIP/SOJ Top View
A2 A3 A4 A5 A6 A7 VSS D0 D1 O0 O1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A1 A0 WE CS1 OE VCC CS2 D3 D2 O3 O2 C123-2
16 x 64 ARRAY
COLUMN DECODER
C123-1
Selection Guide
Commercial Military Maximum Operating Current (mA) Commercial Military Maximum Access Time (ns) 7C123-7 7 120 7C123-9 9 120 150 7C123-10 10 7C123-12 12 12 120 150 7C123-15 15 150
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose * CA 95134 * 408-943-2600 January 1989 - Revised December 1992
CY7C123
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................-65C to+150C Ambient Temperature with Power Applied ..............................................-55C to+125C Supply Voltage to Ground Potential (Pins 24 and 18 to Pins 7 and 12)[1] ............... -0.5V to+7.0V DC Voltage Applied to Outputs in High Z State[1] ............................................. -0.5V to+7.0V DC Input Voltage[1] .........................................-0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Latch-Up Current.................................................... >200 mA
Operating Range
Range Commercial Military[2] Ambient Temperature 0C to + 70C -55C to + 125C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range[3]
7C123-7 7C123-9 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Current (High Z) Power Supply Current
[1]
7C123-10 7C123-15 Min. 2.4 Max. 0.4 2.2 -0.8 -10 -10 VCC +0.8 +10 +10
7C123-12 Min. 2.4 0.4 2.2 -0.8 -10 -10 VCC +0.8 +10 +10 120 Max. Unit V V V V A A mA mA
Test Conditions VCC = Min., IOH = -5.2 mA VCC = Min., IOL = 8.0 mA
Min. 2.4
Max. 0.4
2.2 -0.8 VSS < V I < V CC VSS < VOUT < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Commercial Military -10 -10
VCC +0.8 +10 +10 120
Input Load Current
150
150
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF
Logic Table[5]
Input OE X X L X X H CS1 H X L L L L CS2 X L H H H H WE X X H L L H D0 - D 3 X X X L H X High Z High Z O0 - O3 High Z High Z High Z Outputs Mode Not Selected Not Selected Read Stored Data Write "0" Write "1" Output Disabled
Notes: 1. VIL(min.) = -3.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. Tested initially and after any design or process changes that may affect these parameters. 5. H = High Voltage, L = Low Voltage, X = Don't Care, and High Z = High Impedance.
2
CY7C123
AC Test Loads and Waveforms
R1 470 5V OUTPUT 20 pF INCLUDING JIG AND SCOPE Equivalent to: R2 224 (a) 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 224 (b) R1 470 ALL INPUT PULSES 3.0V 10% GND 3 ns
C123- 3
90%
90% 10% 3ns
C123- 4
THEVENIN EQUIVALENT OUTPUT 152 1.62V
Switching Characteristics Over the Operating Range[3]
7C123-7 Parameter READ CYCLE tRC tAA tACS tDOE tHZCS tHZOE tLZCS tLZOE tWC tHZWE tLZWE tPWE tSD tHD tSA tHA tSCS tAW Read Cycle Time Address to Data Valid Chip Select to Data Valid OE LOW to Data Valid Chip Select to High Z[6,7] OE HIGH to High Z[6] Chip Select to Low Z OE LOW to Low Z Write Cycle Time WE LOW to High Z WE HIGH to Low Z WE Pulse Width Data Set-Up to Write End Data Hold from Write End Address Set-Up to Write Start Address Hold from Write End CS LOW to Write End Address Set-Up to Write End
[6] [7]
7C123-9 Min. 9 Max.
7C123-10 Min. 10 Max.
7C123-12 Min. 12 Max.
7C123-15 Min. 15 Max. Unit ns 15 10 10 8 8 2 2 15 ns ns ns ns ns ns ns ns 8 2 11 11 1 2 2 11 13 ns ns ns ns ns ns ns ns ns
Description
Min. 7
Max.
7 7 7 5 5 2 2 7 5.5 2 5 5 1 0.5 1.5 5 5.5 2 6.5 6 1 1 1.5 6.5 7.5 2 2 9
9 8 8 6 6 2 2 10 6 2 7 7 1 1 2 7 8
10 8 8 6 6 2 2 12 6 2 8 8 1 2 2 8 10
12 8 8 6.5 6.5
WRITE CYCLE 7
Notes: 6. Transition is measured at steady-state HIGH level - 500 mV or steady-state LOW level +500 mV on the output from 1.5V level on the input with load shown in part (b) of AC Test Loads. 7. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device.
3
CY7C123
Switching Waveforms
Read Cycle [8,9]
tRC ADDRESS tAA CS1 - CS2 tACS tLZCS OE tDOE tLZOE DATA OUT DATA VALID
C123-5
tHZCS
tHZOE
Write Cycle [8,9]
tWC ADDRESS tAW CS1 - CS2 tSA WE tPWE tHA
tSCS
tSD DATA IN tHZWE DATA OUT
tHD
tLZWE
C123-6
Notes: 8. Measurements are referenced to 1.5V unless otherwise stated. 9. Timing diagram represents one solution that results in an optimum cycle time. Timing may be changed in various applications as long as the worst case limits are not violated.
4
CY7C123
Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC, ISB NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 ISB 5.5 6.0 ICC 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -55 ISB 25 VCC =5.0V VIN =5.0V ICC NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 90 75 60 45 30 15 0 0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) VCC =5.0V TA =25C
125
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
OUTPUT SINK CURRENT (mA)
NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED t AA NORMALIZED t AA 1.3 1.2 1.1 TA =25C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0
NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 360 300 240 180 120 60
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
VCC =5.0V 0.8 0.6 -55
VCC =5.0V TA =25C 1.0 2.0 3.0 4.0 5.0
25
125
0 0.0
SUPPLY VOLTAGE(V)
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V)
TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED I PO 2.5 (ns) 2.0 1.5 1.0 0.5 0.0 0.0 0 1.0 2.0 3.0 4.0 5.0 20 30
TOTAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.1 NORMALIZED I PO VCC =4.5V TA =25C
NORMALIZED I CC vs. CYCLE TIME VCC =5.0V TA =25C VIN =0.5V 1.0
DELTA t
AA
10
0.9
0
200
400
600
800
1000
0.8 10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
5
CY7C123
Ordering Information
Speed (ns) 7 9 10 12 15 Ordering Code CY7C123-7PC CY7C123-7VC CY7C123-9PC CY7C123-9VC CY7C123-10DMB CY7C123-12PC CY7C123-12DMB CY7C123-15DMB Package Name P13A V13 P13A V13 D14 P13A D14 D14 Package Type 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) CerDIP 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) CerDIP 24-Lead (300-Mil) CerDIP Operating Range Commercial Commercial Military Commercial Military Military
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL Max. IIX IOZ ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Switching Characteristics
Parameter READ CYCLE tRC tAA tACS tDOE WRITE CYCLE tWC tPWE tSD tHD tSA tHA tSCS tAW 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Subgroups
Document #: 38-00060-F
6
CY7C123
7
CY7C123
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9 Config.A
24-Lead (300-Mil) Molded DIP P13/P13A
(c) Cypress Semiconductor Corporation, 1993. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C123
Package Diagrams (continued)
24-Lead Molded SOJ V13
9

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