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1CY 7C26 9
CY7C269
8K x 8 Registered Diagnostic PROM
Features
* CMOS for optimum speed/power * High speed (commercial and military) -- 15-ns address set-up -- 12-ns clock to output * Low power -- 660 mW (commercial) -- 770 mW (military) * On-chip edge-triggered registers -- Ideal for pipelined microprogrammed systems * On-chip diagnostic shift register -- For serial observability and controllability of the output register * EPROM technology -- 100% programmable -- Reprogrammable (7C269W) * 5V 10% VCC, commercial and military * Capable of withstanding >2001V static discharge * Slim 300-mil, 28-pin plastic or hermetic DIP
Functional Description
The CY7C269 is a 8K x 8 registered diagnostic PROM. It is organized as 8,192 words by 8 bits wide, and has both a pipeline output register and an onboard diagnostic shift register. The device features a programmable initialize byte that may be loaded into the pipeline register with the initialize signal. The programmable initialize byte is the 8,193rd byte in the PROM, and may be programmed to any desired value.
Logic Block Diagram
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Pin Configurations
CerDIP/Flatpack Top View
ADDRESS DECODER
ROW DECODER
COLUMN MULTIPLEXER
MODE
DIAGNOSTIC MUX
A7 A6 A5 A4 A3 A2 MODE CLOCK A1 A0 O0 O1 O2 GND S/L 8-BIT EDGETRIGGERED SHIFT REGISTER CP SDI SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC A8 A9 A10 A11 A12 E/ES, I SDI SDO O7 O6 O5 O4 O3
E/I
CONTROL LOGIC
PROGRAMMABLE INITIALIZE WORD 8-BIT EDGE-TRIGGERED PIPELINE REGISTER
C269-2
LCC/PLCC (Opaque Only) Top View
4 3 2 1 28 27 26 25 5 24 6 23 7 22 8 21 9 20 10 19 11 12 1314151617 18
CLOCK
A3 A2 MODE CLOCK A1 A0 O0
A10 A11 A12 E/ES,I SDI SDO O7
O7 O6 O5 O4 O3 O2 O1 O0
C269-1
C269-3
Selection Guide
Minimum Address Set-Up Time (ns) Maximum Clock to Output (ns) Maximum Operating Current Commercial (mA) Military 7C269-15 15 12 120 140 7C269-25 25 15 120 140 7C269-40 40 20 100 7C269-50 50 25 80 120
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
* CA 95134 * 408-943-2600 December 1987 - Revised May 1993
CY7C269
Functional Description (continued)
The CY7C269 is optimized for applications that require diagnostics in a minimum amount of board area. Packaged in 28 pins, it has 13 address signals (A0 through A12), 8 data out signals (O0 through O7), E/I (Enable or Initialize), and CLOCK (pipeline and diagnostic clock). Additional diagnostic signals consist of MODE, SDI (shift in), and SDO (shift out). Normal pipelined operation and diagnostic operation are mutually exclusive. When the MODE signal is LOW, the 7C269 operates in a normal pipelined mode. CLOCK functions as a pipeline clock, loading the contents of the addressed memory location into the pipeline register on each rising edge. The data will appear on the outputs if they are enabled. One pin on the 7C269 is programmed to perform either the Enable or the Initialize function. If the E/I pin is used for a INIT (asynchronous initialize) function, the outputs are permanently enabled and the initialize word is loaded into the pipeline register on a HIGH to LOW transition of the INIT signal. The INIT LOW disables CLOCK and must return high to re-enable CLOCK. If the E/I pin is used for an enable signal, it may be programmed for either synchronous or asynchronous operation. When the MODE signal is HIGH, the 7C269 operates in the diagnostic mode. The E/I signal becomes a secondary mode signal designating whether to shift the diagnostic shift register or to load either the diagnostic register or the pipeline register. If E/I is HIGH, it shifts SDI into the least-significant location of the diagnostic register and all bits one location toward the most-significant location on each rising edge. The contents of the most-significant location in the diagnostic register are available on the SDO pin. If the E/I signal is LOW, SDI becomes a direction signal, transferring the contents of the diagnostic register into the pipeline register when SDI is LOW. When SDI is HIGH, the contents of the output pins are transferred into the diagnostic register. Both transfers occur on a LOW to HIGH transition of the CLOCK. If the outputs are enabled, the contents of the pipeline register are transferred into the diagnostic register. If the outputs are disabled, an external source of data may be loaded into the diagnostic register. In this condition, the SDO signal is internally driven to be the same as the SDI signal, thus propagating the "direction of transfer information" to the next device in the string.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied.............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -3.0V to +7.0V DC Program Voltage .....................................................13.0V UV Exposure.................................................7258 Wsec/cm2 Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial[1] Military[2] Ambient Temperature 0C to +70C -40C to +85C -55C to +125C VCC 5V 10% 5V 10% 5V 10%
Notes: 1. Contact a Cypress representative for industrial temperature range specifications. 2. TA is the "instant on" case temperature.
2
CY7C269
Electrical Characteristics Over the Operating Range[3, 4]
7C269-15, 25 Parameter VOH VOH VOL Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Test Conditions VCC = Min., IOH = -2.0 mA VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA VCC = Min., IOL = 6.0 mA VCC = Min., IOL = 12.0 mA VCC = Min., IOL = 8.0 mA VIH VIL IIX IOZ IOS[5] ICC VPP IPP VIHP VILP Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current VCC Operating Supply Current Programming Supply Voltage Programming Supply Current Input HIGH Programming Voltage Input LOW Programming Voltage 3.0 0.4 VCC = Max., IOUT = 0 mA Com'l Mil 12 GND < VIN < VCC GND < VOUT < VCC, Output Disabled -10 -40 Com'l Mil Com'l Mil 2.0 0.8 +10 +40 90 120 140 13 50 3.0 0.4 12 13 50 3.0 0.4 12 -10 -40 2.0 0.8 +10 +40 90 100 -10 -40 0.4 0.4 0.4 0.4 2.0 0.8 +10 +40 90 80 120 13 50 V mA V V 0.4 0.4 V V A A mA mA V Min. 2.4 2.4 2.4 Max. 7C269-40 Min. Max. 7C269-50 Min. Max. Unit V V V
Capacitance[4, 6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF
Notes: 3. See the last page of this specification for Group A subgroup testing information. 4. See Introduction to CMOS PROMs in this Data Book for general information on testing. 5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 6. Tested initially and after any design or process changes that may affect these parameters.
3
CY7C269
AC Test Loads and Waveforms
Test Load for -15 through -25 speeds
R1 500 (658 MIL) 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE 5V OUTPUT R2 333 (403 MIL) 5 pF INCLUDING JIG AND SCOPE R2 333 (403 MIL) R1 500 (658 MIL) 3.0V GND < 5 ns 90% 10% 90% 10% < 5 ns
C269-4
C269-5
(a) Normal Load
Equivalent to: OUTPUT THEVENIN EQUIVALENT RTH 200 250 MIL
(b) High Z Load
Test Load for - 40 through - 50 speeds
R1 250 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE 5V OUTPUT R2 167 5 pF INCLUDING JIG AND SCOPE R2 167 R1 250
C269-6
(c) Normal Load
Equivalent to: THEVENIN EQUIVALENT RTH 100 OUTPUT 2.0V
(d) High Z Load
Switching Characteristics Over the Operating Range[3, 4]
7C269-15 Parameter tAS tAH tCO tPWC tSES tHES tDI tRI tPWI tCOS tHZC tDOE tHZE Description Address Set-Up to Clock Address Hold from Clock Clock to Output Valid Clock Pulse Width ES Set-Up to Clock (Sync Enable Only) ES Hold from Clock INIT to Out Valid INIT Recovery to Clock INIT Pulse Width Output Valid from Clock (Sync. Mode) Output Inactive from Clock (Sync. Mode) Output Valid from E LOW (Async. Mode) Output Inactive from E HIGH (Async. Mode) 12 12 12 12 12 12 12 12 5 15 15 15 15 15 15 15 Min. 15 0 12 15 15 5 18 20 25 20 20 20 20 Max. 7C269-25 Min. 25 0 15 15 15 5 25 25 35 25 25 25 25 Max. 7C269-40 Min. 40 0 20 20 15 5 35 Max. 7C269-50 Min. 50 0 25 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
4
CY7C269
Diagnostic Mode Switching Characteristics Over the Operating Range[3, 4]
7C269-15 Parameter tSSDI tHSDI tDSDO tDCL tDCH tSM tHM tMS tSS tSO tHO Description Set-Up SDI to Clock SDI Hold from Clock SDO Delay from Clock Minimum Clock LOW Minimum Clock HIGH Set-Up to Mode Change Hold from Mode Change Mode to SDO SDI to SDO Data Set-Up to DCLK Data Hold from DCLK Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil 20 25 10 13 20 25 20 25 20 25 0 0 20 25 30 35 25 30 10 13 Min. 20 25 0 0 20 25 25 25 25 25 25 30 0 0 25 30 40 40 25 30 10 15 ns Max. 7C269-25 Min. 25 30 0 0 25 30 25 25 25 25 25 30 0 0 25 30 40 45 ns ns ns ns ns ns Max. 7C269-40,50 Min. 30 35 0 0 30 40 ns ns ns Max. Unit ns
Switching Waveforms[3,4]
Pipeline Operation (Mode = 0)
ADDDRESS tAS SYNCHRONOUS ENABLE PROGRAMMABLE tSES PCLK/CLOCK tRI OUTPUT tDI tPWI ASYNCHRONOUS INIT tPWC tCOS tCO tHES tAH
VALID DATA tHZC tHZE tDOE
ASYNCHRONOUS ENABLE
C269-7
5
CY7C269
Switching Waveforms[3,4] (continued)
Diagnostic Application (Shifting the Shadow Register[7])
CLOCK tSM MODE tDSDO SDO tMS SDI tSM E/I
C269-8
tDCL
tDCH
tSM
tHM
tSSDI
tHSDI
Diagnostic Application (Parallel Data Transfer)
tSM CLOCK tSM [8] MODE tMS SDI tMS SDO tSM E/I tCO O0 - O7 DATA OUT tSO tHO tMS[9] tSS tSS tDCL tSSDI tHSDI tSM tHM
DATA IN
C269-9
Notes: 7. Diagnostic register = shadow register = shift register. 8. Asynchronous enable mode only. 9. The mode transition to HIGH latches the asynchronous enable state. If the enable state is changed and held before leaving the diagnostic mode (mode H L) then the output impedance change delay is tMS.
Bit Map Data
Programmer Address (Hex.) Decimal Hex 0 0 . . . . 8191 1FFF 8192 2000 8193 2001 RAM Data Contents Data . . Data Init Byte Control Byte
Control Byte 00 01 02 Asynchronous output enable (default condition) Synchronous output enable Asynchronous initialize
6
CY7C269
Programming Modes
Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative.
CerDIP/Flatpack
A7 A6 A5 /VPP A4 A3 A2 PGM NA A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A8 A9 /VPP A10 A11 A12 VPP NA VFY D7 D6 D5 D4 D3 C269-10
LCC/PLCC (Opaque Only)
A3 A2 PGM NA A1 A0 D0
4 3 2 1 28 27 26 25 5 24 6 23 7 22 8 21 9 20 10 19 11 12 1314151617 18
A10 A11 A12 VPP NA VFY D7
C269-11
Figure 1. Programming Pinouts
Mode Selection
Pin Function[10] Read or Output Disable Mode Read Load SR to PR Load Output to SR Shift SR Asynchronous Enable Read Synchronous Enable Read Asynchronous Initialization Read Program Memory Program Verify Program Inhibit Program Synchronous Enable Program Initialize Program Initial Byte Other A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 A12 VIHP VILP A12 A11 A11 A11 A11 A11 A11 A11 A11 A11 A11 A11 A11 VIHP VIHP VILP A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A10 - A7 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 VIHP VIHP VIHP A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 VPP VPP VPP A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A4 - A3 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 VIHP VILP VILP A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1
Pin Function[10] Read or Output Disable Mode Read Load SR to PR Load Output to SR Shift SR Asynchronous Enable Read Synchronous Enable Read Asynchronous Initialization Read Program Memory Program Verify Program Inhibit Program Synchronous Enable Program Initialize Program Initial Byte
Note: 10. X = "don't care" but not to exceed VCC 5%.
A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 VILP VILP VIHP
MODE PGM VIL VIH VIH VIH VIL VIL VIL VILP VIHP VIHP VILP VILP VILP
CLK CLK VIL/VIH VIL/VIH VIL/VIH VIL/VIH VIL VIL/VIH VIL VILP VILP VILP VILP VILP VILP
SDI NA X VIL VIH DIN X X X X X X X X X
SDO VFY High Z SDI SDI SDO High Z High Z High Z VIHP VILP VIHP VIHP VIHP VIHP
E, I VPP VIL VIL VIL VIH VIL VIL VIL VPP VPP VPP VPP VPP VPP
O7 - O0 D7 - D0 O7 - O0 O7 - O0 O7 - O0 O7 - O0 O7 - O0 O7 - O0 O7 - O0 D7 - D0 O7 - O0 High Z D7 - D0 D7 - D0 D7 - D0
Other
7
CY7C269
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.6 1.4 1.2 ICC 1.0 20 0.8 0.6 4.0 0.9 TA =25C f=MAX. 4.5 5.0 5.5 6.0 10 0.8 -55 25 125 0 0.0 1.0 2.0 3.0 4.0 1.0 1.2 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 60 50 1.1 40 ICC 30 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE
SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 1.4 125 1.2 1.0 0.8 0.6 -55 100 75 50 25 25 125 0 0.0 175 150
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 35 30 25 20 15 10
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
VCC =5.0V TA =25C 1.0 2.0 3.0 4.0
5 0 0 200 400
VCC =4.5V TA =25C 600 800 1000
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V) NORMALIZED SUPPLY CURRENT vs. CLOCK PERIOD 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0 25 50 75 100 CLOCK PERIOD (ns) VCC =5.5V TA =25C
CAPACITANCE (pF)
8
CY7C269
Ordering Information[11]
Speed (ns) 15 ICC (mA) 120 Ordering Code CY7C269-15JC CY7C269-15PC CY7C269-15WC 140 CY7C269-15DMB CY7C269-15LMB CY7C269-15QMB CY7C269-15WMB 25 140 CY7C269-25JC CY7C269-25PC CY7C269-25WC CY7C269-25DMB CY7C269-25LMB CY7C269-25QMB CY7C269-25WMB 40 100 CY7C269-40JC CY7C269-40PC CY7C269-40WC 50 80 CY7C269-50JC CY7C269-50PC CY7C269-50WC 120 CY7C269-50DMB CY7C269-50LMB CY7C269-50QMB CY7C269-50WMB Package Name J64 P21 W22 D22 L64 Q64 W22 J64 P21 W22 D22 L64 Q64 W22 J64 P21 W22 J64 P21 W22 D22 L64 Q64 W22 Package Type 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 28-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 28-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 28-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 28-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Windowed CerDIP 28-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Pin Windowed Leadless Chip Carrier 28-Lead (300-Mil) Windowed CerDIP Military Commercial Commercial Military Commercial Military Operating Range Commercial
Note: 11. Most of these products are available in industrial temperature range. Contact a Cypress representative for specifications and product availability.
9
CY7C269
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameters VOH VOL VIH VIL IIX IOZ ICC ISB Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Diagnostic Mode Switching Characteristics
Parameters tSSDI tHSDI tDSDO tDCL tDCH tHM tMS tSS Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
Document #: 38-00069-G
Switching Characteristics
Parameters tAS tHA tCO tPW tSES tHES tCOS Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
10
CY7C269
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
28-Lead Plastic Leaded Chip Carrier J64
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
28-P in Windowed Leadless Chip Carrier Q64
MIL-STD-1835 C-4
11
CY7C269
Package Diagrams (continued)
28-Lead (300-Mil) Molded DIP P21
28-Lead (300-Mil) Windowed CerDIP W22
MIL-STD-1835 D- Config. A 15
(c) Cypress Semiconductor Corporation, 1992. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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