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V961PBC Rev. B2
LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS
* Glueless interface between Intel i960Jx, IBM PPC401Gx, processors and PCI bus * Fully compliant with PCI 2.1 specification * Configurable for primary master, bus master, or target operation * Up to 1Kbyte burst access support on both local and PCI interface * 576 bytes of programmable FIFO storage with DYNAMIC BANDWIDTH ALLOCATIONTM * Two channel DMA controller * Enhanced support for 8/16-bit local bus devices with programmable region size register * 16 8-bit bi-directional mailbox registers with doorbell interrupts V961PBC provides the highest performance, most flexible, and most economical method to directly connect i960Jx or PPC401Gx processors to the PCI bus. V961PBC is also a suitable candidate for a variety of 32-bit multiplexed local bus applications based on Motorola, IBM, Intel embedded processors - where a minimal amount of glue logic is required. V961PBC may also be used in systems without a CPU for a generic PCI master/target interface. V961PBC Rev B2 is the first I2O ready PCI bridge, fully backward compatible with V292PBC Rev B1. The PCI bus can be run at the full 33MHz frequency, independent of local bus clock rate. The overall throughput of the system is dramatically improved by increasing the FIFO depth and utilizing the unique DYNAMIC
* Dual bi-directional address space remapping * On-the-fly byte order (endian) conversion * Optional power on serial EEPROM initialization * I2O ATU and messaging unit including hardware controlled circular queues * Flexible PCI and local interrupt management * Support for real-mode DOS "holes" * Ability to generate both Type 0 and Type 1 configuration cycles * 33MHz and 40MHz local bus versions available with independent PCI operation up to 33MHz * Low cost 160-pin EIAJ PQFP package
BANDWIDTH ALLOCATIONTM architecture. Access to the PCI bus can be performed through two programmable address apertures. Two more apertures are provided for PCI-to-local bus accesses. There are 32-bytes of read FIFO's in each direction, 16-byte dedicated for each aperture. V961PBC also includes bi-directional remapping capabilities, and on-the-fly byte order conversion Two DMA channels are provided for autonomous PCI-to-Local/Local-to-PCI transfers. Mailbox registers and flexible PCI interrupt controllers are also included to provide a simple mechanism to emulate PCI device control ports. The part is available in 160-pin low cost EIAJ Plastic Quad Flat Pack (PQFP) package.
i960Jx PPC401Gx CPU
V96BMC MEMORY CONTROL
D R A M
ROM
TYPICAL APPLICATION
V961PBC
LOCAL TO PCI BRIDGE
PCI SLOT or EDGE CONNECTOR
PCI PERIPHERAL
Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC Data Sheet Rev 2.4
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V3 Semiconductor reserves the right to change the specifications of this product without notice. V961PBC, V96SSC and V96BMC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.
V961PBC
This document contains the product codes, pinouts, package mechanical information, DC characteristics, and AC characteristics for the V961PBC. Detailed functional information is contained in the User's Manual. V3 Semiconductor retains the rights to change documentation, specifications, or device functionality at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design.
1.0 Product Codes
Table 1: Product Codes
Product Code V961PBC-33 REV B2 Processor i960JA/JD/JF PPC401GF i960JA/JD/JF PPC401GF Bus Type 32-bit multiplexed Package 160-pin EIAJ PQFP Frequency 33MHz
V961PBC-40 REV B2
32-bit multiplexed
160-pin EIAJ PQFP
40MHz
2.0 Pin Description and Pinout
Table 2 below lists the pin types found on the V961PBC. Table 3 describes the function of each pin on the V961PBC. Table 5 lists the pins by pin number. Figure 1 shows the pinout for the 160-pin EIAJ PQFP package and Figure 2 shows the mechanical dimensions of the package.
Table 2: Pin Types
Pin Type PCI I PCI O PCI I/O PCI I/OD I/O4 I O4 PCI input only pin. PCI output only pin. PCI tri-state I/O pin. PCI input with open drain output. TTL I/O pin with 4mA output drive. TTL input only pin. TTL output pin with 4mA output drive. Description
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V961PBC
Table 3: Signal Descriptions
PCI Bus Interface Signal AD[31:0] C/BE[3:0] PAR FRAME Type PCI I/O PCI I/O PCI I/O PCI I/O Ra Z Z Z Z Description Address and data, multiplexed on the same pins. Bus Command and Byte Enables, multiplexed on the same pins. Parity represents even parity across AD[31:0] and C/BE[3:0]. Cycle Frame indicates the beginning and burst length of an access. Initiator Ready indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. Target Ready indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. Stop indicates the current target is requesting the master to stop the current transaction (retry or disconnect). Device Select, when actively driven by a target, indicates the driving device has decoded its address as the target of the current access. As an input to the initiator, DEVSEL indicates whether any device on the bus has been selected. Initialization Device Select is used as a chip select during configuration read and write transactions. It must be driven high in order to access the chip's internal configuration space. H Request indicates to the arbiter that this agent requests use of the bus. Grant indicates to the agent that access to the bus has been granted. PCLK provides timing for all transactions on the PCI bus. Acts as an input when RDIR is high, an output when RDIR is low. As an input it is asserted low to bring all internal PBC operation to a reset state. Parity Error is used to report data parity errors during all PCI transactions except a Special Cycle. System Error is used to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. Level-sensitive interrupt requests may be received or generated.
IRDY
PCI I/O
Z
TRDY
PCI I/O
Z
STOP
PCI I/O
Z
DEVSEL
PCI I/O
Z
IDSEL
PCI I
REQ
PCI O
GNT PCLK
PCI I PCI I
PRST
PCI I/O
Z/L
PERR
PCI I/O
Z
SERR
PCI I/OD
Z
INT[A:D]
PCI I/OD
Z
Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC Data Sheet Rev 2.4
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V961PBC
Table 3: Signal Descriptions (cont'd)
Local Bus Interface Signal LAD[31:0] LA[5:2] BE[3:0] W/R ALE ADS RDYRCV HOLD HOLDA LPAR[3:0] BLAST BTERM LINT LRST LCLK Type I/O4 O4 I/O4 I/O4 I/O4 I/O4 I/O4 O4 I I/O4 I/O4 I/O4 O4 I/O4 I Z Z Z H L/Z R Z Z Z Z Z Z Z L Description Local multiplexed address and data bus. Lower local address bus. Generated during local bus master cycles and increments during a burst. Local bus byte enables. Write/Read. Address Latch Enable: used to latch the address during the address phase. Asserted low to indicate the beginning of a bus cycle. Local Bus data ready. Local bus hold request: asserted by the chip to initiate a local bus master cycle. Local bus hold acknowledge. Local bus parity. Burst last. Bus Time-out. Burst terminate. Local interrupt request. Local bus RESET signal. Local bus clock.
Serial EEPROM Interface Signal SCL/LPERR SDA Type O4 I/O4 R X X Description EEPROM clock. Local parity error. EEPROM data.
Configuration Signal RDIR Type I R Description Reset direction. Tie low to drive PRST out and LRST in, high to drive LRST out and PRST in.
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Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC
Table 3: Signal Descriptions (cont'd)
Power and Ground Signals Signal VCC GND Type R Description POWER leads intended for external connection to a VCC board plane. GROUND leads intended for external connection to a GND board plane.
-
a. R indicates state during reset.
2.1
Test Mode Pins
Several device pins are used during manufacturing test to put the V961PBC device into various test modes. These pins must be maintained at proper levels during reset to insure proper operation. This is typically handled through pull-up or pull-down resistors (typically 1K to 10K) on the signal pins if they are not guaranteed to be at the proper level during reset. Table 4 below shows the reset states for test mode pins:
Table 4: RESET State for Test Mode Pins
PIN# Connection 134 Pull-Down 135 Pull-Up 153 Pull-Down
Table 5: Pin Assignments
PIN # 1 2 3 4 5 6 7 8 Signal VCC INTD PRST PCLK GNT REQ AD31 AD30 PIN # 41 42 43 44 45 46 47 48 Signal VCC AD14 AD13 AD12 AD11 AD10 AD9 AD8 PIN # 81 82 83 84 85 86 87 88 Signal VCC NC LAD8 NC LAD9 NC LAD10 NC PIN # 121 122 123 124 125 126 127 128 Signal VCC NC LAD25 LA5 LAD26 LA4 LAD27 LA3
Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC Data Sheet Rev 2.4
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V961PBC
Table 5: Pin Assignments (cont'd)
PIN # 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3 IDSEL AD23 AD22 VCC GND AD21 AD20 AD19 AD18 AD17 AD16 C/BE2 FRAME GND IRDY TRDY DEVSEL STOP PERR PIN # 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal C/BE0 VCC GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VCC GND LAD0 NC LAD1 NC LAD2 NC LAD3 NC LAD4 NC LAD5 NC LAD6 NC PIN # 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 Signal LAD11 NC LAD12 NC LAD13 NC LAD14 NC LAD15 NC LAD16 VCC GND NC LAD17 NC LAD18 NC LAD19 NC LAD20 NC LAD21 NC LAD22 NC LAD23 PIN # 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 Signal LAD28 LA2 LAD29 LAD30 LAD31 ALE BTERM RDYRCV HOLD HOLDA ADS VCC GND LCLK GND VCC BE3 BE2 BE1 BE0 BLAST W/R RDIR LRST '0' LINT SDA
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V961PBC Data Sheet Rev 2.4
Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC
Table 5: Pin Assignments (cont'd)
PIN # 36 37 38 39 40 Signal SERR PAR C/BE1 AD15 GND PIN # 76 77 78 79 80 Signal LAD7 NC LPAR0 LPAR1 GND PIN # 116 117 118 119 120 Signal NC LPAR2 LPAR3 LAD24 GND PIN # 156 157 158 159 160 Signal SCL/ LPERR INTA INTB INTC GND
Figure 1: Pinout for 160-pin EIAJ PQFP (top view)
Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC Data Sheet Rev 2.4
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V961PBC
Figure 2: 160-pin EIAJ PQFP mechanical details
Unit of Measurement = millimeters
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V961PBC Data Sheet Rev 2.4
Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC 3.0 DC Specifications
The DC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.1, Section 4.2.1.1. For more information on the PCI DC specifications, see the PCI Specification.
Table 6: Absolute Maximum Ratings
Symbol VCC VIN IIN TSTG Parameter Supply voltage DC input voltage DC input current Storage temperature range Value -0.3 to +7 -0.3 to VCC+0.3 10 -40 to +125 Units V V mA C
Table 7: Guaranteed Operating Conditions
Symbol VCC TA Parameter Supply voltage Ambient temperature range Value 4.75 to 5.25 0 to 70 Units V C
3.1
PCI Bus DC Specifications Table 8: PCI Bus Signals DC Operating Specifications
Symbol VIH VIL IIH IIL VOH VOL CIN CCLK CIDSEL LPIN
Parameter Input high voltage Input low voltage Input high leakage current Input low leakage current Output high voltage Output low voltage Input pin capacitance PCLK pin capacitance IDSEL pin capacitance Pin inductance
Condition
Min 2.0 -0.5
Max VCC+0.5 0.8 70 -70
Units V V A A V
Notes
VIN = 2.7V VIN = 0.5V IOUT = -2mA IOUT = 3mA, 6mA 2.4
1 1
0.55 10 5 12 8 20
V pF pF pF nH
2 3
4
Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC Data Sheet Rev 2.4
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V961PBC
Notes: 1. Input leakage currents include high impedance output leakage for all bi-directional buffers with tri-state outputs. 2. Signals without pull-up resistors have greater than 3mA low output current. Signals requiring pull resistors have greater than 6mA output current. The latter include FRAME, TRDY, IRDY, STOP, SERR, PERR. 3. Absolute maximum pin capacitance for a PCI unit is 10pF (except for CLK). 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
3.2
Local Bus DC Specifications
Table 9: Local Bus Signals DC Operating Specifications
Symbol VIL VIH IIL IIH VOL4 VOH4 IOZL IOZH Description Low level input voltage High level input voltage Low level input current High level input current Low level output voltage for 4 mA outputs and I/O pins High level output voltage for 4 mA outputs and I/O pins Low level float input leakage High level float input leakage Conditions VCC = 4.75V VCC = 5.25V VIN=GND, VCC=5.25V VIN = VCC = 5.25V IOL = -4 mA IOH = 4 mA VIN = GND VIN = VCC VCC = 5.25V PCLK = LCLK = 33MHz VCC = 5.0V PCLK = LCLK = 33MHz 2.4 -10 10 150 2.0 -10 10 0.4 Min Max 0.8 Units V V A A V
V A A mA
ICC (max) Maximum supply current ICC (typ) CIO Typical supply current Input and output capacitance
120 10
mA pF
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V961PBC Data Sheet Rev 2.4
Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC 4.0 AC Specifications
The AC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.1, Section 4.2.1.2. For more information on the PCI AC specifications, including the V/I curves for 5V signalling, see section 4.2.1.2 of Rev 2.1 PCI Specification.
4.1
PCI Bus Timings Table 10: PCI Bus Signals AC Operating Specifications
Symbol
Parameter Switching current high (Test point) Switching current low (Test point)
Condition 0VVOUT>0.55 VOUT=0.71 -5Min -44 -44+(VOUT-1.4)/0.024
Max
Units mA
Notes 1 1, 2, 3 3 1 1, 3 3
IOH(AC)
Equation A -142
mA mA mA
95 VOUT/0.023 Equation B 206 -25+(VIN+1)/0.015 1 5
IOL(AC)
mA mA mA
ICL tR tF
Low clamp current Unloaded output rise time Unloaded output fall time
V/ns
4
2.4V to 0.4V
1
5
V/ns
4
Notes: 1. Refer to the V/I curves in Section 4.2.1 of the PCI Specification. This specification does not apply to CLK and RST which are system outputs. "Switching Current High" specifications are not relevant to open drain outputs such as SERR and INTA-INTD. 2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the voltage rail (as it does in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up. 3. Maximum current requirements are met as drivers pull beyond the first step voltage (AC drive point). Equations defining these maximums (A and B) are provided with the respective V/I curves given in the PCI Spec. The equation defined maxima is met by design. 4. The minimum slew rate (slowest signal edge) is met by the PCI drivers. The maximum slew rate (fastest signal edge) is a guideline. Motherboard designers must bear in mind that rise and fall times faster than this maximum guideline could occur, and should ensure that signal integrity modeling accounts for this. Equation A: IOH = 11.9*(VOUT - 5.25V)*(VOUT + 2.45V) for VCC > VOUT > 3.1V Equation B: IOL = 78.5*VOUT(4.4V - VOUT) for 0V < VOUT < 0.71V
Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC Data Sheet Rev 2.4
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4.2 Local Bus Timings Table 11: i960Jx Local Bus AC Test Conditions
Symbol VCC VIN COUT Parameter Supply voltage Input low and high voltages Capacitive load on output and I/O pins Limits 4.75 to 5.25 0.4 and 2.0 50 Units V V pF
Table 12: Capacitive Derating for Output and I/O Pins
Output Drive Limit 4mA Derating 0.058 ns/pF for loads > 50pF
Figure 3: Clock and Synchronous Signals
Figure 4: ALE Signal
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V961PBC Data Sheet Rev 2.4
Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC
Table 13: Local Bus Timing Parameters for Vcc = 5 Volts +/- 5%
33MHz # 1 2 3 4 4a 4b 4c 4d Symbol TC TCH TCL TSU TSU TSU TSU TSU TSU TH TCOV TCOV TCZO TCOZ TRST LCLK period LCLK high time LCLK low time Synchronous input setup Synchronous input setup (BLAST) Synchronous input setup (W/R, BTERM) Synchronous input setup (ADS) Synchronous input setup (address, data, byte enables) Synchronous input setup for read data when in local bus master mode Synchronous input hold LCLK to output valid delay LCLK to output valid delay (address, data, byte enable, parity) LCLK to output driving delay LCLK to high impedance delay Reset period when LRST used as input 4 3 3 3 3 3 16*TC 1 1 2 Description Notes Min 30 12 12 7 8 4 6 9 Max 40MHz Min 25 11 11 6 7 4 5 8 Max Units ns ns ns ns ns ns ns ns
4e 5 6 6a 7 8 9
5 2 14 15 15 15
5 2 3 3 3 3 16*TC 12 14 14 14
ns ns ns ns ns ns ns
Notes: 1. Measured at 1.5V. 2. All local bus signals except those in 4a, 4b, 4c, 4d and 4e. 3. All local bus signals except those in 6a. 4. RDYRCV, BLAST, ADS are driven to high impedance at the falling edge of LCLK.
Table 14: ALE Timing Parameters for Vcc = 5 Volts +/- 5%
33MHz # Symbol 1 2 TALE TASUO Description ALE Pulse Width Address setup to ALE falling (ALE as output) Min TCH-4 TCH-5 Max 40MHz Min TCH-4 TCH-4 Max Units ns ns
Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC Data Sheet Rev 2.4
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V961PBC
Table 14: ALE Timing Parameters for Vcc = 5 Volts +/- 5%
3 TAHO TASUI TAHI Address hold from ALE falling (ALE as output) Address setup to ALE falling (ALE as input) Address hold from ALE falling (ALE as input) TCL-5 5 TCL-4 5 ns
4
ns
5
5
5
ns
Table 15: PCI Bus Timing Parameters for Vcc = 5 Volts +/- 5%
# 1 2 2a 3 4 4a 5 6 7 Symbol TC TSU TSU TH TCOV TCOV TCZO TCOZ TRST PCLK period Synchronous input setup to PCLK Synchronous input setup to PCLK (GNT) Synchronous input hold from PCLK PCLK to output valid delay PCLK to output valid delay (REQ) PCLK to output driving delay PCLK to high impedance delay Reset period when PRST used as input 2 1 Description Notes Min 30 7 10 0 3 4 4 5 16*TC 11 12 11 18 Max Units ns ns ns ns ns ns ns ns
Notes: 1. All PCI bus signals except those in 2a. 2. All PCI bus signals except those in 4a.
4.3
Serial EEPROM Port TImings
The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms generated are shown in Figure 5.
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V961PBC Data Sheet Rev 2.4
Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC
Figure 5: Serial EEPROM Waveforms and Timings
512 PCI BUS CLOCKS STOP CONDITION
START CONDITION
SCL
SDA
256 PCI BUS CLOCKS
256 PCI BUS CLOCKS
5.0 Revision History
Table 16: Revision History
Revision Number 2.4 2.3 Date 5/98 10/96 Comments and Changes Data sheet update of B2-step values Data Book revision. 1. In Table 3, changed "LPAR[3:0]" to "LPAR[3:0]". 1. In Table 3, changed "PERR I/OD" to "PERR I/O". 2. In Table 3, added "VCC" and "GND" description. 3. In Table 13 and 14 , added min TCOV and min TCZO timing. 1. Updated timings to final B1-step values. 2. Simplified data sheet format.
2.2
06/96
2.1
03/96
2.0
Removed operational description (found in User's Manual). Device related changes: 1. LA5, LA4, LA3, LA2 pins added to pinout for V960PBC and V961PBC. 11/95 2. Changed references to PCI 2.0 to PCI 2.1 spec level compliance. 3. Updated timings to final B0-step values. 4. Added new TCZO timing. 5. Added test mode pin description.
Copyright (c) 1998, V3 Semiconductor Inc.
V961PBC Data Sheet Rev 2.4
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V961PBC
Table 16: Revision History (cont'd)
Revision Number Date Comments and Changes 1. In Table 1, changed Draining Strategy to "3 or more words" from "4 or more writes". 2. In Table 3, changed Base Address 3 to Unimplemented. 3. In Table 5, changed "PAR" to "PAR". 4. In Table 6, changed "SCL" to "SCL/PERR". 5. In Table 6, changed SDA to "I/O4 from "O4". 6. In Table 6, changed ROMCSx,LREQ, and ADS to "I/O4" from"O4" (device dependent). 7. In Table 6, changed GREQ,LBREQ, and HOLD to "O4" from "I/O4" (device dependent). 8. In Table 6, changed BURST and BLAST to "I/O4" from "O4" (device dependent). 9. In Table 6, changed ERR and BTERM to "I/O4" from "O4" (device dependent). 10. In Table 14, added timings for 16MHz and 40MHz (device dependent). First released version of the data sheet. Some changes to AC and DC specifications and to waveforms. All future changes to the data sheet will be documented in detail in this section. Clean pinouts. Some DC and AC specs. Sent only to a limited number of customers. First pre-silicon revision of preliminary data sheet. DC and AC specs TBD. Sent only to a limited number of customers.
1.3
4/95
1.2
3/95
1.1
2/95
1.0
1/95
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V961PBC Data Sheet Rev 2.4
Copyright (c) 1998, V3 Semiconductor Inc.

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