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Preliminary Technical Data FEATURES 3.3 V/5.2 V single-supply operation 150 ps propagation delay 15 ps overdrive and slew rate dispersion 8 GHz equivalent input risetime bandwidth 80 ps minimum pulse width 35 ps typical output rise/fall 10 ps deterministic jitter (DJ) 200 fs random jitter (RJ) On-chip terminations at both input pins Robust inputs with no output phase reversal Resistor programmable hysteresis Differential latch control Power supply rejection > 70 dB Ultrafast 3.3 V Single-Supply Comparators ADCMP572/ADCMP573 FUNCTIONAL BLOCK DIAGRAM VCCI VCCO VTP TERMINATION VP NONINVERTING INPUT VN INVERTING INPUT VTN TERMINATION LE INPUT HYS LE INPUT 04409-0-025 ADCMP572 ADCMP573 Q OUTPUT CML/ RSPECL Q OUTPUT Figure 1. APPLICATIONS Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Clock and data signal restoration GENERAL DESCRIPTION The ADCMP572/ADCMP573 are ultrafast comparators fabricated on Analog Devices, Inc.'s proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP572 features CML output drivers, and the ADCMP573 features reduced swing PECL (RSPECL) output drivers. Both devices offer 150 ps propagation delay and 100 ps minimum pulse width for 10 Gbps operation with 200 fs RMS random jitter (RJ). Overdrive and slew rate dispersion is typically less than 15 ps. A flexible power supply scheme allows either device to operate with a single +3.3 V positive supply and a -0.2 V to +1.2 V input signal range, or with split input/output supplies to support a wider -0.2 V to +3.2 V input signal range and an independent range of output levels. 50 on-chip termination resistors are provided at both inputs with the optional capability to leave open (on an individual pin basis) for applications requiring high impedance inputs. The CML output stage is designed to directly drive 400 mV into 50 transmission lines terminated to between 3.3 V to 5.2 V. The RSPECL output stage is designed to drive 400 mV into 50 terminated to VCCO - 2 V and is compatible with several commonly used PECL logic families. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided. The ADCMP572/ADCMP573 are available in a 16-lead LFCSP package. Rev. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. ADCMP572/ADCMP573 TABLE OF CONTENTS Electrical Characteristics ................................................................. 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Application Information.................................................................. 9 Power/Ground Layout and Bypassing ....................................... 9 CML/RSPECL Output Stage ....................................................... 9 Using/Disabling the Latch Feature............................................. 9 Preliminary Technical Data Optimizing High Speed Performance ..................................... 10 Comparator Propagation Delay Dispersion ........................... 10 Comparator Hysteresis .............................................................. 11 Minimum Input Slew Rate Requirement ................................ 11 Typical Application Circuits.......................................................... 12 Timing Information ....................................................................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14 REVISION HISTORY 6/04--Revision PrB: Preliminary Version 2/04--Revision PrA: Preliminary Version Rev. PrB | Page 2 of 16 Preliminary Technical Data ELECTRICAL CHARACTERISTICS VCCI = VCCO = 3.3 V, TA = 25C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Input Voltage Range Input Differential Voltage Input Offset Voltage Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Capacitance Input Impedance Input Resistance, Differential Mode Input Resistance, Common Mode Active Gain Common-Mode Rejection Symbol VP, VN Conditions VCCI = 3.3 V, VCCO = 3.3 V VCCI = 5.2 V, VCCO = 3.3 V Min -0.2 -0.2 -1.2 -5.0 -50.0 -5.0 CP, CN 47.5 Open termination Open termination AV CMRR VCCI = 3.3 V, VCCO = 3.3 V, VCM = 0.0 V to 1.0 V VCCI = 5.2 V, VCCO = 3.3 V, VCM = 0.0 V to 3.0 V ADCMP572/ADCMP573 Typ Max +1.2 +3.2 +1.2 +5.0 0.0 +5.0 52.5 Unit V V V mV V/C A nA/C A pF k k dB dB dB mV VOS VOS/dT IP, IN Open termination 2.0 10.0 -25.0 50.0 2.0 TBD 50 50 500 54 50 40 1 Hysteresis LATCH ENABLE CHARACTERISTICS ADCMP572 Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time ADCMP573 Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time Latch Enable Input Impedance Latch to Output Delay Latch Minimum Pulse Width DC OUTPUT CHARACTERISTICS ADCMP572 (CML) Output Impedance Output Voltage High Level Output Voltage Low Level Output Voltage Differential Temperature Coefficient, VOH Temperature Coefficient, VOL ADCMP573 (RSPECL) Output Voltage High Level Output Voltage Low Level Output Voltage Differential RHYS = 2.8 0.2 tS tH VOD = 100 mV VOD = 100 mV 1.8 0.2 tS tH tPLOH, tPLOL tPL VOD = 100 mV VOD = 100 mV 47.5 VOD = 100 mV VOD = 100 mV 0.4 15 0 VCCO+0.2 0.5 V V ps ps V V ps ps ps ps 0.4 0 50 50.0 150 100 VCCO-0.6 0.5 52.5 ZOUT VOH VOL VOH/dT VOL/dT VOH VOL -8 mA < I OUT < 8 mA 50 terminate to VCCO 50 terminate to VCCO 50 terminate to VCCO 50 terminate to VCCO 50 terminate to VCCO 50 terminate to VCCO-2.0 50 terminate to VCCO-2.0 50 terminate to VCCO-2.0 47.5 VCCO-0.10 VOH-0.45 350 50.0 VCCO-0.05 VOH-0.40 400 TBD TBD VCCO-0.80 VOH-0.40 400 52.5 VCCO VOH-0.35 450 V V mV mV/C mV/C V V mV VCCO-0.90 VOH-0.45 350 VCCO-0.70 VOH-0.35 450 Rev. PrB | Page 3 of 16 ADCMP572/ADCMP573 Parameter AC PERFORMANCE Propagation Delay Symbol tPD Conditions VCCI = 3.3 V, VOD = 200 mV VCCI = 3.3 V, VOD = 20 mV VCCI = 5.2 V, VOD = 200 mV VOD = 200 mV, 5 V/ns 50 mV < VOD < 1.0 V, 5 V/ns 10 mV < VOD < 1.0 V, 5 V/ns 2 V/ns to 10 V/ns 100 ps to 5 ns VCCI = 3.3 V, 1 V/ns, VCM = 0 V VCCI = 5.2 V, 1 V/ns, VCM = 0 V VOD=0.4V, 0.0 V < VCM < 1.0 V 0.0 V to 400 mV input tR = tF = 25 ps, 20/80 > 50% Output Swing VOD = 200 mV, 5 V/ns, PRBS31-1 NRZ, 4 Gbps VOD = 200 mV, 5 V/ns, PRBS31-1 NRZ, 10 Gbps VOD = 200 mV, 5 V/ns, 1.25 GHz Preliminary Technical Data Min Typ 150 165 145 0.5 10 10 15 15 5 5 10 5 8.0 12.5 10 TBD 0.2 100 80 35 35 3.1 3.1 -0.2 5.4 5.4 +2.3 Max Unit ps ps ps ps/C ps ps ps ps ps ps ps/V GHz Gbps ps ps ps ps ps ps ps V V V Propagation Delay Tempco Prop Delay Skew--Rising Transition to Falling Transition Overdrive Dispersion Slew Rate Dispersion Pulse Width Dispersion Duty Cycle Dispersion Common-Mode Dispersion Equivalent Input Bandwidth1 Toggle Rate Deterministic Jitter Deterministic Jitter RMS Random Jitter Minimum Pulse Width Minimum Pulse Width Rise Time Fall Time POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential ADCMP572 (CML) Positive Supply Current tPD/dT BWEQ DJ DJ RJ PWMIN PWMIN tR tF VCCI VCCO VCCI -VCCO IVCCI + IVCCO tPD/PW < 5 ps tPD/PW < 10 ps 20/80 20/80 Power Dissipation PD VCCI = 3.3 V, VCCO = 3.3 V, terminate 50 to VCCO VCCI = 5.2 V, VCCO = 5.2 V, terminate 50 to VCCO VCCI = 3.3 V, VCCO = 3.3 V, terminate 50 to VCCO VCCI = 5.2 V, VCCO = 5.2 V, terminate 50 to VCCO VCCI = 3.3 V, VCCO = 3.3 V, 50 to VCCO - 2 V VCCI = 5.2 V, VCCO = 5.2 V, 50 to VCCO - 2V VCCI = 3.3 V, VCCO = 3.3 V, 50 to VCCO - 2 V VCCI = 5.2 V, VCCO = 5.2 V, 50 to VCCO - 2 V VCCI = 3.3 V 5%, VCCO = 3.3 V 44 44 145 240 52 52 160 265 mA mW ADCMP573 (RSPECL) Positive Supply Current IVCCI + IVCCO 66 68 145 175 74 74 76 160 195 mA Power Dissipation PD mW Power Supply Rejection--VCCI PSRVCCI dB 1 Equivalent Input Bandwidth assumes a simple first-order response and is calculated with the following formula: BWEQ = 0.22/*(trCOMP2-trIN2), where trIN is the 20/80 transition time of a quasi-Gaussian signal applied to the comparator input and trCOMP is the effective transition time digitized by the comparator. Rev. PrB | Page 4 of 16 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 2. Parameter SUPPLY VOLTAGES Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Positive Supply Differential (VCCI - VCCO) INPUT VOLTAGES Input Voltage Differential Input Voltage Input Voltage, Latch Enable HYSTERESIS CONTROL PIN Applied Voltage (HYS to GND) Maximum Input/Output Current OUTPUT CURRENT ADCMP572 (CML) ADCMP573 (RSPECL) TEMPERATURE Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating -0.5 V to +6.0 V -0.5 V to +6.0 V -0.5 V to +3.5 V ADCMP572/ADCMP573 Thermal Considerations The ADCMP572/ADCMP573 LFCSP 16-lead package has a JA (junction to ambient thermal resistance) of 70C/W in still air. Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -0.5 V to VCCI + 0.5 V (VCCI + 0.5 V) -0.5 V to VCCO + 0.5 V -0.5 V to +1.5 V 1 mA 20 mA -35 mA -40C to +85C 125C -65C to +150C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrB | Page 5 of 16 ADCMP572/ADCMP573 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 16 15 PIN1 14 13 12 11 10 9 5 6 7 8 Preliminary Technical Data GND VCCI HYS VTP 1 VP 2 VN 3 VTN 4 VCCI VCCO Q Q VCCO 04409-0-026 ADCMP572 ADCMP573 TOP VIEW (Not to Scale) Figure 2. ADCMP572/ADCMP573 Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5, 16 6 Mnemonic VTP VP VN VTN VCCI LE Description Termination Resistor Return Pin for VP Input. Noninverting Analog Input. Inverting Analog Input. Termination Resistor Return Pin for VN Input. Positive Supply Voltage for Input Stage. Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator's being placed in latch mode. LE must be driven in compliment with LE. Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the comparator's being placed in latch mode. LE must be driven in compliment with LE. Termination Return Pin for the LE/LE Input Pins. For the ADCMP572 (CML output stage), this pin should be connected to the positive VCCO supply. For the ADCMP573 (RSPECL output stage), this pin should be connected to the VCCO - 2 V termination potential. Ground. Positive Supply Voltage for the CML/RSPECL Output Stage. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided the comparator is in compare mode. See the LE/LE description (Pins 6 and 7) for more information. Noninverting Output. Q is at logic high if the analog voltage at the noninverting input VP is greater than the analog voltage at the inverting input, VN, provided the comparator is in compare mode. See the LE/LE description (Pins 6 and 7) for more information. Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of RHYS hysteresis control resistor. The metallic back surface of the package is not electrically connected to any part of the circuit, and it can be left floating for best electrical isolation between the package handle and the substrate of the die. But it can also be soldered to the application board if improved thermal and/or mechanical stability is desired. 7 LE 8 VCCO/VTT 13, 15 9, 12 10 GND VCCO Q 11 Q 14 HYS Heatsink N/C Rev. PrB | Page 6 of 16 VCCO/VTT LE LE Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS VCCI = VCCO = 3.3 V, TA = 25C, unless otherwise noted. 20 ADCMP572/ADCMP573 39.0 PROPAGATION DELAY ERROR (ps) 38.5 15 RISE/FALL TIME (ps) 38.0 10 37.5 37.0 5 36.5 0 50 100 150 200 250 -40 -20 0 20 40 60 80 100 INPUT OVERDRIVE VOLTAGE (mV) TEMPERATURE (C) Figure 3. Propagation Delay vs. Input Overdrive Figure 6. Rise/Fall Time vs. Temperature 158.5 60 158.0 PROPAGATION DELAY (ps) 50 HYSTERESIS (mV) 157.5 40 157.0 30 156.5 20 156.0 10 04409-0-040 0 0.2 0.4 0.6 0.8 1.0 1.2 0 1 2 3 RHYS (k) 4 5 6 INPUT COMMON-MODE VOLTAGE (V) Figure 4. Propagation Delay vs. Input Common Mode 160 Figure 7. Hysteresis vs. RHYS Control Resistor -15.0 158 PROPAGATION DELAY (ps) INPUT BIAS CURRENT (A) -15.5 156 154 -16.0 -16.5 152 -17.0 150 -17.5 148 146 -60 -18.0 04409-0-041 -40 -20 0 20 40 60 80 100 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 TEMPERATURE (C) VP INPUT VOLTAGE (VN = -0.2V) Figure 5. Propagation Delay vs. Temperature Figure 8. Input Bias Current vs. Input Differential Rev. PrB | Page 7 of 16 04409-0-044 -18.5 -0.5 04409-0-043 155.5 0 04409-0-042 04409-0-039 0 36.0 -60 ADCMP572/ADCMP573 -16.2 380 -16.3 INPUT BIAS CURRENT (A) Preliminary Technical Data 379 -16.5 OUTPUT LEVELS (mV) 04409-0-045 -16.4 378 377 -16.6 376 -16.7 375 -16.8 -16.9 -60 374 373 -60 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) TEMPERATURE (C) Figure 9. Input Bias Current vs. Temperature Figure 11. Output Levels vs. Temperature Figure 10. Input Offset Voltage vs. Temperature Rev. PrB | Page 8 of 16 04409-0-046 Preliminary Technical Data APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING The ADCMP572/ADCMP573 comparators are very high speed SiGe devices. Consequently, it is essential to use proper high speed design techniques to achieve the specified performance. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. A 1 F electrolytic bypass capacitor should be placed within several inches of each power supply pin to ground. In addition, multiple high quality 0.1 F bypass capacitors should be placed as close as possible to each of the VCCI and VCCO supply pins and should be connected to the GND plane with redundant vias. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly avoided to maximize the effectiveness of the bypass at high frequencies. If the input and output supplies are connected separately such that VCCI VCCO, then care should be taken to bypass each of these supplies separately to the GND plane. A bypass capacitor should not be connected between them. It is recommended that the GND plane separate the VCCI and VCCO planes when the circuit board layout is designed to minimize coupling between the two supplies and to take advantage of the additional bypass capacitance from each respective supply to the ground plane. This enhances the performance when split input/output supplies are used. If the input and output supplies are connected together for single-supply operation such that VCCI = VCCO, then coupling between the two supplies is unavoidable; however, every effort should be made to keep the supply plane adjacent to the GND plane to maximize the additional bypass capacitance this arrangement provides. ADCMP572/ADCMP573 stripline techniques are essential to ensure proper transition times and to prevent output ringing and pulse-width dependant propagation delay dispersion. For the most timing critical applications where transmission line reflections pose the greatest risk to performance, the ADCMP572 provides the best match to 50 output transmission paths. VCCO 50 Q Q 16mA 04409-0-037 GND Figure 12. Simplified Schematic Diagram of the ADCMP572 CML Output Stage VCCO Q Q GND Figure 13. Simplified Schematic Diagram of the ADCMP573 RSPECL Output Stage CML/RSPECL OUTPUT STAGE Specified propagation delay dispersion performance can be achieved only by using proper transmission line terminations. The outputs of the ADCMP572 are designed to directly drive 400 mV into 50 cable or microstrip and/or stripline transmission lines properly terminated to the VCCO supply plane. The CML output stage is shown in the simplified schematic diagram of Figure 12. The outputs are each back-terminated with 50 for best transmission line matching. The RSPECL outputs of the ADCMP573 are illustrated in Figure 13 and should be terminated to VCCO - 2 V. As an alternative, Thevenin equivalent termination networks may also be used in either case if the direct termination voltage is not readily available. If high speed output signals must be routed more than a centimeter, microstrip or USING/DISABLING THE LATCH FEATURE The latch inputs (LE/LE) are active low for latch mode, and are internally terminated with 50 resistors to Pin 8. This corresponds to the VCCO supply for the ADCMP572 and the VTT pin for the ADCMP573. All VCCO pins should be connected to the supply plane for maximum performance, and the VTT pin should be connected externally to VCCO - 2 V, preferably to its own low inductance plane. When using the ADCMP572, the latch function can be disabled by connecting the LE pin to GND with an external pull-down resistor and leaving the LE pin unconnected. To prevent excessive power dissipation, the resistor should be 750 when VCCO = 3.3 V, and 1.2 k when VCCO = 5.2 V. When using the ADCMP573 comparator, the latch can be disabled by connecting the LE pin to VCCO with an Rev. PrB | Page 9 of 16 04409-0-038 ADCMP572/ADCMP573 external 500 resistor, and leaving the LE pin disconnected. In this case, the resistor value does not depend on the chosen VCCO supply voltage, assuming the VTT pin is properly connected to VCCO - 2 V. Preliminary Technical Data COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP572/ADCMP573 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to 500 mV. Propagation delay dispersion is a variation in propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold). Propagation delay dispersion is a specification that becomes important in high speed time critical applications such as data communication, automatic test and measurement, instrumentation, and event-driven applications such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 14 and Figure 15). For the ADCMP572/ADCMP573, dispersion is typically <15 ps because the overdrive is varied from 10 mV to 500 mV, and the input slew rate is varied from 2 V/ns to 10 V/ns. This specification applies for both positive and negative signals since the ADCMP572/ADCMP573 has substantially equal delays for either positive-going or negative-going inputs. 500mV OVERDRIVE OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator, proper design and layout techniques are essential to obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and can often cause oscillation. Discontinuities along input and output transmission lines can also severely limit the specified pulse-width dispersion performance. For applications working in a 50 environment, input and output matching has a significant impact on data dependant (or deterministic) jitter (DJ) and pulse-width dispersion performance. The ADCMP572/ADCMP573 comparators provide internal 50 termination resistors for both VP and VN inputs, and the ADCMP572 provides 50 back terminated outputs. The return side for each input termination is pinned out separately with the VTP and VTN pins, respectively. If a 50 termination is desired at one or both of the VP/VN inputs, then the VTP and VTN pins can be connected (or disconnected) to (from) the desired termination potential as required. The termination potential should be carefully bypassed using high quality bypass capacitors as discussed above to prevent undesired aberrations on the input signal due to parasitic inductance in the circuit board layout. If a 50 input termination is not desired, either one or both of the VTP/VTN termination pins can be left disconnected. In this case, the pins should be left floating with no external pull-downs or bypassing capacitors. It should be understood that when leaving an input termination disconnected, the internal resistor acts as a small stub on the input transmission path and can cause problems for very high speed inputs. Reflections should then be expected from the comparator inputs because they no longer provide a matched impedance to the input path leading to the device. It then becomes important to back-match the drive source impedance to the input transmission path to minimize multiple reflections. For applications in which the comparator is very close to the driving signal source, the source impedance should be minimized. High source impedance in combination with parasitic input capacitance of the comparator could cause an undesirable degradation in bandwidth at the input, thus degrading the overall response. Although the ADCMP572/ ADCMP573 comparators have been designed to minimize input capacitance, some parasitic capacitance is inevitable. It is therefore recommended that the drive source impedance be no more than 50 for best high speed performance. INPUT VOLTAGE 10mV OVERDRIVE VN VOS DISPERSION Q/Q OUTPUT Figure 14. Propagation Delay--Overdrive Dispersion INPUT VOLTAGE 1V/ns VN VOS 10V/ns DISPERSION Q/Q OUTPUT Figure 15. Propagation Delay--Slew Rate Dispersion Rev. PrB | Page 10 of 16 04409-0-028 04409-0-027 Preliminary Technical Data COMPARATOR HYSTERESIS The addition of hysteresis to a comparator is often desirable in a noisy environment or when the differential input amplitudes are relatively small or slow moving. The transfer function for a comparator with hysteresis is shown in Figure 16. If the input voltage approaches the threshold (0.0 V in this example) from the negative direction, the comparator switches from a low to a high when the input crosses +VH/2. The new switching threshold becomes -VH/2. The comparator remains in the high state until the threshold -VH/2 is crossed from the positive direction. In this manner, noise centered on 0.0 V input does not cause the comparator to switch states unless it exceeds the region bounded by VH/2. OUTPUT ADCMP572/ADCMP573 connecting an external pull-down resistor from the HYS pin to GND, a variable amount of hysteresis can be applied. Leaving the HYS pin disconnected disables the feature, and hysteresis is then less than 1 mV as specified. The maximum hysteresis that can be applied using this method is approximately 25 mV. Figure 17 illustrates the amount of hysteresis applied as a function of external resistor value. The advantages of applying hysteresis in this manner are improved accuracy, stability, and reduced component count. An external bypass capacitor is not recommended on the HYS pin because it would likely degrade the jitter performance of the device. 60 50 HYSTERESIS (mV) 40 VOH 30 20 VOL 10 0 1 2 3 RHYS (k) 4 5 6 -VH 2 0 +VH 2 INPUT 04409-0-005 Figure 17. Hysteresis vs. RHYS Control Resistor Figure 16. Comparator Hysteresis Transfer Function MINIMUM INPUT SLEW RATE REQUIREMENT As with all high speed comparators, a minimum slew rate requirement must be met to ensure that the device does not oscillate as the input signal crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator and the feedback parasitics inherent in the package. Analog Devices recommends a minimum slew rate of 50 V/s to ensure a clean output transition from the ADCMP572/ ADCMP573 comparators unless hysteresis is programmed as discussed previously. The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. A limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high speed performance, and can even induce oscillation in some cases. The ADCMP572/ADCMP573 comparators offer a programmable hysteresis feature that can significantly improve the accuracy and stability of the desired hysteresis. By Rev. PrB | Page 11 of 16 04409-0-043 0 ADCMP572/ADCMP573 TYPICAL APPLICATION CIRCUITS 3.3V Preliminary Technical Data VCCI = 5.2V VCCO = 3.3V/5.2V 3.3V/5.2V 50 50 Q VCCO VCCI VTP VIN VP VN VTN 50 50 Q ADCMP572 Q VIN VTH ADCMP572 Q 04409-0-029 LATCH INPUTS Figure 18. Zero-Crossing Detector with 3.3 V CML Outputs Figure 21. Comparator with 0 V to 3 V Input Range and 3.3 V or 5.2 V Positive CML Outputs VCCI = 5.2V VCCI VCCO = 3.3V 50 50 Q VTP VP VN VP VN VTN VCCO 5V 75 100 100 50 50 ADCMP572 Q ADCMP572 04409-0-030 04409-0-032 LATCH INPUTS LATCH INPUTS LATCH INPUTS Figure 19. LVDS to50 Back-Terminated (RS)PECL Receiver Figure 22. Interfacing 3.3 V CML to a 50 Ground Terminated Instrument VCCI = 3.3V VCCO = 2.5V/3.3V 2.5V/3.3V 50 VIN VTH + VCCI VCCO = 3.3V VCCO 50 Q 50 50 ADCMP572 - VP Q VN ADCMP572 VCCO 04409-0-031 GND = -1V Figure 20. Comparator with 1 V Input Range and 2.5 V or 3.3 V CML Outputs Figure 23. Disabling the Latch Feature VCCI VCCO VCCO 50 50 ADCMP572 HYS Figure 24. Adding Hysteresis Using the HYS Control Pin Rev. PrB | Page 12 of 16 04409-0-036 0 TO 5k 04409-0-035 LATCH INPUTS 750 04409-0-034 Preliminary Technical Data TIMING INFORMATION Figure 25 illustrates the ADCMP572/ADCMP573 compare and latch timing relationships. Table 4 provides definitions of the terms shown in the figure. ADCMP572/ADCMP573 LATCH ENABLE 50% LATCH ENABLE tS tH tPL DIFFERENTIAL INPUT VOLTAGE VIN VOD VN VOS tPDL Q OUTPUT tPLOH 50% tPDH tF 50% Q OUTPUT tR Figure 25. System Timing Diagram Table 4. Timing Descriptions Symbol tPDH tPDL tPLOH tPLOL tH tPL tS tR tF VOD Timing Input to output high delay Input to output low delay Latch enable to output high delay Latch enable to output low delay Minimum hold time Minimum latch enable pulse width Minimum setup time Output rise time Output fall time Voltage overdrive Description Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the latch enable signal that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the input voltages VA and VB. Rev. PrB | Page 13 of 16 04409-0-003 tPLOL ADCMP572/ADCMP573 OUTLINE DIMENSIONS 3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF * COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION 1.50 REF 9 8 Preliminary Technical Data 0.50 0.40 0.30 PIN 1 INDICATOR 16 1 0.60 MAX 13 12 BOTTOM VIEW 1.65 1.50 SQ* 1.35 5 4 0.25 MIN Figure 26. 16-Lead Lead Frame Chip Scale Package [LFCSP] (CP-16) Dimensions shown in millimeters ORDERING GUIDE Model ADCMP572BCP ADCMP573BCP Temperature Range -40C to 85C -40C to 85C Package Description LFCSP-16 LFCSP-16 Package Option CP-16 CP-16 Rev. PrB | Page 14 of 16 Preliminary Technical Data NOTES ADCMP572/ADCMP573 Rev. PrB | Page 15 of 16 ADCMP572/ADCMP573 NOTES Preliminary Technical Data (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04409-0-6/04(PrB) Rev. PrB | Page 16 of 16 |
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