View ADS5500_973926.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ADS5500
SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
14 Bit, 125MSPS Analog to Digital Converter
FEATURES D 14-Bit Resolution D 125MSPS Sample Rate D High SNR: 70.5dBFS at 100MHz fIN D High SFDR: 82dBc at 100MHz fIN D 2.3VPP Differential Input Voltage D Internal Voltage Reference D 3.3V Single-Supply Voltage D Analog Power Dissipation: 578mW D D
- Total Power Dissipation: 780mW Serial Programming Interface TQFP-64 PowerPADE Package
D Recommended Amplifiers:
OPA695, OPA847, THS3201, THS3202, THS4503, THS9001
APPLICATIONS D Wireless Communication D D D Communication Instrumentation
- Radar, Infrared - Communication Receivers - Base Station Infrastructure Test and Measurement Instrumentation Single and Multichannel Digital Receivers
D Video and Imaging D Medical Equipment
DESCRIPTION
The ADS5500 is a high-performance, 14-bit, 125MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in very little space, the ADS5500 has excellent power consumption of 780mW at 3.3V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. Parallel CMOScompatible output ensures seamless interfacing with common logic. The ADS5500 is available in a 64-pin TQFP PowerPAD package and is specified over the full temperature range of -40C to +85C.
AVDD DRVDD
CLK+ CLK- Timing Circuitry
CLKOUT
VIN+ S&H VIN-
14-Bit Pipeline ADC Core
Digital Error Correction
Output Control
D0 . . . D13 OVR DFS
CM
Internal Reference
Control Logic Serial Programming Register
ADS5500
DRGND
AGND
SEN
SDATA
SCLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003-2004, Texas Instruments Incorporated
www.ti.com
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
PACKAGE/ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD HTQFP-64(2) PowerPAD PACKAGE DESIGNATOR PAP SPECIFIED TEMPERATURE RANGE -40C to +85C PACKAGE MARKING ADS5500I ORDERING NUMBER ADS5500IPAP ADS5500IPAPR TRANSPORT MEDIA, QUANTITY Tray, 160 Tape and Reel, 1000
ADS5500
(1) For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet. (2) Thermal pad size: 3.5mm x 3.5mm (min), 4mm x 4mm (max).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) ADS5500 Supply Voltage AVDD to AGND, DRVDD to DRGND AGND to DRGND -0.3 to +3.7 0.1 -0.15 to +2.5 -0.3 to DRVDD + 0.3 -0.3 to DRVDD + 0.3 30 -40 to +85 +105 -65 to +150 UNIT V V V V V mA C C C
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Analog input to AGND Logic input to DRGND Digital data output to DRGND Input current (any input) Operating temperature range Junction temperature Storage temperature range
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supplies Analog supply voltage, AVDD Output driver supply voltage, DRVDD Analog Input Differential input range Input common-mode voltage, VCM(1) Digital Output Maximum output load Clock Input ADCLK input sample rate (sine wave) 1/tC DLL ON DLL OFF 60 10 3 50 125 80 MSPS MSPS VPP % C 1.5 10 2.3 1.6 VPP V pF 3.0 3.0 3.3 3.3 3.6 3.6 V V
MIN TYP MAX UNIT
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
Clock amplitude, sine wave, differential(2) Clock duty cycle(3)
Open free-air temperature range -40 +85 (1) Input common-mode should be connected to CM. (2) See Figure 13 for more information. (3) See Figure 12 for more information.
2
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS
Typ, min, and max values at TA = +25C, full temperature range is TMIN = -40C to tMAX = +85C, sampling rate = 125MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, -1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER Resolution Analog Inputs Differential input range Differential input impedance Differential input capacitance Total analog input common-mode current Analog input bandwidth Conversion Characteristics Maximum sample rate Data latency Internal Reference Voltages Reference bottom voltage, VREFM Reference top voltage, VREFP Reference error Common-mode voltage output, VCM Dynamic DC Characteristics and Accuracy No missing codes Differential linearity error, DNL Integral linearity error, INL Offset error Offset temperature coefficient Gain error Gain temperature coefficient Dynamic AC Characteristics fIN = 10MHz fIN = 30MHz fIN = 55MHz Signal-to-noise ratio, SNR fIN = 70MHz fIN = 100MHz fIN = 150MHz RMS Output noise fIN = 225MHz Input tied to common-mode fIN = 10MHz fIN = 30MHz fIN = 55MHz Spurious-free dynamic range, SFDR fIN = 70MHz fIN = 100MHz fIN = 150MHz fIN = 225MHz (1) 2mA per input. (2) See Reccommended Operating Conditions on page 2. Room temp Full temp range 80 77 Room temp Full temp range 82 78 Room temp Full temp range 70 68.5 Room temp Full temp range 70.5 69 71.5 71.5 71.5 71.5 71.2 71 70.5 70.1 69.1 1.1 84 84 84 79 83 82 82 78 74 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS LSB dBc dBc dBc dBc dBc dBc dBc dBc dBc fIN = 10MHz fIN = 10MHz -0.9 -5 Tested 0.75 2.5 1.5 0.0007 0.45 0.01 +1.1 +5 LSB LSB mV %/C %FS %/C -4 0.97 2.11 0.9 1.55 0.05 +4 V V % V See timing diagram, Figure 1 see note (2) 16.5 125 MSPS Clock Cycles Source impedance = 50 See Figure 4 See Figure 4 2.3 6.6 4
4(1)
CONDITIONS
MIN
TYP 14 Tested
MAX
UNIT Bits VPP k pF mA MHz
750
3
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (continued)
Typ, min, and max values at TA = +25C, full temperature range is TMIN = -40C to tMAX = +85C, sampling rate = 125MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, -1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER CONDITIONS fIN = 10MHz fIN = 30MHz fIN = 55MHz Second-harmonic, HD2 fIN = 70MHz fIN = 100MHz fIN = 150MHz fIN = 225MHz fIN = 10MHz fIN = 30MHz fIN = 55MHz Third-harmonic, HD3 fIN = 70MHz fIN = 100MHz fIN = 150MHz Worst-harmonic/spur (other than HD2 and HD3) fIN = 225MHz fIN = 10MHz Room temp fIN = 70MHz fIN = 10MHz fIN = 30MHz fIN = 55MHz Signal-to-noise + distortion, SINAD fIN = 70MHz fIN = 100MHz fIN = 150MHz fIN = 225MHz fIN = 10MHz fIN = 30MHz fIN = 55MHz Total harmonic distortion, THD fIN = 70MHz fIN = 100MHz fIN = 150MHz fIN = 225MHz Room temp Full temp range 77.5 76 Room temp Full temp range 80 78 Room temp Full temp range 68.5 67 Room temp Room temp Full temp range 69 67.5 Room temp Full temp range 80 77 Room temp Full temp range 82 78 Room temp Full temp range 80 77 Room temp Full temp range MIN 82 78 TYP 91 86 86 84 87 83 84 78 74 89 88 90 79 85 82 82 80 76 88 86 70 70 70 69.5 69 69.5 69 69 66.4 85 83 82 77 81 79.5 79 75 71.8 MAX UNIT dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
4
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (continued)
Typ, min, and max values at TA = +25C, full temperature range is TMIN = -40C to tMAX = +85C, sampling rate = 125MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, -1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER Effective number of bits, ENOB CONDITIONS fIN = 70MHz f = 10.1MHz, 15.1MHz (-7dBFS each tone) f = 30.1MHz, 35.1MHz (-7dBFS each tone) f = 50.1MHz, 55.1MHz (-7dBFS each tone) Power Supply Total supply current, ICC Analog supply current, IAVDD Output buffer supply current, IDRVDD VIN = full-scale, fIN = 55MHz AVDD = DRVDD = 3.3V VIN = full-scale, fIN = 55MHz AVDD = DRVDD = 3.3V VIN = full-scale, fIN = 55MHz AVDD = DRVDD = 3.3V Analog only Total power with 10pF load on digital output to ground With clocks running 236 175 61 578 780 181 265 190 75 627 875 250 mA mA mA mW mW mW MIN TYP 11.3 85 85 88 MAX UNIT Bits dBc dBc dBc
Two-tone intermodulation distortion, IMD
Power dissipation Standby power
DIGITAL CHARACTERISTICS
Typ, min, and max values at TA = +25C, full temperature range is TMIN = -40C to tMAX = +85C, sampling rate = 125MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, -1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER Digital Inputs High-level input voltage Low-level input voltage High-level input current Low-level input current Input current for RESET Input capacitance Digital Outputs(1) Low-level output voltage High-level output voltage Output capacitance CLOAD = 10pF(2), fS = 125MSPS CLOAD = 10pF(2), fS = 125MSPS -20 4 0.3 3.0 3 2.4 0.8 10 10 V V A A A pF V V pF CONDITIONS MIN TYP MAX UNIT
(1) For optimal performance, all digital output lines (D0:D13), including the output clock, should see a similar load. (2) Equivalent capacitance to ground of (load + parasitics of transmission lines).
5
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
TIMING CHARACTERISTCS
N+2 N+3 N+4 N + 16 N + 17 tPDI
Analog Input Signal
Sample N
N+1
N + 15 tA
Input Clock t SETUP
Output Clock N - 17 Data Out (D0- D13) N - 16 N - 15 N - 13 N-3 N-2 N-1 N
tHOLD
16.5 Clock Cycles
Data Invalid
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing matches closely with the specified values.
Figure 1. Timing Diagram
TIMING CHARACTERISTICS
Typ, min, and max values at TA = +25C, full temperature range is TMIN = -40C to tMAX = +85C, sampling rate = 125MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, -1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER Switching Specification Aperture delay, tA Aperture jitter (uncertainty) Data setup time, tSETUP Data hold time, tHOLD Data latency, tD(Pipe) Propagation delay, tPDI Data rise time Data fall time Output enable (OE) to output stable delay Input CLK falling edge to data sampling point Uncertainty in sampling instant Data valid to 50% of CLKOUT rising edge CLKOUT rising edge to data becoming invalid Input clock falling edge (on which sampling takes place) to input clock rising edge (on which the corresponding data is given out) Input clock rising edge to data valid Data out 20% to 80% Data out 80% to 20% 1 300 2 1.7 16.5 7.5 2.5 2.5 2 ns fs ns ns Clock Cycles ns ns ns ms DESCRIPTION MIN TYP MAX UNIT
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The device has a three-wire serial interface. The device latches the serial data SDATA on the falling edge of serial clock SCLK when SEN is active.
D Data is loaded at every 16th SCLK falling edge
while SEN is low.
D Serial shift of bits is enabled when SEN is low.
SCLK shifts serial data at falling edge.
D In case the word length exceeds a multiple of 16
bits, the excess bits are ignored.
D Minimum width of data stream for a valid loading is
16 clocks.
D Data can be loaded in multiple of 16-bit words within
a single active SEN pulse.
6
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
SDATA
A3
A2
A1
A0
D11
D10
D9 DATA
D0
ADDRESS MSB
Figure 2. DATA Communication is 2-Byte, MSB First
tSLOADS SEN tWSCLK tWSCLK tSCLK
tSLOADH
SCLK t OS SDATA t OH
MSB
LSB 16 x M
MSB
LSB
Figure 3. Serial Programming Interface Timing Diagram Table 1. Serial Programming Interface Timing Characteristics
SYMBOL tSCLK tWSCLK tSLOADS tSLOADH tDS tDH PARAMETER SCLK Period SCLK Duty Cycle SEN to SCLK setup time SCLK to SEN hold time Data Setup Time Data Hold Time MIN(1) 50 25 8 6 8 6 50 75 TYP(1) MAX(1) UNIT ns % ns ns ns ns
(1) Min, typ, and max values are characterized, but not production tested.
Table 2. Serial Register Table
A3 1 A2 1 A1 0 A0 1 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 DLL OFF D0 0 DESCRIPTION DLL OFF = 0 : internal DLL is on, recommended for 60-125MSPS clock speed DLL OFF = 1 : internal DLL is off, recommended for 10-80MSPS clock speed TP<1:0> - Test modes for output data capture TP<1> = 0, TP<0> = 0 : Normal mode of operation, TP<1> = 0 TP<0> = 1 : All output lines are pulled to '0', TP<1> = 1 TP<0> = 0 : All output lines are pulled to '1', TP<1> = 1 TP<0> = 1 : A continuous stream of '10' comes out on all output lines PDN = 0 : Normal mode of operation, PDN = 1 : Device is put in power down (low current) mode
1
1
1
0
0
TP<1>
TP<0>
0
0
0
0
0
0
0
0
0
1
1
1
1
PDN
0
0
0
0
0
0
0
0
0
0
0
7
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
Table 3. DATA FORMAT SELECT (DFS TABLE)
DFS-PIN VOLTAGE (VDFS)
V DFS t 5 12 2 3 1 6 AV DD AV DD AV DD
DATA FORMAT Straight Binary Two's Complement Straight Binary Two's Complement
CLOCK OUTPUT POLARITY Data valid on rising edge Data valid on rising edge Data valid on falling edge Data valid on falling edge
1 AV DD u V DFS u 3 7 AV DD u V DFS u 12 V DFS u 5 6 AV DD
PIN CONFIGURATION
PAP PACKAGE (TOP VIEW)
D13 (MSB) DRVDD DRVDD 49 48 DRGND 47 D3 46 D2 45 D1 44 D0 (LSB) 43 CLKOUT 42 DRGND 41 OE 40 DFS 39 AVDD 38 AGND 37 AVDD 36 AGND 35 RESET 34 AVDD 33 AVDD 17 CM 18 AGND 19 INP 20 INM 21 AGND 22 AVDD 23 AGND 24 AVDD 25 AGND 26 AVDD 27 AGND 28 AVDD 29 REFP 30 REFM 31 IREF 32 AGND DRGND DRGND DRGND 50 OVR D12 D11 D10
D9
D8
D7
D6
D5 52
64 DRGND SCLK SDATA SEN AVDD AGND AVDD AGND AVDD 1 2 3 4 5 6 7 8 9
63
62
61
60
59
58
57
56
55
54
53
51
ADS5500 PowerPAD
(Connected to Analog Ground)
CLKP 10 CLKM 11 AGND 12 AGND 13 AGND 14 AVDD 15 AGND 16
8
D4
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
PIN ASSIGNMENTS
TERMINAL NAME AVDD AGND DRVDD DRGND INP INM REFP REFM IREF CM RESET OE DFS CLKP CLKM SEN SDATA SCLK D0 (LSB)-D13 (MSB) OVR CLKOUT NO. 5, 7, 9, 15, 22, 24, 26, 28, 33, 34, 37, 39 6, 8, 12, 13, 14, 16, 18, 21, 23, 25, 27, 32, 36, 38 49, 58 1, 42, 48, 50, 57, 59 19 20 29 30 31 17 35 41 40 10 11 4 3 2 44-47, 51-56, 60-63 64 43 NO. OF PINS 12 14 2 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 14 1 1 I/O I I I I I I O O I O I I I I I I I I O O O Analog power supply Analog ground Output driver power supply Output driver ground Differential analog input (positive) Differential analog input (negative) Reference voltage (positive); 0.1F capacitor in series with a 1 resistor to GND Reference voltage (negative); 0.1F capacitor in series with a 1 resistor to GND Current set; 56k resistor to GND; do not connect capacitors Common-mode output voltage Reset (active high), 200k resistor to AVDD Output enable (active high) Data format and clock out polarity select(1) Data converter differential input clock (positive) Data converter differential input clock (negative) Serial interface chip select Serial interface data Serial interface clock Parallel data output Over-range indicator bit CMOS clock out in sync with data DESCRIPTION
NOTE: PowerPAD is connected to analog ground. (1) The DFS pin is programmable to four discrete voltage levels: 0, 3/8 AVDD, 5/8 AVDD, and AVDD. The thresholds are centered. More details are listed in Table 3 on page 8.
9
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3dB. Aperture Delay The delay in time between the falling edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle A perfect differential sine wave clock results in a 50% clock duty cycle on the internal coversion clock. Pulse width high is the minimum amount of time that the ENCODE pulse should be left in logic `1' state to achieve rated performance. Pulse width low is the minimum time that the ENCODE pulse should be left in a low state (logic `0'). At a given clock rate, these specifications define an acceptable clock duty cycle. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation of any single LSB transition at the digital output from an ideal 1 LSB step at the analog input. If a device claims to have no missing codes, it means that all possible codes (for a 14-bit converter, 16384 codes) are present over the full operating range. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula: Integral Nonlinearity (INL) INL is the deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" or "best fit" determined by a least square curve fit. INL is independent from effects of offset, gain or quantization errors. Maximum Conversion Rate The encode rate at which parametric testing is performed. This is the maximum sampling rate where certified operation is given. Minimum Conversion Rate This is the minimum sampling rate where the ADC still works. Nyquist Sampling When the sampled frequencies of the analog input signal are below fCLOCK/2, it is called Nyquist sampling. The Nyquist frequency is fCLOCK/2, which can vary depending on the sample rate (fCLOCK). Offset Error
Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode.
Propagation Delay This is the delay between the input clock rising edge and the time when all data bits are within valid logic levels. Signal-to-Noise and Distortion (SINAD) The RMS value of the sine wave fIN (input sine wave for an ADC) to the RMS value of the noise of the converter from DC to the Nyquist frequency, including harmonic content. It is typically expressed in decibels (dB). SINAD includes harmonics, but excludes DC.
ENOB + SINAD * 1.76 6.02
If SINAD is not known, SNR can be used exceptionally to calculate ENOB (ENOBSNR). Effective Resolution Bandwidth
SINAD + 20Log (10)
Input(VS ) Noise ) Harmonics
The highest input frequency where the SNR (dB) is dropped by 3dB for a full-scale input amplitude.
Gain Error The amount of deviation between the ideal transfer function and the measured transfer function (with the offset error removed) when a full-scale analog input voltage is applied to the ADC, resulting in all 1s in the digital code. Gain error is usually given in LSB or as a percent of full-scale range (%FSR).
10
Signal-to-Noise Ratio (without harmonics) SNR is a measure of signal strength relative to background noise. The ratio is usually measured in dB. If the incoming signal strength in V is VS, and the noise level (also in V) is VN, then the SNR in dB is given by the formula:
SNR + 20Log (10)
VS VN
This is the ratio of the RMS signal amplitude, VS (set 1dB below full-scale), to the RMS value of the sum of all other spectral components, VN, excluding harmonics and DC.
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
Spurious-Free Dynamic Range (SFDR) The ratio of the RMS value of the analog input sine wave to the RMS value of the peak spur observed in the frequency domain. It may be reported in dBc (that is, it degrades as signal levels are lowered), or in dBFS (always related back to converter full-scale). The peak spurious component may or may not be a harmonic. Temperature Drift Temperature drift (for offset error and gain error) specifies the maximum change from the initial temperature value to the value at TMIN or TMAX.
Total Harmonic Distortion (THD) THD is the ratio of the RMS signal amplitude of the input sine wave to the RMS value of distortion appearing at multiples (harmonics) of the input, typically given in dBc. Two-Tone Intermodulation Distortion Rejection The ratio of the RMS value of either input tone (f1, f2) to the RMS value of the worst third-order intermodulation product (2f1 - f2; 2f2 - f1). It is reported in dBc.
11
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS
Typical values are at TA = 25C, AVDD = DRVDD = 3.3V, differential input amplitude = -1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted.
SPECTRAL PERFORMANCE (FFT for 2MHz Input Signal) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 10 20 30 Frequency (MHz) SFDR = 84.0dBc SNR = 71.2dBFS THD = 84.0dBc SINAD = 71.0dBFS Amplitude (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 10
SPECTRAL PERFORMANCE (FFT for 15MHz Input Signal) SFDR = 84.8dBc SNR = 71.5dBFS THD = 83.2dBc SINAD = 71.2dBFS
Amplitude (dB)
62.5
62.5
40
50
60
20
30
40
50
60
Frequency (MHz)
SPECTRAL PERFORMANCE (FFT for 60MHz Input Signal) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 SFDR = 81.0dBc SNR = 71.2dBFS THD = 80.2dBc SINAD = 70.7dBFS 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0
SPECTRAL PERFORMANCE (FFT for 70MHz Input Signal) SFDR = 85.1dBc SNR = 71.4dBFS THD = 83.6dBc SINAD = 71.1dBFS
Amplitude (dB)
Amplitude (dB) 62.5
62.5
10
20
30
40
50
60
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
SPECTRAL PERFORMANCE (FFT for 80MHz Input Signal) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 SFDR = 84.4dBc SNR = 71.2dBFS THD = 81.3dBc SINAD = 70.9dBFS 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0
SPECTRAL PERFORMANCE (FFT for 100MHz Input Signal) SFDR = 84.3dBc SNR = 71.1dBFS THD = 81.6dBc SINAD = 70.7dBFS
Amplitude (dB)
Amplitude (dB) 62.5
62.5
10
20
30
40
50
60
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
12
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25C, AVDD = DRVDD = 3.3V, differential input amplitude = -1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted.
SPECTRAL PERFORMANCE (FFT for 150MHz Input Signal) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 SFDR = 77.8dBc SNR = 70.0dBFS THD = 75.3dBc SINAD = 69.0dBFS 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0
SPECTRAL PERFORMANCE (FFT for 225MHz Input Signal) SFDR = 73.0dBc SNR = 69.1dBFS THD = 70.0dBc SINAD = 66.5dBFS
Amplitude (dB)
Amplitude (dB) 62.5
62.5
10
20
30
40
50
60
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
SPECTRAL PERFORMANCE (FFT for 300MHz Input Signal) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 0 SFDR = 67.4dBc SNR = 68.0dBFS THD = 64.7dBc SINAD = 63.0dBFS Power (dBFS) -20 -40 -60 -80 -100 -120 -140
TWO-TONE INTERMODULATION f1 = 10.1MHz, -7dBFS f2 = 15.1MHz, -7dBFS 2-tone IMD = 88.0dBc
Amplitude (dB)
62.5
62.5
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
TWO-TONE INTERMODULATION 0 - 20 - 40 - 60 - 80 -100 -120 -140 62.5 0 10 20 30 40 50 60 Frequency (MHz) Power (dBFS) Power (dBFS) f1 = 30.1MHz, -7dBFS f2 = 35.1MHz, -7dBFS 2-tone IMD = 87.0dBc 0 -20 -40 -60 -80 -100 -120 -140
TWO-TONE INTERMODULATION f 1 = 50.1MHz, -7dBFS f 2 = 55.1MHz, -7dBFS 2-tone IMD = 89.0dBc
62.5
0
10
20
30
40
50
60
Frequency (MHz)
13
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25C, AVDD = DRVDD = 3.3V, differential input amplitude = -1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted.
DIFFERENTIAL NONLINEARITY (DNL) 1.50 1.25 1.00 0.75 0.50 0.25 LSB 0 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 2048 4096 6144 8192 10240 0 f S = 125MSPS f IN = 10MHz AIN = -0.5dBFS 12288 14336 16384 LSB 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 2048
INTEGRAL NONLINEARITY (INL)
f S = 125MSPS f IN = 10MHz AIN = -0.5dBFS 4096 6144 8192 10240 12288 14336 250 3.5 16384 300 3.6 0
Code
Code
SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY 90 85 80 SNR (dBFS) SFDR (dBc) 75 70 65 60 55 50 0 50 100 150 200 250 300 Input Frequency (MHz) f S = 125MSPS DLL On 76 74 72 70 68 66 64 62 60 0
SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY
f S = 125MSPS DLL On 50 100 150 200
Input Frequency (MHz)
AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE 90 85 80 75 SNR 70 65 60 3.0 3.1 3.2 3.3 AVDD (V) 3.4 3.5 3.6 fS = 125MSPS fIN = 150MHz DRVDD = 3.3V 90 85 80 75
AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE
SFDR
SNR (dBFS) SFDR (dBc)
SFDR
SNR (dBFS) SFDR (dBc)
SNR 70 65 60 3.0 3.1 3.2 3.3 AVDD (V) 3.4 fS = 125MSPS fIN = 70MHz DRVDD = 3.3V
14
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25C, AVDD = DRVDD = 3.3V, differential input amplitude = -1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted.
AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE 79 78 77 76 SNR (dBFS) SFDR (dBc) 75 74 73 72 71 70 69 3.0 3.1 3.2 3.3 DRVDD (V) 3.4 3.5 3.6 72 SNR 70 3.0 fS = 125MSPS fIN = 150MHz AVDD = 3.3V SNR (dBFS) SFDR (dBc) 80 78 76 74 SFDR 84 82
AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE
SFDR
fS = 125MSPS fIN = 70MHz AVDD = 3.3V
SNR
3.1
3.2
3.3 DRVDD (V)
3.4
3.5
3.6
POWER DISSIPATION vs SAMPLE RATE 850 800 Power Dissipation (mW) 750 700 650 600 550 500 10 30 50 70 90 110 130 150 Sample Rate (MSPS) AVDD = DRVDD = 3.3V fIN = 150MHz Power Dissipation (mW) 800
POWER DISSIPATION vs SAMPLING FREQUENCY f IN = 70MHz 750 DLL On 700 650 DLL Off 600 550 500 125 10 20 30 40 50 60 70 80 90 100 110 120 Sampling Frequency (MSPS)
SIGNAL-TO-NOISE RATIO AND SPURIOUS-FREE DYNAMIC RANGE vs TEMPERATURE 90 85 SFDR SNR (dBFS) SFDR (dBc) 80 75 SNR 70 65 60 -40 0 25 Temperature (_C) 40 85 fS = 125MSPS fIN = 70MHz DLL On AC Performance (dB)
AC PERFORMANCE vs INPUT AMPLITUDE 90 80 70 60 50 40 30 20 10 0 -10 -20 fS = 125MSPS fIN = 70MHz DLL On 0 SNR (dBc) SFDR (dBc) SNR (dBFS)
-30 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Input Amplitude (dBFS)
15
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25C, AVDD = DRVDD = 3.3V, differential input amplitude = -1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted.
AC PERFORMANCE vs INPUT AMPLITUDE 90 80 70 AC Performance (dB) 50 40 30 20 10 0 -10 -20 fS = 125MSPS fIN = 150MHz DLL On 0 SNR (dBc) SFDR (dBc) AC Performance (dB) 60 SNR (dBFS) 90 80 70 60 50 40 30 20 10 0 -10 -20 -30 -90
AC PERFORMANCE vs INPUT AMPLITUDE SNR (dBFS)
SFDR (dBc) SNR (dBc)
-30 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Input Amplitude (dBFS)
f S = 125MSPS f IN = 220MHz DLL On -80 -70 -60 -50 -40 -30 -20 -10 0
Input Amplitude (dBFS)
OUTPUT NOISE HISTOGRAM 40 35 30 Occurrence (%) SNR (dBFS) SFDR (dBc) 25 20 15 10 5 0 8209 8210 8211 8212 8213 8214 8215 8216 8217 8218 8219 8220 8221 8222 90 85 80 75 70 65 60 55 50 0
AC PERFORMANCE vs CLOCK AMPLITUDE SFDR
SNR
fS = 125MSPS fIN = 70MHz 0.5 1.0 1.5 2.0 2.5 3.0
Differential Clock Amplitude (V)
Output Code
WCDMA TONE 0 -20 -40 -60 -80 -100 -120 -140 0 10 20 30 40 50 60 Frequency (MHz) fS = 150MSPS fIN = 125MHz
16
Amplitude (dB)
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25C, AVDD = DRVDD = 3.3V, differential input amplitude = -1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted.
SIGNAL-TO-NOISE RATIO (SNR) WITH DLL ON
150 73
71
140 130 120 Sample Frequency (MSPS) 110 100 90 80 70 60 50 40 0 50
71 69 71
71 72
72 70
69
70
69 72 73 73 72 71 72
100 150 Input Frequency (MHz)
69
71 69 70 70
68 68
68
69 69
200
67
68
250
67
300
66
SIGNAL-TO-NOISE RATIO (SNR) WITH DLL OFF
80
71 73
70
70
69
72
73
60 Sample Frequency (MSPS)
72
70
71
40
67
66
72 73
30
73 70 71 69 68
100 150 Input Frequency (MHz)
69
68 67 66 65 66 64 63 62
200 250 300
64
20
71 72
62
67
10 0 50
60
SNR (dB)
50
69 70
68
68
SNR (dB)
17
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25C, AVDD = DRVDD = 3.3V, differential input amplitude = -1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted.
SPURIOUS-FREE DYNAMIC RANGE (SFDR) WITH DLL ON
150
83
140
77 80 80 71 68
85
130 120 Sample Frequency (MSPS) 110
83 86 86
83
83 77
77
74
80
100
80
90 86 80 70 60 50
71 68
75
83 89 86 86 83
77
74
89
80 83 77 74
70
71
68
40 0 50 100 150 Input Frequency (MHz) 200 250 300
65
SPURIOUS-FREE DYNAMIC RANGE (SFDR) WITH DLL OFF
80 88
88
70
78 80 84 84 86 88 86 72 82 76 74
70
86 84 82 80
88 86
60 Sample Frequency (MSPS)
80
40
78
70
68
78 76
86 86 82 76 74
74 30
84 88
20
72 86 84 82 80 78 76 74
100 150 Input Frequency (MHz)
72
70
70
68
68
72
70
66 200 250 300
10 0 50
18
SFDR (dBc)
50
SFDR (dBc)
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25C, AVDD = DRVDD = 3.3V, differential input amplitude = -1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted.
SECOND HARMONIC (HD2) WITH DLL ON
150
95
140
86 86
83 86 89 86 92 92 89 89 86 86 95 92 89 86 83 98 89 92 92 95
50 100 150 Input Frequency (MHz)
83
77 80 71 74
68
95
98 89
130 120 Sample Frequency (MSPS) 110 100 90 80
86
92 89 80 83 86 77
90
80 77
98 89 95 92
74
80
89
83 86 77 74 71
68
75
70 60
98 95
50
83 68 89 86
200
70
98 95
92
40 0
80
77
250
74
71
65 300
SECOND HARMONIC (HD2) WITH DLL OFF
80
93
70
90 87 84 93 96 99
81
68
95
96
60 Sample Frequency (MSPS)
78 99 87 99 93 99 99 99 93 96 90 78 75 87 84 81 78 87 84 75
100 150 Input Frequency (MHz) 200 250 300
90
75
72 68
85
40
80
72
75
30
68 72
70
20
10 0 50
HD2 (dBc)
50
84
81
HD2 (dBc)
92
71
85
19
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25C, AVDD = DRVDD = 3.3V, differential input amplitude = -1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted.
THIRD HARMONIC (HD3) WITH DLL ON
150 140
83
80
77 89 74 86
71
68
90
86
130 120 110
86 89 86
83
85
86 83 80 77 77 74 77 80 86 89 89 86
75 80 HD3 (dBc) HD3 (dBc)
71
100 90 80 70 60 50 40 0
83
83
92 86 86 83 83 89
65 50 100 150 Input Frequency (MHz) 200 250 300
86
70
92
89
86
THIRD HARMONIC (HD3) WITH DLL OFF
80
87 90
90
90
87 84
81
78
70
84 78
85
60 Sample Frequency (MSPS)
84 87 75 72 84 81 78
80
50
40
87
75
30
87 84 90 84 81 84 87
0 50 100 150 Input Frequency (MHz)
75 81 78 72
200 250
72
20
70
75
72
300
10
20
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
APPLICATION INFORMATION THEORY OF OPERATION
The ADS5500 is a low-power, 14-bit, 125MSPS, CMOS, switched capacitor, pipeline ADC that operates from a single 3.3V supply. The conversion process is initiated by a falling edge of the external input clock. Once the signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in a data latency of 16.5 clock cycles, after which the output data is available as a 14-bit parallel word, coded in either straight offset binary or binary two's complement format.
INPUT CONFIGURATION
The analog input for the ADS5500 consists of a differential sample-and-hold architecture implemented using a switched capacitor technique, shown in Figure 4.
SAMPLE PHASE L1 W1a R1a
SAMPLE W 3a PHASE C1a
INP
CP1 CACROSS SAMPLE W2 PHASE SWITCH CP3 R3 SWITCH
L2
R1b
C1b
SWITCH
INM
CP2 W1b SAMPLE PHASE L1, L2 : 6nh to 10nh effective R1a, R1b : 25 to 35 C1a, C1b : 2.2pF to 2.6pF CP1, CP2 : 2.5pF to 3.5pF CP3, CP4, : 1.2pF to 1.8pF CACROSS : 0.8pF to 1.2pF R3 : 80 to 120 Switches: W1a, W1b : On Resistance: 25to 35 W2 : On Resistance: 7.5 to 15 W3a, W3b : On Resistance: 40to 60 W1a, W1b, W2, W3a, W3b : Off Resistance: 1e10 All switches are on in sample phase. Approximately half of every clock period is a sample phase. SAMPLE W 3a PHASE SWITCH CP4
VINCM 1V
Figure 4. Analog Input Stage
21
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
This differential input topology produces a high level of AC performance for high sampling rates. It also results in a very high usable input bandwidth, especially important for high intermediate-frequency (IF) or undersampling applications. The ADS5500 requires each of the analog inputs (INP, INM) to be externally biased around the common-mode level of the internal circuitry (CM, pin 17). For a full-scale differential input, each of the differential lines of the input signal (pins 19 and 20) swings symmetrically between CM + 0.575V and CM - 0.575V. This means that each input is driven with a signal of up to CM 0.575V, so that each input has a maximum differential signal of 1.15VPP for a total differential input signal swing of 2.3VPP. The maximum swing is determined by the two reference voltages, the top reference (REFP, pin 29), and the bottom reference (REFM, pin 30). The ADS5500 obtains optimum performance when the analog inputs are driven differentially. The circuit shown in Figure 5 shows one possible configuration using an RF transformer.
4mA f s 125MSPS Where: fS > 60MSPS.
(1)
This equation helps to design the output capability and impedance of the driving circuit accordingly. When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combine single-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifier without a transformer, to drive the input of the ADS5500. TI offers a wide selection of single-ended operational amplifiers (including the THS3201, THS3202, OPA847, and OPA695) that can be selected depending on the application. An RF gain block amplifier, such as TI's THS9001, can also be used with an RF transformer for very high input frequency applications. The THS4503 is a recommended differential input/output amplifier. Table 4 lists the recommended amplifiers. When using single-ended operational amplifiers (such as the THS3201, THS3202, OPA847, or OPA695) to provide gain, a three-amplifier circuit is recommended with one amplifier driving the primary of an RF transformer and one amplifier in each of the legs of the secondary driving the two differential inputs of the ADS5500. These three amplifier circuits minimize even-order harmonics. For very high frequency inputs, an RF gain block amplifier can be used to drive a transformer primary; in this case, the transformer secondary connections can drive the input of the ADS5500 directly, as shown in Figure 5, or with the addition of the filter circuit shown in Figure 6. Figure 6 illustrates how RIN and CIN can be placed to isolate the signal source from the switching inputs of the ADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommended that these components be included in the ADS5500 circuit layout when any of the amplifier circuits discussed previously are used. The components allow fine-tuning of the circuit performance. Any mismatch between the differential lines of the ADS5500 input produces a degradation in performance at high input frequencies, mainly characterized by an increase in the even-order harmonics. In this case, special care should be taken to keep as much electrical symmetry as possible between both inputs. Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers that can simplify the driver circuit for applications requiring DC coupling of the input. Flexible in their configurations (see Figure 7), such amplifiers can be used for singleended-to-differential conversion, signal amplification.
R0 50
Z0 50 1:1 INP R 50
AC Signal Source ADT1- 1WT
ADS5500 INM 10 CM
1nF
0.1F
Figure 5. Transformer Input to Convert Single-Ended Signal to Differential Signal The single-ended signal is fed to the primary winding of an RF transformer. Since the input signal must be biased around the common-mode voltage of the internal circuitry, the common-mode voltage (VCM) from the ADS5500 is connected to the center-tap of the secondary winding. To ensure a steady low-noise VCM reference, best performance is obtained when the CM (pin 17) output is filtered to ground with 0.1F and 0.01F low-inductance capacitors. Output VCM (pin 17) is designed to directly drive the ADC input. When providing a custom CM level, be aware that the input structure of the ADC sinks a common-mode current in the order of 4mA (2mA per input). Equation (1) describes the dependency of the common-mode current and the sampling frequency:
22
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
Table 4. Recommended Amplifiers to Drive the Input of the ADS5500
INPUT SIGNAL FREQUENCY DC to 20MHz DC to 50MHz RECOMMENDED AMPLIFIER THS4503 OPA847 OPA695 10MHz to 120MHz THS3201 THS3202 Over 100MHz THS9001 TYPE OF AMPLIFIER Differential In/Out Amp Operational Amp Operational Amp Operational Amp Operational Amp RF Gain Block USE WITH TRANSFORMER? No Yes Yes Yes Yes Yes
+5V -5V RS 100 OPA695 1000pF R1 400 AV = 8V/V (18dB)
VIN
0.1F
1:1 RT 100
RIN INP RIN CIN INM CM ADS5500
R2 57.5
10
0.1F
Figure 6. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
RS
RG +5V
RF
RT
+3.3V 10F 0.1F R IN INP VOCM 1F THS4503 10F 0.1F 10 RG -5V RF R IN INM CM ADS5500 14- Bit/125MSPS
0.1F
Figure 7. Using the THS4503 with the ADS5500
23
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
POWER SUPPLY SEQUENCE
The ADS5500 requires a power-up sequence where the DRVDD supply must be at least 0.4V by the time the AVDD supply reaches 3.0V. Powering up both supplies at the same time will work without any problem. If this sequence is not followed, the device may stay in power-down mode.
CLOCK INPUT
The ADS5500 clock input can be driven with either a differential clock signal or a single-ended clock input, with little or no difference in performance between both configurations. The common-mode voltage of the clock inputs is set internally to CM (pin 17) using internal 5k resistors that connect CLKP (pin 10) and CLKM (pin 11) to CM (pin 17), as shown in Figure 9.
POWER DOWN
The device will enter power-down in one of two ways: either by reducing the clock speed to between DC and 1MHz, or by setting a bit through the serial programming interface. Using the reduced clock speed, the power-down may be initiated for clock frequencies below 10MHz. For clock frequencies between 1MHz and 10Mhz, this can vary from device to device, but will power-down for clock speeds below 1MHz. The device can be powered down by programming the internal register (see Serial Programming Interface section). The outputs become tri-stated and only the internal reference is powered up to shorten the power-up time. The Power-Down mode reduces power dissipation to a minimum of 180mW.
CM CM
5k
5k
CLKP
CLKM
6pF 3pF 3pF
REFERENCE CIRCUIT
The ADS5500 has built-in internal reference generation, requiring no external circuitry on the printed circuit board (PCB). For optimum performance, it is best to connect both REFP and REFM to ground with a 1F decoupling capacitor in series with a 1 resistor, as shown in Figure 8. In addition, an external 56.2k resistor should be connected from IREF (pin 31) to AGND to set the proper current for the operation of the ADC, as shown in Figure 8. No capacitor should be connected between pin 31 and ground; only the 56.2k resistor should be used. Figure 9. Clock Inputs When driven with a single-ended CMOS clock input, it is best to connect CLKM (pin 11) to ground with a 0.01F capacitor, while CLKP is AC-coupled with a 0.01F capacitor to the clock source, as shown in Figure 10.
Square Wave or Sine Wave (3VPP)
0.01F CLKP ADS5500 CLKM
1 29 1F 1 30 1F 31 56k IREF REFM REFP
0.01F
Figure 10. AC-Coupled, Single-Ended Clock Input The ADS5500 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with 0.01F capacitors, as shown in Figure 11.
Figure 8. REFP, REFM, and IREF Connections for Optimum Performance
24
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
0.01F CLKP Differential Square Wave or Sine Wave (3VPP) ADS5500 0.01F CLKM
amplitudes without exceeding the supply rails and absolute maximum ratings of the ADC clock input. Figure 13 shows the performance variation of the device versus input clock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, refer to the ADS5500EVM User's Guide (SLWU010), available for download from www.ti.com.
Figure 11. AC-Coupled, Differential Clock Input
90
AC PERFORMANCE vs CLOCK AMPLITUDE SFDR
For high input frequency sampling, it is recommended to use a clock source with very low jitter. Additionally, the internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% duty cycle should be provided. Figure 12 shows the performance variation of the ADC versus clock duty cycle.
85 80 SNR (dBFS) SFDR (dBc) 75 70 65 60 55
SNR
fS = 125MSPS fIN = 70MHz 0 0.5 1.0 1.5 2.0 2.5 3.0
90 85 80 75
fS = 125MSPS fIN = 20MHz
50 SFDR Differential Clock Amplitude (V)
SNR (dBFS) SFDR (dBc)
Figure 13. AC Performance vs Clock Amplitude
SNR
70 65 60 30 35 40 45 50 55 60 65 70 Clock Duty Cycle (%)
INTERNAL DLL
In order to obtain the fastest sampling rates achievable with the ADS5500, the device uses an internal digital phase lock loop (DLL). Nevertheless, the limited frequency range of operation of DLL degrades the performance at clock frequencies below 60MSPS. In order to operate the device below 60MSPS, the internal DLL must be shut off using the DLL OFF mode described in the Serial Interface Programming section. The Typical Performance Curves show the performance obtained in both modes of operation: DLL ON (default), and DLL OFF. In either of the two modes, the device will enter power down mode if no clock or slow clock is provided. The limit of the clock frequency where the device will function properly is ensured to be over 10MHz.
Figure 12. AC Performance vs Clock Duty Cycle Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. When using a sinusoidal clock, the clock jitter will further improve as the amplitude is increased. In that sense, using a differential clock allows for the use of larger
25
ADS5500
www.ti.com SBAS303C - DECEMBER 2003 - REVISED MARCH 2004
OUTPUT INFORMATION
The ADC provides 14 data outputs (D13 to D0, with D13 being the MSB and D0 the LSB), a data-ready signal (CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals 1 when the output reaches the full-scale limits. Two different output formats (straight offset binary or two's complement) and two different output clock polarities (latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to one of four different voltages. Table 3 details the four modes. In addition, output enable control (OE, pin 41, active high) is provided to tri-state the outputs. The output circuitry of the ADS5500 has being designed to minimize the noise produced by the transients of the data switching, and in particular its coupling to the ADC analog circuitry. Output D4 (pin 51) senses the load capacitance and adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in the timing diagram of Figure 1, as long as all outputs (including CLKOUT) have a similar load as the one at D4 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply voltage or temperature. External series resistors with the output are not necessary.
SERIAL PROGRAMMING INTERFACE
The ADS5500 has internal registers for the programming of some of the modes described in the previous sections. The registers should be reset after power-up by applying a 2s (minimum) high pulse on RESET (pin 35); this also resets the entire ADC and sets the data outputs to low. This pin has a 200k internal pull-up resistor to AVDD. The programming is done through a three-wire interface. The timing diagram and serial register setting in the Serial Programing Interface section describe the programming of this register. Table 2 shows the different modes and the bit values to be written on the register to enable them. Note that some of these modes may modify the standard operation of the device and possibly vary the performance with respect to the typical data shown in this data sheet.
26
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
PACKAGING INFORMATION
Orderable Device ADS5500IPAP ADS5500IPAPR
(1)
Status (1) ACTIVE ACTIVE
Package Type HTQFP HTQFP
Package Drawing PAP PAP
Pins Package Eco Plan (2) Qty 64 64 160 1000 None None
Lead/Ball Finish CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-3-235C-168 HR Level-3-235C-168 HR
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless

▲Up To Search▲

Price & Availability of ADS5500

	To Download ADS5500 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .