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| ADS ADS808 808 www.ti.com 12-Bit, 70MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM FEATURES q DYNAMIC RANGE: SNR: 65dB at 10MHz fIN SFDR: 68dB at 10MHz fIN q PREMIUM TRACK/HOLD: High Bandwidth: 1GHz Low Jitter: 0.25ps rms Differential or Single-Ended Inputs Selectable Full-Scale Input Range q FLEXIBLE CLOCKING: Differential or Single-Ended Accepts Sine or Square Wave Clocking Down to 0.5Vp-p Variable Threshold Level DESCRIPTION The ADS808 is a high-dynamic range 12-bit, 70MHz pipelined Analog-to-Digital (A/D) converter. It includes a high-bandwidth linear track/hold that gives excellent spurious performance up to and beyond the Nyquist rate. This high-bandwidth track/hold also has a low jitter of only 0.25ps rms, leading to excellent SNR performance. The clock input can accept a low level differential sine wave or square wave signal down to 0.5Vp-p, further improving the SNR performance. It also accepts a single-ended clock signal and has flexible threshold levels. The ADS808 has a 2Vp-p differential input range (1Vp-p x 2 inputs) for optimum signal-to-noise ratio. The differential operation gives the lowest even-order harmonic components. A lower input voltage of 1.5Vp-p or 1Vp-p can also be selected using the internal references, further optimizing SFDR. Alternatively, a single-ended input range can be used by tying the IN input to the common-mode voltage if desired. The ADS808 also provides an over-range flag that indicates when the input signal has exceeded the converter's fullscale range. This flag can also be used to reduce the gain of the front end signal conditioning circuitry. It also employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS808 is available in a small TQFP-48 package. +VS DV APPLICATIONS q BASESTATION WIDEBAND RADIOS: CDMA, GSM, TDMA, 3G, AMPS, NMT q TEST INSTRUMENTATION q CCD IMAGING CLK ADS808 Timing Circuitry CLK 1Vp-p 1Vp-p IN T/H IN 12-Bit Pipelined A/D Core Error Correction Logic 3-State Outputs D0 * * * D11 CM (+2.5V) Reference Ladder and Driver Reference and Mode Select OVR REFT VREF SEL1 SEL2 REFB OE VDRV Copyright (c) 2000, Texas Instruments Incorporated SBAS179 Printed in U.S.A. December, 2000 SPECIFICATIONS At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, and internal reference, unless otherwise noted. ADS808Y PARAMETER RESOLUTION SPECIFIED TEMPERATURE RANGE ANALOG INPUT Standard Differential Input Range Single-Ended Input Voltage Common-Mode Voltage Optional Input Ranges Analog Input Bias Current Track-Mode Input Bandwidth Input Impedance CONVERSION CHARACTERISTICS Sample Rate Data Latency DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 1MHz No Missing Codes Integral Nonlinearity Error, f = 1MHz Spurious Free Dynamic Range(1) f = 1MHz f = 10MHz Two-Tone Intermodulation Distortion fIN = 19.4MHz and 20.4MHz (-7dB each tone) Signal-to-Noise Ratio (SNR) f = 1MHz f = 10MHz Signal-to-(Noise + Distortion) (SINAD) f = 2.2MHz f = 10MHz Output Noise Aperture Delay Time Aperture Jitter Overvoltage Recovery Time Full-Scale Step Acquisition Time DIGITAL INPUTS Convert Command (Start Conversion) Logic Family (Other Clock Inputs) High Level Input Current(3) (VIN = 5V) Low Level Input Current (VIN = 0V) High Level Input Voltage Low Level Input Voltage Input Capacitance DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50A to 1.6mA) High Output Voltage, (IOH = 50A to 0.5mA) Low Output Voltage, (IOL = 50A to 1.6mA) High Output Voltage, (IOH = 50A to 1.6mA) 3-State Enable Time 3-State Disable Time Output Capacitance Ambient Air (1Vp-p x 2, +10dBm) 1Vp-p Selectable -3dBFS 1 2 2.5 1Vp-p or 1.5Vp-p 1 1 1.25 || 9 1M 5 70M CONDITIONS MIN TYP 12 Guaranteed -40 to +85 2 3 MAX UNITS Bits C V V V V A GHz M || pF Samples/s Clk Cyc 0.7 Guaranteed 4.0 72 68 -77 64.5 64 64 63 0.3 3 0.25 2 5 +0.5 1.7 7 LSB LSBs dBFS(2) dBFS dBFS dBFS dBFS dBFS dBFS LSBs rms ns ps rms ns ns 65 Input Grounded Rising Edge of Convert Clock +VS 100 10 Vp-p A A V V pF +2.0 +3V/+5V Compatible CMOS +1.0 5 VDRV = 3V +2.5 VDRV = 5V +2.5 OE = L OE = H +0.2 +3V/+5V Compatible CMOS +0.2 Straight Offset Binary 20 40 2 10 5 0.5 12 1.5 38 0.75 20 68 10 660 V V V V ns ns pF %FS ppm/C %FS ppm/C %FS ppm/C dB mV ACCURACY (Internal Reference, = 2V, Unless Otherwise Noted) Zero Error (Midscale) at 25C Zero Error Drift (Midscale) Gain Error(4) at 25C Gain Error Drift(4) Gain Error(5) at 25C Gain Error Drift(5) Power Supply Rejection of Gain VS = 5% Internal REF Tolerance (VREFP - VREFN) Deviation from Ideal Reference Input Resistance 40 2 ADS808 SBAS179 SPECIFICATIONS (Cont.) At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, and internal reference, unless otherwise noted. ADS808Y PARAMETER POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Output Driver Supply Current (VDRV) Power Dissipation: VDRV = 5V VDRV = 3V VDRV = 5V VDRV = 3V Power Down Thermal Resistance, JA TQFP-48 CONDITIONS Operating Operating Internal Reference Internal Reference External Reference External Reference Operating MIN +4.75 TYP +5.0 142 10 740 720 720 700 20 28.8 MAX +5.25 UNITS V mA mA mW mW mW mW mW C/W 770 NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) A 50k pull-down resistor is inserted internally. (4) Includes internal reference. (5) Excludes internal reference. PACKAGE/ORDERING INFORMATION PACKAGE DESIGNATOR PHP " SPECIFIED TEMPERATURE RANGE -40C to +85C " PACKAGE MARKING ADS808Y " ORDERING NUMBER(1) ADS808Y/250 ADS808Y/2K TRANSPORT MEDIA Tape and Reel Tape and Reel PRODUCT ADS808Y " PACKAGE TQFP-48 " NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of "ADS808Y/2K" will get a single 2000-piece Tape and Reel. ABSOLUTE MAXIMUM RATINGS +VS ....................................................................................................... +6V Analog Input ........................................................... (-0.3V) to (+VS +0.3V) Logic Input ............................................................. (-0.3V) to (+VS +0.3V) Case Temperature ......................................................................... +100C Junction Temperature .................................................................... +150C Storage Temperature ..................................................................... +150C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ADS808 SBAS179 3 PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 I/O DESIGNATOR BYP +VS +VS +VS GND CLK CLK GND GND OVR DV NC NC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION Bypass Point Supply Voltage Supply Voltage Supply Voltage Ground Clock Input Complementary Clock Input Ground Ground Overrange Indicator Data Valid Pulse: HI = Data Vaild No Connection No Connection Data Bit 11, (MSB) Data Bit 10 Data Bit 9 Data Bit 8 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0, (LSB) PIN 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I/O DESIGNATOR VDRV GND OE PD BTC GND SEL2 SEL1 VREF GND GND GND GND REFB CM REFT GND GND IN GND IN +VS +VS DESCRIPTION Output Bit Driver Voltage Supply Ground Output Enable: HI = High Impedance; LO or Floating: Normal Operation Power Down: HI = Power Down; LO = Normal HI = Binary Two's Complement; LO = Straight Binary Ground Reference Select 2: See Table Reference Select 1: See Table Internal Reference Voltage Ground Ground Ground Ground Bottom Reference Voltage Bypass Common-Mode Voltage (mid-scale) Top Reference Voltage Bypass Ground Ground Complementary Analog Input Ground Analog Input Supply Voltage Supply Voltage I I I I I O O O O O O O O O O O O O O I I PIN DIAGRAM REFB REFT GND GND GND GND 38 48 BYP +VS +VS +VS GND CLK CLK GND GND 1 2 3 4 5 6 7 8 9 47 46 45 44 43 42 41 40 39 37 36 GND 35 GND 34 VREF 33 SEL1 32 SEL2 GND 31 GND 30 BTC 29 PD 28 OE 27 GND 26 VDRV 25 D0 (LSB) 24 +VS +VS ADS808Y OVR 10 DV 11 NC 12 13 14 15 16 17 18 19 20 21 22 23 NC D11 (MSB) D10 D9 D8 D7 D6 D5 D4 CM IN IN D3 D2 NC = No Connection D1 4 ADS808 SBAS179 TIMING DIAGRAM N+6 Analog In N N+1 N+2 tA Clock t1 5 Clock Cycles Data Bits Out N-5 N-4 N-3 N-2 N-1 t2 tDV Data Valid Pulse N N+1 tCONV tH tL N+3 N+4 N+5 N+7 SYMBOL t CONV tH tL tA tDV t1 t2 DESCRIPTION Convert Clock Period Clock Pulse High Clock Pulse Low Aperture Delay Data Valid Pulse Delay(1) Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max MIN 12.5 6.2 6.2 TYP MAX 1s UNITS ns ns ns ns ns ns ns 4.6 t CONV /2 t CONV /2 4.6 19.1 5.8 17 6.1 20.5 19.3 NOTE: (1) Measured from the 50% point of the clock to the time when signals are within valid logic levels. REFERENCE AND FULL-SCALE RANGE SELECT TABLE DESIRED FULL SCALE RANGE 1Vp-p 1.5Vp-p 2Vp-p SEL1 VREF GND GND SEL2 GND +VS GND INTERNAL VREF 0.5V 0.75V 1.0V For external reference operation, tie VREF to +VS and apply REFT and REFB externally. Internal voltage buffer of CM is powered down. In this case CM should not be used externally. The full-scale input range is equal to 2x the reference value (REFT - REFB). ADS808 SBAS179 5 TYPICAL PERFORMANCE CURVES At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, and internal reference, unless otherwise noted. SPECTRAL PERFORMANCE (Differential, 2Vp-p) 0 80 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 20 25 30 35 Frequency (MHz) fIN = 1MHz (-1.0dBFS) SFDR = 71.40dBFS SNR = 64.41dBFS SINAD = 63.33dBFS fIN = 1MHz 75 70 DYNAMIC PERFORMANCE vs SAMPLING FREQUENCY SFDR, SNR, and SINAD (dBFS) SFDR Amplitude (dBFS) SNR 65 60 SINAD 55 50 30 35 40 45 50 55 60 65 70 75 80 Sampling Frequency (MHz) DYNAMIC PERFORMANCE vs SAMPLING FREQUENCY (2Vp-p, Differential) 80 80 DYNAMIC PERFORMANCE vs SAMPLING FREQUENCY (2Vp-p, Differential) SFDR, SNR, and SINAD (dBFS) 75 SFDR 70 65 60 SINAD 55 50 30 35 40 45 50 55 60 65 70 75 80 Sample Frequency (MHz) SNR SFDR, SNR, and SINAD (dBFS) fIN = 10MHz fIN = 20MHz 75 70 SNR 65 60 55 50 40 45 50 55 60 65 70 75 80 Sample Frequency (MHz) SINAD SFDR TOTAL POWER vs SAMPLING FREQUENCY 760 740 720 700 680 660 640 620 600 580 560 540 520 500 30 35 40 45 50 55 75 DYNAMIC PERFORMANCE vs INPUT FREQUENCY SFDR, SNR, and SINAD (dBFS) fIN = 10MHz SFDR 70 Power (mW) fIN = 1MHz 65 SNR 60 SINAD 55 50 60 65 70 75 80 1 6 11 16 21 26 31 Sampling Frequency (MHz) Input Frequency (MHz) 6 ADS808 SBAS179 TYPICAL PERFORMANCE CURVES (Cont.) At TA = full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, and internal reference, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR 1 0.8 0.6 0.4 5 4 3 ILE (LSB) 2 1 0 -1 -2 -3 0 1024 2048 Code 3072 4096 0 INTEGRAL LINEARITY ERROR DLE (LSB) 0.3 0 -0.2 -0.4 -0.6 -0.8 -1 1024 2048 Code 3072 4096 OUTPUT NOISE HISTOGRAM (2Vp-p, Grounded Input) 300k 250k 200k Counts 150k 100k 50k 0 N-2 N-1 N Code N+1 N+2 ADS808 SBAS179 7 APPLICATION INFORMATION THEORY OF OPERATION The ADS808 is a high-speed, high performance, CMOS A/D converter built with a fully differential, 9-stage pipeline architecture. Each stage contains a low-resolution quantizer and digital error correction logic, ensuring excellent differential linearity and no missing codes at the 12-bit level. The conversion process is initiated by a rising edge of the external convert clock. Once the signal is captured by the input track-and-hold amplifier, the bits are sequentially encoded starting with the MSB. This process results in a data latency of five clock cycles, after which the output data is available as a 12-bit parallel word either coded in a straight binary or two's complement format. The analog input of the ADS808 consists of a differential tack and hold circuit, as shown in Figure 1. The differential topology produces a high level of AC-performance at high sampling rates. It also results in a very high usable input bandwidth that is especially important for IF, or undersampling applications. Both inputs (IN, IN) require external biasing up to a common-mode voltage that is typically at the mid-supply level (+VS /2). This is because the on-resistance of the CMOS switches is lowest at this voltage, minimizing the effects of the signal dependent nonlinearity of RON. The track and hold circuit can also convert a single-ended input signal into a fully differential signal for the quantizer. For ease of use, the ADS808 incorporates a selectable voltage reference, a versatile clock input, and a logic output driver designed to interface to 3V or 5V logic. ADS808 is particularly suited for communication systems that digitize wideband signals. Features on the ADS808, like the input range selector or the option of an external reference, provide the needed flexibility to accommodate a wide range of applications. In any case, the analog interface/ driver requirements should be carefully examined before selecting the appropriate circuit configuration. The circuit definition should include considerations on the input frequency spectrum and amplitude, single-ended versus differential driver configuration, as well as the available power supplies. Differential vs Single-Ended The ADS808 input structure allows it to be driven either single-ended or differentially. Differential operation of the ADS808 requires an input signal that consists of an in-phase and a 180 out-of-phase component simultaneously applied to the inputs (IN, IN). Differential signals offer a number of advantages, that in many applications, will be instrumental in achieving the best harmonic performance of the ADS808: * The signal amplitude is half of that required for the singleended operation, and is therefore less demanding to achieve while maintaining good linearity performance from the signal source. * The reduced signal swing allows for more headroom of the interface circuitry, and therefore a wider selection of the best suitable driver amplifier. * Even-order harmonics are minimized. * Improves the noise immunity based on the converter's common-mode input rejection. For the single-ended mode, the signal is applied to one of the inputs while the other input is biased with a DC voltage to the required common-mode level. Both inputs are identical in terms of their impedance and performance except that applying the signal to the complementary input (IN) instead of the IN-input will invert the orientation of the input signal relative to the output code. For example, if the input driver operates in inverting mode, using IN as the signal input, it will restore the phase of the signal to its original orientation. Time-domain applications may benefit from a single-ended interface configuration and a reduced circuit complexity. Driving the ADS808 with a single-ended signal will result in a trade-off of the excellent distortion performance, while maintaining a good signal-to-noise ratio (SNR). The tradeoff of the differential input configuration over the singleended is its increase in circuit complexity. In either case, the selection of the driver amplifier should be such that the amplifier's performance will not degrade the A/D's performance. Input Full-Scale Range vs Performance Employing dual supply amplifiers and AC-coupling will usually yield the best results. DC-coupling and/or single-supply amplifiers impose additional design constrains due to their headroom requirements, especially when selecting the 2Vp-p input range. The full-scale input range of the ADS808 is defined either by the settings of the reference select pins (SEL1, SEL2) or by an external reference voltage (see Table I). ADS808 S5 S3 S1 IN S2 IN CIN CIN T&H S4 S6 Tracking Phase: S1, S2, S3, S4 closed; S5, S6 open Hold Phase: S1, S2, S3, S4 open; S5, S6 closed FIGURE 1. Simplified Circuit of Input Track-and-Hold Amplifier. DRIVING THE ANALOG INPUTS Types of Applications The analog input of the ADS808 can be configured in various ways and driven with different circuits, depending on the application and the desired level of performance. Offering a high dynamic range at high input frequencies, the 8 ADS808 SBAS179 By choosing between the three different signal input ranges, tradeoffs can be made between noise and distortion performance. For maximizing the SNR, which is important for time-domain applications, the 2Vp-p range may be selected. This range may also be used with low-level (-6dBFS to -40dBFS) to high frequency inputs (multi-tone). The 1.5Vp-p range may be considered for achieving a combination of both low noise and distortion performance. Here, the SNR number is typically 3dB down compared to the 2Vp-p range, while an improvement in the distortion performance of the driver amplifier may be realized due to the reduced output power level required. The third option, 1Vp-p FSR, may be considered mainly for applications requiring DCcoupling and/or single-supply operation of the driver and the converter. Input biasing (VCM) The ADS808 operates from a single +5V supply, and requires each of the analog inputs to be externally biased to a common-mode voltage of typically +2.5V. This allows a symmetrical signal swing while maintaining sufficient headroom to either supply rail. Communication systems are usually AC-coupled in-between signal processing stages, making it convenient to set individual common-mode voltages and allow optimizing the DC operating point for each stage. Other applications (e.g., imaging) process only unipolar or DC-restored signals. In this case, the common-mode voltage may be shifted such that the full-input range of the converter is utilized. It should be noted that the CM pin is internally buffered. However, it is recommended to keep the loading of this pin to a minimum to avoid an increase in the converter's nonlinearity. Also, the DC voltage at the CM pin is not exactly +2.5V, but is subject to the tolerance of the top and bottom references as well as the resistor ladder. Input Impedance As shown in Figure 1, the input of the ADS808 is of a capacitive nature and the driving source needs to provide the slew current to charge or discharge the input sampling capacitor while the track-and-hold amplifier is in track mode. This effectively results in a dynamic input impedance that is a function of the sampling frequency. Figure 2 depicts the differential input impedance of the ADS808 as a function of the input frequency. For applications that use op amps to drive the A/D converter, it is recommended to add a series resistor between the amplifier output and the converter inputs. This will isolate the converter's capacitive input from the driving source and avoid gain peaking, or instability. Furthermore, it will create a first-order, low-pass filter in conjunction with the specified input capacitance of the ADS808. Its cut-off frequency can be adjusted even further by adding an external shunt capacitor from each signal input to ground. However, the optimum values of this RC network depend on a variety of factors, including the ADS808's sampling rate, the selected op amp, the interface configuration, and the particular application (time domain vs frequency domain). Generally, increasing ADS808 INPUT IMPEDANCE vs INPUT FREQUENCY 1000 100 ZIN (k) 10 1 0.1 0.01 0.1 1 10 fIN (MHz) 100 1000 FIGURE 2. Differential Input Impedance versus Input Frequency. the size of the series resistor and/or capacitor will improve the signal-to-noise ratio, however, depending on the signal source, large resistor values may reduce the harmonic distortion performance. In any case, the use of the RC network is optional but optimizing the values to adapt to the specific application is encouraged. INPUT DRIVER CONFIGURATIONS The following section provides some principal circuit suggestions on how to interface the analog input signal to the ADS808. A first example of a typical analog interface circuit is shown in Figure 3. Here, it is assumed that the input signal is already available in differential form, e.g.: coming from a preceding mixer stage. The differential driver performs an impedance transformation as well as amplifying the signal to match the selected full-scale input range of the ADS808 (for example, 2Vp-p). The common-mode voltage (VCM) for the converter input is established by connecting the inputs to the midpoints of the resistor divider. The input signal is ACcoupled through capacitors CIN to the inputs of the converter that are set to a VCM of approximately +2.5VDC . 1k 1k CIN 0.1F VIN Differential Driver VIN 1k 1k CIN 0.1F VCM = +2.5V IN REFB IN ADS808 REFT NOTE: Reference bypassing omitted for clarity. FIGURE 3. AC coupling allows for easy DC biasing of the ADS808 inputs while the input signal is applied by the differential input driver. 9 ADS808 SBAS179 Some differential driver circuits may allow setting an appropriate common-mode voltage directly at the driver input. This will simplify the interface to the ADS808 and eliminate the external biasing resistors and the coupling capacitors. Suitable integrated circuits include the AD8138. This part permits a DC-coupled interface solution; however, its use is limited to about a 10MHz input frequency for which the part maintains acceptable distortion performance providing a 2Vp-p (max) output swing on 5V supplies. Combining a differential driver circuit with a step-up transformer can lead to significant improvement of the distortion performance (see Figure 6). Transformer Coupled Interface Circuits If the application allows for AC-coupling, but requires a signal conversion from a single-ended source to drive the ADS808 differentially, using a transformer offers a number of advantages. As a passive component, it does not add to the total noise, plus using a step-up transformer, further signal amplification can be realized. As a result, the signal swing out of the amplifier driving the transformer can be reduced, leading to more headroom for the amplifier and improved distortion performance. One possible interface solution that uses a transformer is given in Figure 4. The input signal is assumed to be an Intermediate Frequency (IF) and bandpass filtered prior to the IF amplifier Dedicated IF amplifiers, for example the RF2312 or MAR-6, are fixed-gain broadband amplifiers and feature a very high bandwidth, a low-noise figure, and a high intercept point at the expense of high quiescent currents of 50 to 120mA. The IF amplifier may be AC-coupled or directly connected to the primary side of the transformer. A variety of miniature RF transformers are readily available from different manufacturers, i.e.: Mini-Circuits, Coilcraft, or Trak. For the selection, it is important to carefully examine the application requirements and determine the correct model, the desired impedance ratio, and frequency characteristics. Furthermore, the appropriate model must support the targeted distortion level and should not exhibit any core saturation at full-scale voltage levels. Since the transformer does not appreciably load the ladder, its center tap can be directly tied to the CM pin of the converter (see Figure 4). The value of termination resistor (RT) should be chosen to satisfy the termination requirements of the source impedance (RS). It can be calculated using the equation RT = n2 * RS to ensure proper impedance matching. Transformer Coupled, Single-Ended to Differential Configuration For applications in which the input frequency is limited to about 40MHz (i.e.: baseband), the wideband, current-feedback, operational amplifier OPA685 may be used. As shown in Figure 5, the OPA685 is configured for the non-inverting mode, amplifies the single-ended input signal, and drives the primary of a RF transformer. To maintain the very low distortion performance of the OPA685, it may be advantageous to reduce the full-scale input range (FSR) of the ADS808 from 2Vp-p to 1.5Vp-p or 1Vp-p (refer to the paragraph "Reference" for details on selecting the converter's full-scale range). The circuit also shows the use of additional RC low-pass filter placed in series with each converter input. This optional filter can be used to set a defined corner frequency and +VS 1:n XFMR RT -VS VCM +2.5V + 4.7F +5V VIN (IF) Optional Bandpass Filter IF Amp RS 0.1F RIN IN RIN CIN IN CIN CM ADS808 0.1F FIGURE 4. Driving the ADS808 with a Low Distortion RF Amplifier and a Transformer Suited for IF Sampling Applications. +V -V RG +5V VIN OPA685 R1 RS 0.1F 1:n XFMR RT RIN IN RIN CIN IN CIN CM + VCM +2.5V 2.2F 0.1F ADS808 R2 FIGURE 5. Converting a Single-Ended Input Signal into a Differential Signal Using a RF Transformer. 10 ADS808 SBAS179 attenuate some of the wideband noise. The actual component values would need to be tuned for the individual application requirements. As a guideline, resistor values are typically in the range of 10 to 100, on back capacitors in the range of 10pF to 200pF. In any case, the R and C values should have a low tolerance. This will ensure that the ADS808 sees closely matched source impedances. AC-Coupled, Differential Interface with Gain The interface circuit example presented in Figure 6 employs two OPA685s, (current feedback op amp), optimized for gains of 8V/V or higher. The input transformer (T1) converts the single-ended input signal to a differential signal required at the amplifier's inverting inputs, that are tuned to provide a 50 impedance match to an assumed 50 source. To achieve the 50 input match at the primary of the 1:2 transformer, the secondary input must see a 200 load impedance. Both amplifiers are configured for the inverting mode resulting in close gain and phase matching of the differential signal. This technique, along with a highly symmetrical layout, is instrumental in achieving a substantial reduction of the second harmonic, while retaining excellent third-order performance. A common-mode voltage (VCM) is applied to the non-inverting inputs of the OPA685. Additional series of 43.2 resistors isolate the output of the op amps from the capacitive load presented by the 22pF capacitors and the input capacitance of the ADS808. This 43.2 /22pF combination sets a pole at approximately 167MHz and rolls off some of the wideband noise. REFERENCE REFERENCE OPERATION Integrated into the ADS808 is a bandgap reference circuit including some logic that provides a +0.5V, +0.75V, or +1V reference output by selecting the corresponding pin-strap configuration. Table I gives a complete overview of the possible reference options and pin configurations. +5V DIS VCM OPA685 Power supply decoupling not shown. 50 Source VI Noise Figure 11.8dB T1 1:2 100 -5V 600 43.2 22pF VO ADC Input 100 +5V 600 43.2 22pF DIS OPA685 VCM -5V VO = 12V/V (21.6dB) VI FIGURE 6. Wideband Differential ADC Driver. DESIRED FULL-SCALE RANGE, FSR (Differential) 2Vp-p (+10dBm) 1.5Vp-p (+7.5dBm) 1Vp-p External Reference CONNECT SEL1 (Pin 33) GND GND VREF -- CONNECT SEL2 (Pin 32) GND +VS GND -- VOLTAGE AT VREF (Pin 34) +1.0V +0.75V +0.5V > +3.5V VOLTAGE AT REFT (Pin 41) +3V +2.875V +2.75V +2.75V to +4.5V VOLTAGE AT REFB (Pin 39) +2V +2.125V +2.25V +0.5V to +2.25V TABLE I. Reference Pin Configurations and Corresponding Voltage on the Reference Pins. ADS808 SBAS179 11 Figure 7 shows the basic model of the internal reference circuit. The functional blocks are a 1V bandgap voltage reference, a selectable gain amplifier, the drivers for the top and bottom reference (REFT, REFB), and the resistive reference ladder. The ladder resistance measures approximately 660 between the REFT and REFB pin. The ladder is split into two equal segments, establishing a commonmode voltage at the ladder midpoint, labeled "CM". The ADS808 requires solid bypassing for all reference pins to keep the effect of clock feedthrough to a minimum and to achieve the specified level of performance. Figure 7 also demonstrate the recommended decoupling scheme. All 0.1F capacitors should be located as close to the pins as possible. When operating the ADS808 from the internal reference, the effective full-scale input span for each of the inputs, IN and IN, is determined by the voltages at REFT and REFB pins, given as: Input Span (differential) = 2x (REFT - REFB), in Vp-p = 2 x VREF The top and bottom reference outputs may be used to provide up to 1mA (sink or source) of current to external circuits. Degradation of the differential linearity (DNL) and, consequently, of the dynamic performance of the ADS808 may occur if this limit is exceeded. Using External References For even more design flexibility, the ADS808 can be operated with an external reference. The utilization of an external reference voltage may be considered for applications requiring higher accuracy, improved temperature stability, or a continuous adjustment of the converter's full-scale range. Especially in multi-channel applications, the use of a common external reference offers the benefit of improving the gain matching between converters. Selection between internal or external reference operation is controlled through the VREF pin. The internal reference will become disabled if the voltage applied to the VREF pin exceeds +3.5VDC. Once selected, the ADS808 requires two reference voltages--a top-reference voltage applied to the REFT pin and a bottom-reference voltage applied to the REFB pin (see Table I). As illustrated in Figure 8, a micropower reference (REF1004) and a dual, single supply amplifier may be used to generate a precision external reference. Note that the function of the range select pins, SEL1 and SEL2, are disabled while the converter is in external mode. SEL1 SEL2 PD ByP 0.1F Range Select and Gain Amplifier Top Reference Driver 330 REFT 0.1F CM 0.1F 330 1F +1VDC Bandgap Reference Bottom Reference Driver ADS808 VREF 0.1F 1 0.1F REFB 0.1F FIGURE 7. Internal Reference Circuit of the ADS808 and Recommended Bypass Scheme. +5V -5V 1/2 OPA2234 + R3 2.2F 0.1F 4.7k REFT R1 REF1004 +2.5V + 10F R4 ADS808 1/2 OPA2234 R2 0.1F + 2.2F 0.1F REFB FIGURE 8. Example for an External Reference Circuit Using a Dual, Single-Supply Op Amp. 12 ADS808 SBAS179 DIGITAL INPUTS AND OUTPUTS CLOCK INPUT Unlike most A/D converters, the ADS808 contains an internal clock conditioning circuitry. This enables the converter to adapt to a variety of application requirements and different clock sources. Some interface examples are given in the following section. With no input signal connected to either clock pin, the threshold level is set to about +1.6V by the on-chip resistive voltage divider (see Figure 9). The parallel combination of R1 || R2 and R3 || R4 sets the input impedance of the clock inputs (CLK, CLK) to approximately 2.7k single-ended or 5.4k differentially. The associated groundreferenced input capacitance is approximately 5pF for each input. If a logic voltage other than the nominal +1.6V is desired, the clock inputs can be externally driven to establish an alternate threshold voltage. Applying a single-ended clock signal will provide satisfactory results in many applications. However, unbalanced high-speed logic signals often introduce a high amount of disturbances, such as ringing or ground bouncing. Also, a high amplitude may cause the clock signal to have unsymmetrical rise and fall times, potentially effecting the converter distortion performance. Proper termination practice and a clean PCB layout will help to keep those effects to a minimum. To take full advantage of the excellent distortion performance of the ADS808, it is recommended to drive the clock inputs differentially. A low-level, differential clock improves the digital feedthrough immunity and minimizes the effect of modulation between the signal and the clock. Figure 11 illustrates a simple method of converting a square wave clock from single-ended to differential using a RF transformer. Small surface-mount transformers are readily available from several manufacturers (e.g.: model ADT1-1 by Mini-Circuits). A capacitor in series with the primary side may be inserted to block any DC voltage present in the signal. Since the clock inputs are self-biased, the secondary side connects directly to the two clock inputs of the converter. +5V ADS808 R3 8.5k R1 8.5k CLK CLK R2 4k R4 4k 0.1F Square Wave Clock Source 1:1 CLK ADS808 CLK FIGURE 9. The Differential Clock Inputs are Internally Biased. The ADS808 can be interfaced to standard TTL or CMOS logic and accepts 3V or 5V compliant logic levels. In this case, the clock signal should be applied to the CLK-input, while the complementary clock input (CLK) should be bypassed to ground by a low-inductance ceramic chip capacitor, as shown in Figure 10. Depending on the quality of the signal, inserting a series, damping resistor may be beneficial to reduce ringing. When digitizing at high sampling rates (fS > 50MHz), the clock should have a 50% duty cycle (tH = tL) to maintain a good distortion performance. FIGURE 11. Connecting a Ground Referenced Square Wave Clock Source to the ADS808 Using a RF Transformer. The clock inputs of the ADS808 can be connected in a number of ways. However, the best performance is obtained when the clock input pins are driven differentially. When operating in this mode, the clock inputs accommodate signal swings ranging from 2.5Vp-p down to 0.5Vp-p differentially. This allows direct interfacing of clock sources, such as voltage-controlled crystal oscillators (VCXO) to the ADS808. The advantage here is the elimination of external logic usually necessary to convert the clock signal into a suitable logic (TTL or CMOS) signal, that otherwise would create an additional source of jitter. In any case, a very lowjitter clock is fundamental to preserving the excellent AC performance of the ADS808. The converter itself is specified for a very low 0.25ps (rms) jitter, characterizing the outstanding capability of the internal clock and track-andhold circuitry. Generally, as the input frequency increases, the clock jitter becomes more dominant in maintaining a good SNR. This is particularly critical in IF sampling applications where the sampling frequency is lower than the input frequency (or undersampling). The following equation can CLK TTL/CMOS Clock Source (3V/5V) CLK 47nF ADS808 FIGURE 10. Single-Ended TTL/CMOS Clock Source. ADS808 SBAS179 13 be used to calculate the achievable SNR for a given input frequency and clock jitter (tJA in ps rms). SINGLE-ENDED INPUT (IN) (IN Biased to VCM) +FS - 1LSB (IN = CMV + FSR/ 2) +1/2 FS Bipolar Zero (IN = CMV) STRAIGHT OFFSET BINARY (SOB) 1111 1111 1111 1100 0000 0000 1000 0000 0000 0100 0000 0000 0000 0000 0000 BINARY TWO'S COMPLEMENT (BTC) 0111 1111 1111 0100 0000 0000 0000 0000 0000 1100 0000 0000 1000 0000 0000 SNR = 20 log10 (2 fIN t JA ) 1 Depending on the nature of the clock source's output impedance, an impedance matching might become necessary. For this, a termination resistor (RT) may be installed, as shown in Figure 12. To calculate the correct value for this resistor, consider the impedance ratio of the selected transformer and the differential clock input impedance of the ADS808, which is approximately 5.4k. It is not recommended to employ any type of differential TTL logic that suffers from mismatch in delay time and slew-rate leading to performance degradation. Alternatively, a low jitter ECL or PECL clock may be AC-coupled directly to the clock inputs using small (0.1F) capacitors. -1/2 FS -FS (IN = CMV - FSR /2) TABLE II. Coding Table for Single-Ended Input Configuration with IN Tied to the Common-Mode Voltage (CMV). BINARY TWO'S COMPLEMENT (BTC) 0111 1111 1111 0100 0000 0000 0000 0000 0000 1100 0000 0000 1000 0000 0000 DIFFERENTIAL INPUT +FS - 1LSB (IN = +3V, IN = +2V) +1/2 FS Bipolar Zero (IN = IN = CMV) -1/2 FS -FS (IN = +2V, IN = +3V) STRAIGHT OFFSET BINARY (SOB) 1111 1111 1111 1100 0000 0000 1000 0000 0000 0100 0000 0000 0000 0000 0000 1:1 RF Sine Source RT CLK ADS808 CLK TABLE III. Coding Table for Differential Input Configuration and 2Vp-p Full-Scale Input Range. Output Enable (OE) FIGURE 12. Applying a Sinusoidal Clock to the ADS808. MINIMUM SAMPLING RATE The pipeline architecture of the ADS808 uses the switched capacitor technique in its internal track and hold stages. With each clock cycles charges representing the captured signal level are moved within the A/D pipeline core. The high sampling speed necessitates the use of very small capacitor values. In order to hold the droop errors low, the capacitors require a minimum "refresh rate". Therefore, the sampling clock on the ADS808 should not drop below the specified minimum of 1MHz. DATA OUTPUT FORMAT (BTC) The ADS808 makes two data output formats available, either the "Straight Offset Binary" code (SOB) or the "Binary Two's Complement" code (BTC). The selection of the output coding is controlled through the BTC pin. Applying a logic HIGH will enable the BTC coding, while a logic LOW will enable the SOB code. The BTC output format is widely used to interface to microprocessors and such. The two code structures are identical with the exception that the MSB is inverted for the BTC format, see Tables II and III. The digital outputs of the ADS808 can be set to high impedance (tri-state), exercising the output enable pin (OE). For normal operation, this pin must be at a logic low potential while a logic high voltage disables the outputs. Even though this function effects the output driver stage, the threshold voltages for the OE pin do not depend on the output driver supply (VDRV), but are fixed (see "Specifications, Digital Inputs"). Operating the OE function dynamically (i.e.: high speed multiplexing, should be avoided, as it will corrupt the conversion process. Power Down (PD) A power-down of the ADS808 is initiated by taking the PD pin HIGH. This shuts down portions within the converter and reduces the power dissipation to about 20mW. The remaining active blocks include the internal reference, ensuring a fast reactivation time. During power-down, data in the converter pipeline will be lost and new valid data will be subject to the specified pipeline delay. In case the PD pin is not used, it should be tied to ground or a logic low level. Over Range Indicator (OVR) If the analog input voltage exceeds the full-scale range set by the reference voltages, an over range condition exists. The ADS808 incorporates a function, that monitors the input voltage and detects any such out-of-range condition. The 14 ADS808 SBAS179 current state can be read at the over range indicator pin (OVR). This output is LOW when the input voltage is within the defined input range. It will change to HIGH if the applied signal exceeds the full-scale range. It should be noted that the OVR output is updated along with the data output, corresponding to the particular sampled analog input voltage. Therefore, the OVR data is subject to the same pipeline delay as the digital data (5 clock cycles). Output Loading It is recommended to keep the capacitive loading on the data output lines as low as possible, preferably below 15pF. Higher capacitive loading will cause larger dynamic currents to flow as the digital outputs are changing. For example, with a typical output slew-rate of 0.8V/ns and a total capacitive loading of 10pF (including 4pF output capacitance, 5pF input capacitance of external logic buffer, and 1pF pc-board parasitics), a bit transition can cause a dynamic current of (10pF * 0.8V/1ns = 8mA). Those high current surges can feed back to the analog portion of the ADS808 and adversely affect the performance. External buffers, or latches, close to the converter's output pins may be used to minimize the capacitive loading. They also provide the added benefit of isolating the ADS808 from any digital activities on the bus from coupling back high-frequency noise. POWER SUPPLIES When defining the power supplies for the ADS808, is it highly recommended to consider linear supplies instead of switching types. Even with good filtering, switching supplies may radiate noise that could interfere with any high frequency input signal and cause unwanted modulation products. At its full conversion rate of 70MHz, the ADS808 requires typically 170mA of supply current on the +5V supply (+Vs). Note that this supply voltage should stay within a 5% tolerance. The ADS808 does not require separate analog and digital supplies, but only one single +5V supply to be connected to all its +VS pins. This is with the exception of the output driver supply pin, denoted VDRV (see the following section). Digital Output Driver Supply (VDRV) A dedicated supply pin, denoted VDRV, provides power to the logic output drivers of the ADS808, and may be operated with a supply voltage in the range of +3.0V to +5.0V. This can simplify interfacing to various logic families, in particular low-voltage CMOS. It is recommended to operate the ADS808 with a +3.0V supply voltage on VDRV. This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line that may affect the AC performance of the converter. The analog supply (+Vs) and driver supply (VDRV) may be tied together, with a ferrite bead or inductor between the supply pins. Each of the these supply pins must be bypassed separately with at least one 0.1F ceramic chip capacitor, forming a pi-filter. The recommended operation for the ADS808 is +5V for the +VS pins and +3.0V on the output driver pin (VDRV). LAYOUT AND DECOUPLING CONSIDERATIONS Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for highfrequency designs. Achieving optimum performance with a fast sampling converter, like the ADS808, requires careful attention to the pc-board layout to minimize the effect of board parasitics and optimize component placement. A multilayer board usually ensures best results and allows convenient component placement. The ADS808 should be treated as an analog component with the +VS pins connected to clean analog supplies. This will ensure the most consistent results, since digital supplies often carry a high level of switching noise that could couple into the converter and degrade the performance. As mentioned previously, the driver supply pins (VDRV) should also be connected to a low-noise supply. Supplies of adjacent digital circuits may carry substantial current transients. The supply voltage must be thoroughly filtered before connecting to the VDRV supply of the converter. All ground connections on the ADS808 are internally bonded to the metal flag (bottom of package) that forms a large ground plane. All ground pins should directly connect to an analog ground plane that covers the pc-board area under the converter. Because of its high sampling frequency, the ADS808 generates high-frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. If not sufficiently bypassed, this will add noise to the conversion process. Figure 13 shows the recommended supply decoupling scheme for the ADS808. All +VS pins may be connected together and bypassed with a combination of 10nF - 0.1F ceramic chip capacitors (0805, low ESR) and a 10F tantalum tank capacitor. A similar approach may be used on the driver supply pins, VDRV. In order to minimize the lead and trace inductance, the capacitors should be located as close to the supply pins as possible. Where double-sided component mounting is allowed, they are best placed directly under the package. In addition, larger bipolar decoupling capacitors (2.2F to 10F), effective at lower frequencies, should also be used on the main supply pins. They can be placed on the pc-board in proximity (< 0.5") of the A/D converter. ADS808 GND +VS 35, 36, 37, 38 42, 43, 45 2, 47, 48 0.01F GND 5, 8, 31 0.01F +VS 3, 4 GND 9, 27 VDR 26 0.01F 0.1F 0.1F 0.1F +5V +3V, +5V FIGURE 13. Recommended Supply Decoupling Scheme. ADS808 SBAS179 15 If the analog inputs to the ADS808 are driven differentially, it is especially important to optimize towards a highly symmetrical layout. Small trace length differences may create phase shifts compromising a good distortion performance. For this reason, the use of two single op amps (rather than one dual amplifier) enables a more symmetrical layout and a better match of parasitic capacitances. The pin orientation of the ADS808 package follows a "flow-through" design with the analog inputs located on one side of the package while the digital outputs are located on the opposite side of the quad-flat package. This provides a good physical isolation between the analog and digital connections. While designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog portion. Also, try to match trace length for the differential clock signal (if used) to avoid mismatches in propagation delays. Single-ended clock lines must be short and should not cross any other signal traces. Short-circuit traces on the digital outputs will minimize capacitive loading. Trace length should be kept short to the receiving gate (< 2 inch) with only one CMOS gate connected to one digital output. If possible, the digital data outputs should be buffered (with a 74LCX571, for example). Dynamic performance may also be improved with the insertion of series resistors at each data output line. This sets a defined time constant and reduces the slew rate that would otherwise flow, due to the fast edge rate. The resistor value may be chosen to result in a time constant of 15% to 25% of the used data rate. 16 ADS808 SBAS179 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, license, warranty or endorsement thereof. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Resale of TI's products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright (c) 2001, Texas Instruments Incorporated |
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