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ADS8411
SLAS369A - APRIL 2002 - REVISED JUNE 2003
16-BIT, 2 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE
FEATURES D D D D D D D D D D D D
2-MHz Sample Rate 16-Bit NMC Ensured Over Temperature Zero Latency Unipolar Single-Ended Input Range: 0 V to Vref Onboard Reference Onboard Reference Buffer High-Speed Parallel Interface Power Dissipation: 175 mW at 2 MHz Typ Wide Digital Supply 8-/16-Bit Bus Transfer 48-Pin TQFP Package ESD Sensitive - HBM Capability of 500 V, 1000 V at All Input Pins
APPLICATIONS D DWDM D Instrumentation D High-Speed, High-Resolution, Zero Latency
Data Acquisition Systems
D Transducer Interface D Medical Instruments D Communication DESCRIPTION
The ADS8411 is a 16-bit, 2 MHz A/D converter with an internal 4.096-V reference. The device includes a 16-bit capacitor-based SAR A/D converter with inherent sample and hold. The ADS8411 offers a full 16-bit interface and an 8-bit option where data is read using two 8-bit read cycles. The ADS8411 has a unipolar single-ended input. It is available in a 48-lead TQFP package and is characterized over the industrial -40C to 85C temperature range.
SAR
+IN -IN REFIN
+ _
Output Latches and 3-State Drivers
BYTE 16-/8-Bit Parallel DATA Output Bus
CDAC Comparator
RESET Conversion and Control Logic CONVST BUSY CS RD
REFOUT
4.096-V Internal Reference
Clock
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002-2003, Texas Instruments Incorporated
ADS8411
www.ti.com SLAS369A - APRIL 2002 - REVISED JUNE 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES RESOLUTION (BIT) PACKAGE TYPE PACKAGE DESIGNATOR TEMPERATURE RANGE ORDERING INFORMATION TRANSPORT MEDIA QUANTITY Tape and reel 250 Tape and reel 1000 Tape and reel 250 Tape and reel 1000
ADS8411IPFBT ADS8411I -6 ~ 6 6 -2~3 23 15 48 Pin TQFP PFB -40C to 85C 40C t ADS8411IPFBR ADS8411IBPFBT ADS8411IB -3.5 ~ 3.5 35 35 -1~2 12 16 48 Pin TQFP PFB -40C to 85C 40C t ADS8411IBPFBR
NOTE: For the most current specifications and package information, refer to our website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) +IN to AGND Voltage -IN to AGND +VA to AGND Voltage range +VBD to BDGND +VA to +VBD Digital input voltage to BDGND Digital output voltage to BDGND Operating free-air temperature range, TA Storage temperature range, Tstg Junction temperature (TJ max) Power dissipation TQFP package JA thermal impedance Vapor phase (60 sec) Lead temperature soldering temperature, Infrared (15 sec) -0.4 V to +VA + 0.1 V -0.4 V to 0.5 V -0.3 V to 7 V -0.3 V to 7 V -0.3 V to 2.55 V -0.3 V to +VBD + 0.3 V -0.3 V to +VBD + 0.3 V -40C to 85C -65C to 150C 150C (TJMax - TA)/JA 86C/W 215C 220C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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ADS8411
www.ti.com SLAS369A - APRIL 2002 - REVISED JUNE 2003
SPECIFICATIONS
TA = -40C to 85C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 2 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Analog Input Full-scale input voltage (see Note 1) Absolute input voltage Input capacitance Input leakage current System Performance Resolution ADS8411I No missing codes Integral linearity (see Notes 2 and 3) Differential linearity Differentiallinearity Offset error (see Note 4) Gain error (see Notes 4 and 5) Noise DC Power supply rejection ratio Sampling Dynamics Conversion time Acquisition time Throughput rate Aperture delay Aperture jitter Step response Overvoltage recovery (1) Ideal input span, does not include gain or offset error. (2) LSB means least significant bit (3) This is endpoint INL, not best fit. (4) Measured relative to an ideal full-scale input (+IN - -IN) of 4.096 V (5) This specification does not include the internal reference voltage error and drift. 2 25 100 100 100 2 360 ns ns MHz ns ps ns ns At FFFFh output code, +VA = 4.75 V to 5.25 V, Vref = 4.096 V, See Note 4 ADS8411IB ADS8411I ADS8411IB ADS8411I ADS8411IB ADS8411I ADS8411IB ADS8411I ADS8411IB 15 16 -6 -3.5 -2 -1 -1.5 -0.75 -0.15 -0.098 60 2 4 2 1 0.8 0.5 0.25 6 3.5 3 2 1.5 0.75 0.15 0.098 %FS V RMS LSB LSB mV mV LSB Bits 16 Bits +IN - -IN +IN -IN 0 -0.2 -0.2 25 0.5 Vref Vref + 0.2 0.2 V V pF nA MAX UNIT
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ADS8411
www.ti.com SLAS369A - APRIL 2002 - REVISED JUNE 2003
SPECIFICATIONS (CONTINUED)
TA = -40C to 85C, +VA = +5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 2 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Dynamic Characteristics Total harmonic distortion (THD) (see Note 1) Signal-to-noise ratio (SNR) Signal-to-noise + distortion (SINAD) Spurious free dynamic range (SFDR) -3dB Small signal bandwidth External Voltage Reference Input Reference voltage at REFIN, Vref Reference resistance (see Note 2) Internal Reference Output Internal reference start-up time Vref range Source Current Line Regulation Drift Digital Input/Output Logic family VIH VIL VOH VOL IIH = 5 A IIL = 5 A IOH = 2 TTL loads IOL = 2 TTL loads +VBD-1 -0.3 +VBD - 0.6 0 Straight Binary CMOS +VBD + 0.3 0.8 +VBD 0.4 V from 95% (+VA), with 1 F storage capacitor IOUT = 0 Static load +VA = 4.75 ~ 5.25 V IOUT = 0 0.6 36 4.065 4.096 120 4.13 10 ms V A mV PPM/C 3.9 4.096 500 4.2 V k VIN = 4 Vpp at 100 kHz VIN = 4 Vpp at 500 kHz VIN = 4 Vpp at 100 kHz VIN = 4 Vpp at 100 kHz VIN = 4 Vpp at 100 kHz VIN = 4 Vpp at 500 kHz -90 -88.5 86 85 90 88 5 dB dB dB dB dB dB MHz MAX UNIT
Logic level
Data format Power Supply Requirements +VBD Power supply voltage P l lt +VA fs = 2 MHz fs = 2 MHz +VA Supply current (see Note 3) Power dissipation (see Note 3) Temperature Range Operating free-air -40 (1) Calculated on the first nine harmonics of the input frequency (2) Can vary 20% (3) This includes only VA+ current. +VBD current is typically 1 mA with 5 pF load capacitance on output pins. 2.7 4.75
3 5 35 175
5.25 5.25 38 190 85
V V mA mW C
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ADS8411
www.ti.com SLAS369A - APRIL 2002 - REVISED JUNE 2003
TIMING CHARACTERISTICS
All specifications typical at -40C to 85C, +VA = +VBD = 5 V (see Notes 1, 2, and 3) PARAMETER tCONV tACQ tHOLD tpd1 tpd2 tpd3 tw1 tsu1 tw2 tw3 tw4 th1 td1 tsu2 tw5 ten td2 td3 tw6 tw7 th2 tpd4 tsu3 th3 tdis td5 tsu4 td6 td7 tsu(AB) Conversion time Acquisition time Sampling capacitor hold time CONVST low to BUSY high Propagation delay time, end of conversion to BUSY low Propagation delay time, from start of conversion (internal state) to rising edge of BUSY Pulse duration, CONVST low Setup time, CS low to CONVST low Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal low Pulse duration, BUSY signal high Hold time, First data bus data transition (RD low, or CS low for read cycle, or BYTE input changes) after CONVST low Delay time, CS low to RD low Setup time, RD high to CS high Pulse duration, RD low time Enable time, RD low (or CS low for read cycle) to data valid Delay time, data hold from RD high Delay time, BYTE rising edge or falling edge to data valid Pulse duration, RD high Pulse duration, CS high time Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge Setup time, BYTE transition to RD falling edge Hold time, BYTE transition to RD falling edge Disable time, RD high (CS high for read cycle) to 3-stated data bus Delay time, BUSY low to MSB data valid Byte transition setup time, from BYTE transition to next BYTE transition Delay time, CS rising edge to BUSY falling edge Delay time, BUSY falling edge to CS rising edge Setup time, from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST used to abort) or to the next falling edge of CS (when CS is used to abort) 50 50 50 60 340 0 2 20 20 50 0 0 0 20 10 20 40 0 0 50 20 Min(tACQ) 360 20 0 20 10 100 25 40 15 15 MIN TYP MAX 360 UNIT ns ns ns ns ns ns ns ns ns ps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. (3) All timings are measured with 20 pF equivalent loads on all data bits and BUSY pins.
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ADS8411
www.ti.com SLAS369A - APRIL 2002 - REVISED JUNE 2003
TIMING CHARACTERISTICS
All specifications typical at -40C to 85C, +VA = 5 V, +VBD = 3 V (see Notes 1, 2, and 3) PARAMETER tCONV tACQ tHOLD tpd1 tpd2 tpd3 tw1 tsu1 tw2 tw3 tw4 th1 td1 tsu2 tw5 ten td2 td3 tw6 tw7 th2 tpd4 tsu3 th3 tdis td5 tsu4 td6 td7 tsu(AB) Conversion time Acquisition time Sampling capacitor hold time CONVST low to BUSY high Propagation delay time, end of conversion to BUSY low Propagation delay time, from start of conversion (internal state) to rising edge of BUSY Pulse duration, CONVST low Setup time, CS low to CONVST low Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal low Pulse duration, BUSY signal high Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS 16/16 input changes) after CONVST low Delay time, CS low to RD low Setup time, RD high to CS high Pulse duration, RD low Enable time, RD low (or CS low for read cycle) to data valid Delay time, data hold from RD high Delay time, BYTE rising edge or falling edge to data valid Pulse duration, RD high time Pulse duration, CS high time Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge Setup time, BYTE transition to RD falling edge Hold time, BYTE transition to RD falling edge Disable time, RD high (CS high for read cycle) to 3-stated data bus Delay time, BUSY low to MSB data valid delay time Byte transition setup time, from BYTE transition to next BYTE transition Delay time, CS rising edge to BUSY falling edge Delay time, BUSY falling edge to CS rising edge Setup time, from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST used to abort) or to the next falling edge of CS (when CS is used to abort) 50 50 50 70 350 0 2 20 20 50 0 0 0 30 10 30 40 0 0 50 30 Min(tACQ) 360 20 0 20 10 100 25 50 25 25 MIN TYP MAX 360 UNIT ns ns ns ns ns ns ns ns ns ps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. (3) All timings are measured with 10-pF equivalent loads on all data bits and BUSY pins.
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ADS8411
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PIN ASSIGNMENTS
PFB PACKAGE (TOP VIEW)
36 35 34 33 32 31 30 29 28 27 26 25
+VBD RESET BYTE CONVST RD CS +VA AGND AGND +VA REFM REFM
BUSY BDGND +VBD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 BDGND
37 38 39 40 41 42 43 44 45 46 47 48 12 3 45 678 24 23 22 21 20 19 18 17 16 15 14 13 9 10 11 12
+VBD DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 AGND AGND +VA
REFIN REFOUT NC +VA AGND +IN -IN AGND +VA +VA
NC - No connection
AGND AGND
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ADS8411
www.ti.com SLAS369A - APRIL 2002 - REVISED JUNE 2003
TERMINAL FUNCTIONS
NAME AGND BDGND BUSY BYTE NO. 5, 8, 11, 12, 14, 15, 44, 45 25, 35 36 39 I/O - - O I Analog ground Digital ground for bus interface digital supply Status output. High when a conversion is in progress. Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[15:8]. Convert start. The falling edge of this input ends the acquisition period and starts the hold period. Chip select. The falling edge of this input starts the acquisition period. 8-Bit Bus Data Bus Dt B DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 -IN +IN NC REFIN REFM REFOUT RESET RD +VA +VBD 16 17 18 19 20 21 22 23 26 27 28 29 30 31 32 33 7 6 3 1 47, 48 2 38 41 4, 9, 10, 13, 43, 46 24, 34, 37 O O O O O O O O O O O O O O O O I I - I I O I I - - D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) Inverting input channel Non inverting input channel No connection Reference input Reference ground Reference output. Add 1 F capacitor between the REFOUT pin and REFM pin when internal reference is used. Current conversion is aborted and output latches are cleared (set to zeros) when this pin is asserted low. RESET works independantly of CS. Synchronization pulse for the parallel output. When CS is low, this serves as the output enable and puts the previous conversion result on the bus. Analog power supplies, 5-V dc Digital power supply for bus BYTE = 0 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) All ones All ones All ones All ones All ones All ones All ones All ones BYTE = 1 D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) 16-Bit Bus BYTE = 0 DESCRIPTION
CONVST CS
40 42
I I
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ADS8411
www.ti.com SLAS369A - APRIL 2002 - REVISED JUNE 2003
TIMING DIAGRAMS
tw1 CONVST tpd1 BUSY tsu1 CS tpd3 CONVERT tHOLD SAMPLING (When CS Toggle) tACQ BYTE tsu(AB) tsu4 th1 tpd4 RD td1 tsu2 th2 tsu(AB) td7 td6 tCONV tCONV tpd2 tw3 tw7 tw2
tw4
ten DB[15:8] Hi-Z D [15:8] DB[7:0] Hi-Z D [7:0] Signal internal to device D [7:0]
tdis Hi-Z
Hi-Z
Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling
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ADS8411
www.ti.com SLAS369A - APRIL 2002 - REVISED JUNE 2003
tw1 CONVST tpd1 BUSY tsu1 CS tpd3 CONVERT tHOLD SAMPLING (When CS Toggle) tpd2
tw2
tw4
tw3 tw7 td7 td6 tCONV tCONV
tACQ tsu(AB) BYTE th1 tpd4 RD = 0 DB[15:8] Hi-Z Previous D [15:8] Previous D [7:0] tdis Hi-Z ten D [15:8] tdis D [7:0] Hi-Z Repeated D [15:8] Repeated D [7:0] tsu4 th2 tsu(AB)
DB[7:0] ten
Hi-Z
Hi-Z
D [7:0] ten
Hi-Z
Signal internal to device
Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND
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ADS8411
www.ti.com SLAS369A - APRIL 2002 - REVISED JUNE 2003
tw1 CONVST tpd1 BUSY tsu1 CS = 0 tpd3 CONVERT tCONV tHOLD td6 tpd2
tw2
tw4
tw3 tw7
td7
tCONV
SAMPLING (When CS = 0) tsu(AB) BYTE
t(ACQ)
tsu(AB) tsu4 th1 tpd4 th2
RD ten DB[15:8] Hi-Z D [15:8] D [7:0] tdis Hi-Z
DB[7:0] Signal internal to device
Hi-Z
D [7:0]
Hi-Z
Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling
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ADS8411
www.ti.com SLAS369A - APRIL 2002 - REVISED JUNE 2003
tw1 CONVST tpd1 BUSY tw4 tpd2
tw2
tw3
CS = 0
CONVERT tpd3 tHOLD
tCONV tpd3 tHOLD t(ACQ)
tCONV
SAMPLING (When CS = 0) tsu(AB) BYTE th1 tsu4 tdis td5 DB[15:8]
Previous D [7:0] D [15:8] D [7:0]
tsu(AB) tsu4 th1 td3
Next D [15:8]
RD = 0
DB[7:0]
D [7:0]
Next D [7:0]
Signal internal to device
Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND--Auto Read
CS
RD tsu4 BYTE ten ten DB[15:0] Hi-Z Valid tdis Hi-Z Valid Valid td3 tdis Hi-Z
Figure 5. Detailed Timing for Read Cycles
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ADS8411
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TYPICAL CHARACTERISTICS
HISTOGRAM (DC Code Spread) FULL SCALE 131071 CONVERSIONS
70000 60000 50000 40000 30000 20000 10000 0 65230 65235 65239 +VA = 5 V, +VBD = 3.3 V Code = 65235 86.8 86.6 SNR - Signal-to-Noise Ratio - dB 86.4 86.2 86 85.8 85.6 85.4 85.2 -40 fi = 100 kHz, +VA = 5 V, +VBD = 3.3 V, TA = 25C, Internal Reference
SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE
-20
0 20 40 60 TA - Free-Air Temperature - C
80
Figure 6
Figure 7
SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE
83.8 SINAD - Signal-to-Nois and Distortion - dB 83.6 83.4 83.2 83 82.8 82.6 82.4 82.2 82 81.8 81.6 -40 -20 0 20 40 60 TA - Free-Air Temperature - C 80 13.6
EFFECTIVE NUMBER OF BITS vs FREE-AIR TEMPERATURE ENOB - Effective Number of Bits - Bits
fi = 100 kHz, +VA = 5 V, +VBD = 3.3 V, TA = 25C, Internal Reference
fi = 100 kHz, +VA = 5 V, +VBD = 3.3 V, TA = 25C, Internal Reference
13.55 13.5
13.45 13.4
13.35 13.3 13.25 -40
-20 0 20 40 60 TA - Free-Air Temperature - C
80
Figure 8
Figure 9
At -40C to 85C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 2 MHz (unless otherwise noted) 13
ADS8411
www.ti.com SLAS369A - APRIL 2002 - REVISED JUNE 2003
SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE
95.5 SFDR - Spurious Free Dynamic Range - dB 95 94.5 94 93.5 fi = 100 kHz, +VA = 5 V, +VBD = 3.3 V, TA = 25C, Internal Reference -91 -91.5 -92
TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE
fi = 100 kHz, +VA = 5 V, +VBD = 3.3 V, TA = 25C, Internal Reference
THD - Total Harmonic Distortion - dB
-92.5 -93
93 92.5 92 -40
-93.5 -94 -94.5 -40
-20 0 20 40 60 TA - Free-Air Temperature - C
80
-20
0
20
40
60
80
TA - Free-Air Temperature - C
Figure 10
SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY
86.9 13.9
Figure 11
EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY ENOB - Effective Number of Bits - Bits
+VA = 5 V, +VBD = 3.3 V, TA = 25C, Internal Reference
86.8 SNR - Signal-to-Noise Ratio - dB 86.7 86.6 86.5 86.4 86.3 86.2 86.1 86 0 20
+VA = 5 V, +VBD = 3.3 V, TA = 25C, Internal Reference
13.85 13.8 13.75 13.7 13.65 13.6 13.55 13.5 13.45 13.4 0 20
40 60 80 fi - Input Frequency - kHz
100
40 60 80 fi - Input Frequency - kHz
100
Figure 12
Figure 13
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ADS8411
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SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY
85.50 SINAD - Signal-to-Nois and Distortion - dB SFDR - Spurious Free Dynamic Range - dB +VA = 5 V, +VBD = 3.3 V, TA = 25C, Internal Reference 103 102 101 100 99 98 97 96 95 94 0 20 40 60 80 100 fi - Input Frequency - kHz 0
SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY
+VA = 5 V, +VBD = 3.3 V, TA = 25C, Internal Reference
85
84.50
84
83.50
83 82.50
20
40 60 80 fi - Input Frequency - kHz
100
Figure 14
TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY
-92 -93 -94 -95 -96 -97 -98 -99 -100 -101 0 20 40 60 80 fi - Input Frequency - kHz 100 +VA = 5 V, +VBD = 3.3 V, TA = 25C, Internal Reference 33.5 33 ICC - Supply Current - mA 32.5 32 31.5 31 30.5 30 29.5 29 28.5 500 700 900
Figure 15
SUPPLY CURRENT vs SAMPLE RATE
+VA = 5 V, +VBD = 3.3 V, TA = 25C, Internal Reference
THD - Total Harmonic Distortion - dB
1100 1300 1500 1700 1900
Samply Rate - KSPS
Figure 16
Figure 17
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ADS8411
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GAIN ERROR vs SUPPLY VOLTAGE
0.25 +VBD = 3.3 V, TA = 25C, External Reference EO - Offset Error - mV 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 4.75
OFFSET ERROR vs SUPPLY VOLTAGE
+VB D= 3.3 V, TA = 25C, External Reference
0.20 E G - Gain Error - mV
0.15
0.10
0.05
4.75
4.85 4.95 5.05 5.15 VDD - Supply Voltage - V
5.25
4.85 4.95 5.05 5.15 VDD - Supply Voltage - V
5.25
Figure 18
INTERNAL VOLTAGE REFERENCE vs FREE-AIR TEMPERATURE
4.092 4.091 Internal Voltage Reference - V 4.090 E G - Gain Error - mV 4.089 4.088 4.087 4.086 4.085 4.084 4.083 -40 +VA = 5 V, +VBD = 3.3 V 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -20 0 20 40 60 TA - Free-Air Temperature - C 80 -0.15 -40 -20
Figure 19
GAIN ERROR vs FREE-AIR TEMPERATURE
+VA = 5 V, +VBD = 3.3 V, External Reference
0
20
40
60
80
TA - Free-Air Temperature - C
Figure 20
Figure 21
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ADS8411
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OFFSET ERROR vs FREE-AIR TEMPERATURE
0.5 0.4 0.3 EO - Offset Error - mV 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -40 33.6 +VA = 5 V, +VBD = 3.3 V, External Reference 33.4 ICC - Supply Current - mA 33.2 33 32.8 32.6 32.4 32.2 32 -40
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
+VA = 5 V, +VBD = 3.3 V
-20 0 20 40 60 TA - Free-Air Temperature - C
80
-20 0 20 40 60 TA - Free-Air Temperature - C
80
Figure 22
DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE
2 3 Max
Figure 23
INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE
DNL - Differential Nonlinearity - LSBs
1.5
INL - Integral Nonlinearity - LSBs
2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 +VA = 5 V, +VBD = 3.3 V, Internal Reference
Max
1 0.5 0 -0.5 Min -1 -1.5 -40 +VA = 5 V, +VBD = 3.3 V, Internal Reference
Min
-20
0 20 40 60 TA - Free-Air Temperature - C
80
-2 -40
-20 0 20 40 60 TA - Free-Air Temperature - C
80
Figure 24
Figure 25
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ADS8411
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DNL
4 3
DNL - LSBs
2 1 0 -1 -2 -3 -4 0 16384 32768 Code 49152 65536
Figure 26
INL
4 3 2
INL - LSBs
1 0 -1 -2 -3 -4 0 16384 32768 Code 49152 65536
Figure 27
FFT
0 -20
Magnitude - dB
-40 -60 -80 -100 -120 -140 -160 -180 0 100 200 300 400 500 600 700 800 900 1000
Frequency - kHz
Figure 28
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ADS8411
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APPLICATION INFORMATION MICROCONTROLLER INTERFACING
ADS8411 to 8-Bit Microcontroller Interface Figure 29 shows a parallel interface between the ADS8411 and a typical microcontroller using the 8-bit data bus. The BUSY signal is used as a falling-edge interrupt to the microcontroller.
Analog 5 V
0.1 F AGND 10 F 1 F 0.1 F Ext Ref Input Analog Input +VA REFIN REFM AGND +IN -IN
Micro Controller GPIO GPIO P[7:0] RD GPIO INT CS
Digital 3 V ADS8411 BDGND BDGND +VBD 0.1 F
BYTE DB[15:8] RD CONVST BUSY
Figure 29. ADS8411 Application Circuitry (using external reference)
Analog 5 V
0.1 F 10 F
AGND
0.1 F 1 F REFOUT REFM +VA REFIN AGND
AGND
ADS8411
Figure 30. Use Internal Reference
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ADS8411
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PRINCIPLES OF OPERATION
The ADS8411 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on charge redistribution, which inherently includes a sample/hold function. See Figure 29 for the application circuit for the ADS8411. The conversion clock is generated internally. The conversion time of 360 ns is capable of sustaining a 2-MHz throughput. The analog input is provided to two input pins: +IN and -IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function.
REFERENCE
The ADS8411 can operate with an external reference with a range from 3.9 V to 4.2 V. A 4.096-V internal reference is included. When internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with an 0.1 F decoupling capacitor and 1 F storage capacitor between pin 2 (REFOUT) and pins 47 and 48 (REFM) (see Figure 33). The internal reference of the converter is double buffered. If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected (floating) if external reference is used.
ANALOG INPUT
When the converter enters the hold mode, the voltage difference between the +IN and -IN inputs is captured on the internal capacitor array. The voltage on the -IN input is limited between -0.2 V and 0.2 V, allowing the input to reject small signals which are common to both the +IN and -IN inputs. The +IN input has a range of -0.2 V to Vref + 0.2 V. The input span (+IN - (-IN)) is limited to 0 V to Vref. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8411 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25 pF) to an 16-bit settling level within the acquisition time (100 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1 G. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN and -IN inputs and the span (+IN - (-IN)) should be within the limits specified. Outside of these ranges, the converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output impedance of the sources driving +IN and -IN inputs are matched. If this is not observed, the two inputs could have different setting time. This may result in offset error, gain error and linearity error which varies with temperature and input voltage.
DIGITAL INTERFACE
Timing And Control See the timing diagrams in the specifications section for detailed information on timing signals and their requirements. The ADS8411 uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter. No external clock input is required. Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8411 switches from the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is important to the performance of the converter. The BUSY output is brought high after CONVST goes low. BUSY stays high throughout the conversion process and returns low when the conversion has ended. Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when BUSY is low.
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Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus with the conversion. Reading Data The ADS8411 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should be attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used for multiword read operations. BYTE is used whenever lower bits of the converter result are output on the higher byte of the bus. Refer to Table 1 for ideal output codes. Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION FULL SCALE RANGE Least significant bit (LSB) Full scale Midscale Midscale - 1 LSB Zero ANALOG VALUE Vref Vref/65536 Vref - 1 LSB Vref/2 Vref/2 - 1 LSB 0V DIGITAL OUTPUT STRAIGHT BINARY BINARY CODE 1111 1111 1111 1111 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 HEX CODE FFFF 8000 7FFF 0000
The output data is a full 16-bit word (D15-D0) on DB15-DB0 pins (MSB-LSB) if BYTE is low. The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15-DB8. In this case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on pins DB15-DB8, then bringing BYTE high. When BYTE is high, the low bits (D7-D0) appear on pins DB15-D8. These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity. Table 2. Conversion Data Readout
DATA READ OUT BYTE High Low DB15-DB8 Pins D7-D0 D15-D8 DB7-DB0 Pins All one's D7-D0
RESET
RESET is an asynchronous active low input signal (that works independently of CS). Minimum RESET low time is 25 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In addition, all output latches are cleared (set to zero's) after RESET. The converter goes back to normal operation mode no later than 20 ns after RESET input is brought high. The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling edge of CS, whichever is later. Another way to reset the device is through the use of the combination of CS and CONVST. This is useful when the dedicated RESET pin is tied to the system reset but there is a need to abort only the conversion in a specific converter. Since the BUSY signal is held high during the conversion, either one of these conditions triggers an internal self-clear reset to the converter just the same as a reset via the dedicated RESET pin. The reset does not have to be cleared as for the dedicated RESET pin. A reset can be started with either of the two following steps.
D Issue a CONVST when CS is low and a conversion is in progress. The falling edge of CONVST must satisfy the
timing as specified by the timing parameter tsu(AB) mentioned in the timing characteristics table to ensure a reset. The falling edge of CONVST starts a reset. Timing is the same as a reset using the dedicated RESET pin except the instance of the falling edge is replaced by the falling edge of CONVST.
D Issue a CS while a conversion is in progress. The falling edge of CS must satisfy the timing as specified by the
timing parameter tsu(AB) mentioned in the timing characteristics table to ensure a reset.The falling edge of CS
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causes a reset. Timing is the same as a reset using the dedicated RESET pin except the instance of the falling edge is replaced by the falling edge of CS.
POWER-ON INITIALIZATION
RESET is not required after power on. An internal power-on-reset circuit generates the reset. To ensure that all of the registers are cleared, the three conversion cycles must be given to the converter after power on.
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8411 circuitry. As the ADS8411 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the ADS8411 draws very little current from an external reference, as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-F bypass capacitor and a 1-F storage capacitor are recommended from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the same ground plane under the device. The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8411 should be clean and well bypassed. A 0.1-F ceramic bypass capacitor should be placed as close to the device as possible. See Table 3 for the placement of the capacitor. In addition, a 1-F to 10-F capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-F electrolytic capacitor or even a Pi filter made up of inductors and capacitors--all designed to essentially low-pass filter the 5-V supply, removing the high frequency noise. Table 3. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE SUPPLY PINS Pin pairs that require shortest path to decoupling capacitors Pins that require no decoupling CONVERTER ANALOG SIDE (4,5), (8,9), (10,11), (13,15), (43,44), (45,46) 12, 14 CONVERTER DIGITAL SIDE (24,25), (34, 35) 37
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