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Features
* * * * * * * * * * * * * * * * * * * * * * * * * * *
DAVIC/DVB(R)/ETS300.429/ITU-T J.83 Annex A, C Fully Compliant Direct IF Sampling (No Second IF Down Conversion Required) or Baseband Input Internal DC Offset Compensation 1024, 512, 256, 128, 64, 32, 16 QAM and QPSK Demodulation Roll-off Factor Adapted to Raised-cosine Filtered Signal (0.11 to 0.4) Fully Digital Timing Recovery Variable Symbol Rate Recovery Anti-aliasing Continuously Variable Digital Filtering with Symbol Rate Adaptive Bandwidth (1 to 18.75M Baud at the Same Sampling Frequency) Fully Digital Carrier Recovery (Coherent or Differential for QPSK) Robust Equalizer Acquisition Selectable Transversal or Decision Feedback Equalizer Dual Phase/Frequency Offset Recovery up to 12% of the Symbol Rate with No Degradation MPEG2 Frame Synchronization Reed-Solomon Decoder (204, 188, 8) De-interleaving (I = 12 and I = 17) Energy Dispersal Descrambling I2C Interface Switch for Separate Bi-directional I2C Bus-to-tuner to Avoid Phase Noise Problems Due to I2C Integrated Clock Reference for Tuner, Especially Designed for NIU in CAN Two AGCs: Analog and Digital Gains Three Program Identifier (PID) Filtering IRQ Interrupt Request Generation to Simplify Monitoring Bit Error Rate and Packet Error Rate Monitoring Signal-to-noise Ratio Estimation, Residual Phase Noise Estimation Automatic Spectrum Inversion JTAG Support 0.35 CMOS Technology, 3.3V Operation 100-lead TQFP Package
Digital Reception/ Transmission IC Integrated DVB(R)- compliant QAM Demodulator AT76C651
Description
The AT76C651 is a DVB-compliant Quadrature Amplitude Modulation (QAM) demodulation circuit, which can be used in DVB and other applications using Quadrature Phase Shift Keying (QPSK) or QAM transmission systems. The signal, after output from tuner and adjacent channels rejection filter, is externally sampled at IF frequency. The signal is converted to digital format by an analog-to-digital converter and goes through several processing steps required for demodulation: automatic gain control, baseband down conversion, timing recovery with anti-aliasing filtering, square root raised-cosine receive filtering, carrier recovery and digital gain control and equalization (linear and decision feedback dual structure). The output from demodulation then goes through forward error decoding: DVB/DAVIC de-mapping, frame synchronization, de-interleaving, Reed-Solomon decoding and spectrum de-randomization. The output before decoding may also be output directly for use with post-processing devices in applications other than DVB. An additional block situated in the back-end may be used to filter out programmable PIDs, providing additional flexibility in interactive solutions or DVB data-broadcast PC receive cards. It is especially designed for modem implementations with a 24-bit mask on one PID (medium access control) and can be used for return channel implementation.
Rev. 1293D-10/00
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Figure 1. Symbol of the AT76C651 QAM Demodulator
External A/D converter(s) IF (10 bits) I (6 bits) Q (6 bits) Signal Amplification Control
IFQBB3 IFQBB2 IFQBB1 IFQBB0 QBB1 QBB0
ADCLK
IFIBB5 IFIBB4 IFIBB3 IFIBB2 IFIBB1 IFIBB0
SMPLPHASE
AGC
RC
VDD
RESET* TESTADC Signal In PLLCTRL2 PLLCTRL1 PLLCTRL0
Control
CSTPWM
RC
Constant Voltage (IC Controlled)
IRQ
RC
LFTPLL TUNCLK
/n
QAM Demodulator
FLAGPID0 FLAGPID1
Quartz XO
XTAL_O XTAL_I XOCLK OSCMODE I2CSCL I2CSDA
I2CADDR1 I2CADDR0
Osc PLL
Ref_Clk Indicators FRMVALID FRMSTART DATAVALID
IC
Configuration LOCK1 LOCK2 CORFAIL CORBYTE Output Data
TDI TMS TCK TRST
JTAG
Test Interface
DATAOUT0 DATAOUT1 DATAOUT2 DATAOUT3
TESTMODE
MPEG2-TS Output or I/Q Constellation
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DATAOUT4 DATAOUT5 DATAOUT6 DATAOUT7
TDO
PHASYM ENSYM
REF2CLK
TI2CSCL
TI2CSDA
AT76C651
Table 1. Signal Description
Signal Name
I2CADDR I2CSDA I2CSCL TI2CSDA TI2CSCL IFIBB IFQBB QBB PLLCTRL XOCLK XTAL_I XTAL_O OSCMODE LFTPLL TESTADC ADCLK SMPLPHASE TDI TDO TMS TCK TRST DATAOUT CORFAIL CORBYTE DATAVALID FRMSTART FRMVALID FLAGPID IRQ LOCK1 LOCK2 CSTPWM AGC TUNCLK REF2CLK PHASYM ENSYM
Function
I C circuit address selection SDA line of I C SCL line of I C I C bus data line SDA to/from tuner through bi-directional switch I C bus clock SCL to tuner through switch IF 6 MSBs or I-baseband digital input IF 4 LSBs or Q-baseband digital input 4 MSBs Q-baseband digital input (2 LSBs) PLL division/bypass control Crystal oscillator input Crystal input Crystal output Oscillator input mode (0 for crystal, 1 for XO) Low pass filter input to PLL A/D test pin (must be connected to VDD3 in standard operation) Sampling clock for external A/D converter External A/D sampling phase JTAG JTAG JTAG JTAG JTAG MPEG2-TS parallel byte <0:7> or serial bit stream output <0> RS packets not corrected Corrected byte indicator MPEG2-TS byte or bit output enable active at level 0 or on both edges Start of MPEG2-TS frame Valid MPEG2-TS frame control in parallel mode output PID filtering indicator Interrupt request Maskable lock signal 1 Maskable lock signal 2 Configurable value output with PWM Analog automatic gain control PWM 4 MHz reference oscillator output to tuner Half digital clock Test output signal Test output signal
2 2 2 2 2
Number of I/Os
2 1 1 1 1 6 4 2 3 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1
Pull-up
No R = 15 k No R = 15 k No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No
Voltage
VDD3 VDD5 VDD5 VDD5 VDD5 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD5 VDD5 VDD5 VDD3 VDD3 VDD3
Direction
I I/O I I/O O I I I I I I O I A I O I I O I I I O O O O O O O O O O O O O O O O
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Table 1. Signal Description (Continued)
Signal Name
GND I2CGND VDD I2CVDD TESTMODE RESET
Function
Ground I C ground +3.3V supply I2C power supply Test pin Hard reset of circuit
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Number of I/Os
Pull-up
Voltage
Direction
GND GND
VDD3 VDD5 1 1 No No VDD3 VDD3
PWR PWR I/O I
Figure 2. Block Diagram of the AT76C651
Digital In (IF or BB)
DDS Baseband Conversion
Timing Recovery & Continuous Variable Filtering
Sq. Root Nyquist
AGC2 Digital
Equalizer LE/DFE
PWM
AGC1 Analog
De-interleaver (I=12/I=17)
Frame Synchro
Symbol Detection & DVB/DAVIC De-mapping
Carrier Recovery
I2C Interface ReedSolomon Decoder (204, 188, 8) Spectrum Descrambler PID Filtering MPEG-TS Output Parallel & Serial (Common Interface)
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AT76C651
Functional Description
The following sections describe the main functions of all blocks included in the AT76C651 QAM demodulation IC. which controls the analog gain. The PWM output generates a very stable control. Since power estimation is done by digital loop control, only the output is given in PWM format for simpler implementation on board (only an RC filter with about 1 kHz cut-off bandwidth is required), whose frequency is fPWM = fREF/2. The power estimation is made over the entire signal sampled by the ADC, thus including the adjacent channels and the target signal. This ensures that no analog saturation can happen due to the AGC feedback. Also, the power estimation of the analog gain control can be used in conjunction with the AGC2 level (which indicates the power of the QAM signal only) in order to compute the power of adjacent channels. This may be used to adjust the takeover point (TOP) of external amplifiers when several amplifiers are required on the board (typically in the tuner and after the SAW filter). Note that an I2C-controllable PWM is available for this purpose.
Interface to A/D Converter (ADC)
A 10-bit external A/D converter must be connected to the AT76C651 in case of a signal in IF frequency. The sampling clock of the ADC must be taken on pin ADCLK of the chip. The digital outputs of the external ADC must connect input IFIBB5 to IFIBB0 and input IFQBB3 to IFQBB0 (MSB to LSB). The pin SAMPLEPHASE can be used to select the phase of the internal resampling clock, depending on the external ADC propagation delay (see "Timing Waveforms" on page 35). In case of a signal in baseband, two external 6-bit ADCs must be used. The sampling clock of the ADCs must be taken on pin ADCLK of the chip. The digital outputs of the ADCs must connect input IFIBB5 to IFIBB0 for I input and input IFQBB3 to IFQBB0 and QBB1 to QBB0 for Q input (MSB to LSB). SAMPLEPHASE should be connected as decribed in the previous paragraph. The sampling clock frequency (on ADCLK) is equal to the input frequency if the PLL is used (either with a crystal or a crystal oscillator XO) or half the crystal frequency if the PLL is bypassed (see "Oscillator and Phase Locked Loop" on page 7). Two examples: If a 28 MHz crystal is used, the sampling frequency is 28 MHz; if a 60 MHz XO is used, the sampling frequency is 30 MHz.
Digital Timing Recovery
The baseband conversion output is then fed to the timing recovery block. This block integrates a digital timing loop, which estimates the best resampling time. This information is provided to a time-continuous filter, which interpolates the baseband signal and produces QAM symbols at the recovered symbol rate. The interpolating filter's main property is its continuously autoadaptive bandwidth, which allows the demodulator to recover a wide range of symbol rate 1/TS with the same perfomance and avoids signal aliasing during resampling operation.
DC Offset Control
An internal DC-offset compensation is done on the I and Q baseband signals in order to compensate potential offsets created by A/D converters.
Square Root Raised-cosine Nyquist Receive Filter (SRRC)
The SRRC filter, with roll-off factor allowing demodulation of raised-cosine transmitted signals from 0.11 to 0.4, receives the signal from the timing recovery output and ensures an out-of-band rejection higher than 43 dB. This significant rejection increases the back-off margin of the receiver against adjacent channels.
Direct Digital Synthesizer (DDS) - Coarse Tuning
An IF to baseband conversion from FO is then performed. The frequency FO is configurable, which reduces the constraint on the relation between the SAW filter center frequency and the chip oscillator. The frequency of the DDS is further adjusted by the carrier frequency recovery in order to adjust exactly the received spectrum to the receive filter.
Digital Automatic Gain Control (AGC2)
The internal digital AGC performs a fine adjustment of the signal level at the equalizer input. This AGC only takes into account the QAM signal itself, since adjacent channels have been filtered out by the SRRC, and thus compensates digitally the analog AGC, which may have reduced the input power due to adjacent channels.
"Analog" Automatic Gain Control (AGC1)
The signal level at the ADC input is adjusted through a first AGC loop. The power estimation block estimates the signal level at the output of the ADC, compares it to a given level and generates a Pulse Width Modulation (PWM) signal,
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Equalizer
The equalizer is based on algorithms that provide blind and robust acquisition. The equalizer compensates for the different impairments encountered on the network. Two equalizer structures can be selected: transversal (powerful for long echoes) or decision feedback (powerful for strong short echoes). The equalizer central tap position is configurable. This allows an optimal compensation for post and pre-cursor echoes. The equalizer comprises 32 taps, which represents a length of about 6.2 microseconds at 5M bauds. This allows a large compensation for echoes with significant delays, and a total compensation for significant (small attenuation) short echoes.
Symbol Detection and DVB/DAVIC Demapping
The output is fed to the symbol threshold detector, then to the differential decoder and finally to the DVB or DAVIC de-mapper, which produces the recovered bit stream sent to the Forward Error Correction (FEC).
Frame Synchronization
The first function performed by the FEC is the frame synchronization. The bit stream is decomposed into packets of 204 bytes at the output, starting with a frame synchronization word.
De-interleaving
The packets are then de-interleaved. Two depths can be selected for the interleaver: 12 (DVB/DAVIC) and 17. The depth 17 increases the robustness of the system against impulse noise but assumes the signal has been interleaved with the same value as the modulator.
Carrier Recovery - Fine Tuning
The carrier recovery block allows the acquisition and tracking of a frequency offset as high as 12% of the symbol rate, even for low signal-to-noise ratios. The phase comparator algorithm provides a high-phase noise tolerance, which reduces the tuner cost. The frequency offset recovered by the chip can be monitored through the I2C interface. This information can be used to readjust the tuner frequency in order to reduce the analog filtering degradation on the signal and thus improves the bit error rate. This information is also provided automatically to the DDS in order to recover the frequency with complete accuracy before receive filtering.
Reed-Solomon Decoder
The de-interleaved output is sent to the Reed-Solomon (RS) input, which performs a correction of a maximum of eight errors (bytes) per packet. The RS also provides other information regarding the uncorrected packets and the position of the corrected bytes in the packet, if there are any.
Differential Demodulation for QPSK
A differential demodulation can be used in a strongly distorted environment in the case of differentially encoded QPSK demodulation. This mode provides a stronger robustness against phase noise but reduces the performance of the receiver by 3 dB, as shown in theory. I 2 C register QAMSEL must be configured to set this mode.
Spectrum Descrambler
After RS decoding, the packets are descrambled for energy dispersal removal.
PID Filtering
A Program Identifier (PID) filtering can be performed on the MPEG2 Transport Stream (TS) before feeding the packets to the output. Three PIDs can be selected at the same time. This block outputs an enable signal on the packet stream that goes to the component interfaced with the QAM demodulator. This provides an interesting feature for onboard PC implementations, where either data or video and audio are processed directly by the PC processor. A mask is provided for one of the PIDs, offering a filter on the overall MPEG-TS packet header. Note that one of the PIDs can be selected, so that a special enable output can be used to filter out all MPEG-TS packets containing MAC messages (for in-band return channel implementations of the DVB-RC specification). This stream contains all the control information for the return channel, and is required by other components used for the return channel.
Phase and Additive Noise Estimation
Phase noise and additive noise estimations are performed. This information can be used to select the best carrier loop bandwidth giving the best trade-off between phase noise and additive noise. The phase noise can come from the tuner and/or the LNB in MMDS application. This feature can also be used to remotely monitor the various problems encountered by an STB or cable modem at the user installation.
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AT76C651
Interrupt Request (IRQ)
An interrupt request can be generated by the AT76C651 device when configurable events occur. This is controlled by the I2C registers IRQMASK and OUTPUTCFG. The internal reference clock of the chip is generated by using an internal PLL and its frequency is given by: n f REF = -- f XTAL with n = 2, 4, 5, 6, 7 2 The frequency f REF is the maximum output bit rate supported by the device and must be less than 80 MHz (see "Symbol Rate" on page 13). The value n is configured by the PLLCTRL2, PLLCTRL1 and PLLCTRL0 input pins, as shown in Table 2. Table 2.
PLLCTRL2 n=2 n=4 n=5 n=6 n=7 Note: 1 0 0 0 0 Other cases for test only. PLLCTRL1 0 0 0 1 1 PLLCTRL0 0 0 1 0 1
MPEG2-TS Output Interface
The output of the FEC is made up of MPEG2 Transport Stream (TS) packets. The output can be either parallel or serial on DATAOUT. The data is present on either edge or low state of the DATAVALID pin in output mode. In serial output mode DATAOUT (7) to DATAOUT (1) are individually valid, with each bit output in serial mode (see "Timing Waveforms" on page 35).
Oscillator and Phase Locked Loop
The fully digital clock and carrier recovery eliminates the need to implement external VCOs and VCXOs and thus reduces the total function cost. Only a simple crystal oscillator is needed by the chip to perform all the demodulation functions with variable symbol rate. Two configurations are possible: 1. A crystal can be connected to the XTAL_I and XTAL_O pins of the chip with frequency: 25 MHz f XTAL 30 MHz Values may depend on crystal characteristics. See Figure 3, where R = 12 kOhms and C = 20 pF. Figure 3.
GND C XTAL Unit
The value n = 2 allows to input directly the reference clock at frequency fREF (bypass the PLL). The PLL pin LFTPLL must be connected to an RC filter as shown in Figure 4. Values of resistance and capacitors should be R = 25, C = 100 nF, and C2 = 20 nF. Figure 4. RC Filter Connection to PLL Input of Device
LFTPLL
R
C
C2
R
XTAL_O
XTAL_I
AT76C651
2. A crystal oscillator (XO) can be connected directly to the XOCLK input pin, with frequency: f XTAL 80 MHz In case of a crystal, the OSCMODE pin is connected to GND. In case of an XO, it must be connected to VDD. The crystal must be first order, serial resonance and have a load capacitance of 10 pF. The internal oscillator of the chip provides a direct, jitterfree clock used to sample the input signal of external ADC. This clock is available on the output pin ADCLK.
A separate TUNCLK output pin provides a fraction of the crystal frequency given by: 1 f TUNCLK = -- f XTAL with p = 2, 4, 8 p which can be used as a reference for the tuner oscillator or any other reference frequency on the board. The value p is configured by the I2C register, OUTPUTCFG (page 23). WARNING: Performance in 256-QAM may be affected by the jitter on the oscillator. It is preferable to use an external crystal oscillator if 256-QAM is required in the final application. Atmel does not guarantee the BER specifications given on page 20 and page 21 if a crystal is used on its own.
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JTAG
A JTAG controller compatible with IEEE Std. 1149.1 is provided in the device. The pin TRST must be connected to a pull-down on the board in order to have it connected to GND during functional operation of the chip. The JTAG provides a boundary-scan chain on the pinout of the chip. The following instructions are available: * BYPASS: The chip remains in functional mode and a single BYPASS register is connected between TDI and TDO. The bit code of this instruction is 11. * SAMPLE/PRELOAD: The chip remains in functional mode and the boundary-scan register is connected between TDI and TDO. The bit code of this instruction is 01. * EXTEST:The chip is in external boundary-test mode and the boundary-scan register is connected between TDI and TDO. The bit code of this instruction is 00. * IDCODE: The chip is in functional mode and the device identification register is connected between TDI and TDO. The bit code of this instruction is 10. The device identification register is 32 bits long and contains the value 0x00280B8F.
Special I/O Description
Special I/Os that are not described elsewhere in this specification are described in this section. * OSCMODE: When set to 1, a crystal oscillator is used. When set to 0, a crystal is used. * TEST: Three test pins are available on the chip for testing. 1. TESTMODE: Input test pin, connected to GND 2. PHASYM: Output test pin, not connected 3. ENSYM: Output test pin, not connected * REF2CLK: Clock output test pin, not connected
I2C Control
The chip is controlled entirely via an I2C interface. The chip address can be modified by connecting the I2CADDR pins to GND or VDD3 to select the two LSBs of the address. The chip address is:
0 0 0 1 1 ADDI2C(1) ADDI2C(0)
I2C Write Mode Registers can be written using a standard I 2 C bus with clock SCL and data SDA as described by "The I2C-bus and how to use it", Philips Semiconductors (April 1995). The protocol used to write into I2C registers is described by the frame shown below.
S
chip address
0 (Write)
A
register address
A
data 1
A
...
data n
A
P
S = Start A = Acknowledge bit P = Stop
to chip
* data 1 is written at register address * data 2 is written at register address + 1 * ... * data n is written at register address + (n - 1) It is therefore possible to configure several successive registers with a single I2C frame (from first Start to Stop).
from chip
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AT76C651
I2C Read Mode Register values can be read from the chip by transmitting the following frames on the I2C bus.
S S chip address chip address 0 (Write) 1 (Read) A A register address data X2 A A ... S chip address S chip address 1 (Read) A data X1 A data Xn A A or A P
1 (Read)
* data X1 is read from register address * data X2 is read from register address + 1 * ... * data Xn is read from register address + (n - 1) It is therefore possible to read from several successive registers with a single I2C frame (from first Start to Stop). Note that multiple byte registers must be read MSB/low address first. All LSBs of the complete data are memorized only at the time when MSBs are read and do not change during readings of LSBs.
Switch for Tuner I2C Bus In order to avoid phase noise created by the I2C bus on the tuner, an active bi-directional switch provides a separate I2C bus for tuner configuration. For this purpose, the I 2 C bus to the tuner must be connected to the AT76C651 TI2CSCL and TI2CSDA pins (see Figure 1). The I 2 C register called TUNI2CADD (see I 2 C registers table) must be configured with the I2C address of the tuner. The switch between the normal I2C bus and the tuner I2C bus can be enabled or disabled using the LSB of TUNI2CADD. When disabled, TI2CSCL/TI2CSDA lines are isolated from I2CSCL/SI2CDA. When enabled, the switc h c opies I2CSDA to/from TI2CSDA when data is transmitted to/from the tuner. The switch should be enabled by the microcontroller only when the tuner is being configured.
Figure 5. I2C Connection between AT76C651, Tuner and Microcontroller
Tuner SCL SDA
AT76C651 TI2CSCL I2CSCL TI2CSDA I2CSDA
Microcontroller SCL SDA
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Automatic Configuration
In order to configure the chip, the following actions are required: * Hard reset of chip * Configure registers SYMRATE (symbol rate), QAMSEL (QAM modulation type) and BBFREQ (IF frequency) * Write value 0x01 into SETAUTOCFG in order to automatically configure all other registers * Optionally modify some register values, if required * Write value 0x01 into RESTART in order to restart the chip with the new values The automatic configuration of all registers as a function of the QAM modulation, symbol rate and IF frequency offers a very simple use of the chip with a basic software driver.
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AT76C651
Table 3. I2C Registers List
Address General 0x00 to 0x02 0x03 0x04 - 05 0x06 0x07 0x08* 0x09* 0x0A* 0x0B* 0x0C* 0x0E - 0x0F W/R W/R W/R W W W/R W/R W/R W/R W/R R SYMRATE QAMSEL BBFREQ SETAUTOCFG RESTART OUTPUTCFG MASKLOCK1 MASKLOCK2 IRQMASK TUNI2CADD CHIPID Symbol rate QAM selection (and mapping type, DVB and others) IF input frequency Sets automatic configuration of all parameters (see Note) Restart chip without modifying configuration parameters Select MPEG2 or other internal signals for test output Mask for lock 1 signal output Mask for lock 2 signal output Events mask for interrupt request generation Tuner I2C address for use of specific tuner I2C bus Chip ID and version R/W Name & Function Meaning
Baseband Conversion and AGC1 0x13* 0x14* 0x15* 0x17* 0x19 Timing Recovery 0x23 - 0x24* 0x29 Carrier Recovery 0x31* 0x32* 0x33* 0x34* 0x39 - 0x3B AGC2 0x42* 0x43 - 0x44* W/R W/R AGC2CFG AGC2INIT AGC2 configuration AGC2 initial value W/R W/R W/R W/R R CARALPHAACQ CARBETAACQ CARALPHATRACK CARBETATRACK CARCONST Alpha parameter of loop bandwidth during acquisition phase of carrier Beta parameter of loop bandwidth during acquisition phase of carrier Alpha parameter of loop bandwidth during tracking phase of carrier Beta parameter of loop bandwidth during tracking phase of carrier Constellation points after carrier recovery W/R R TIMLOOPCFG TIMLOOPMONIT Configuration of initial loop parameters Variable loop bandwidth value W/R W/R W/R W/R R AGC1NMIN AGC1NMAX BBCFG CSTPWM BBTOPCNT Minimum value authorized for AGC value Maximum value authorized for AGC value General configuration of baseband block Constant value for PWM output A/D saturation rate over 16384 successive samples
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Table 3. I2C Registers List (Continued)
Address Equalizer 0x51* 0x52* 0x53* 0x54 - 0x55 0x56 - 0x57 FEC 0x60* 0x61* 0x62* 0x63* 0x64* 0x65* PID Filtering 0x70 - 0x71* 0x72 - 0x73* 0x74 - 0x76* 0x77 - 0x79* General Monitoring 0x80 0x81 - 0x83 0x84 0x85 0x86 - 0x88 0x89 - 0x8A 0x8B - 0x8C 0x8D - 0x8E 0x8F - 0x90 0x91 R R R R R R R R R R LOCK BER1 BER2 NPERR TIMFREQOFF DDSFREQOFFSET CARFREQOFFSET PHASENOISE ADDITIVENOISE AGC1LEVEL Lock status of AGC1, AGC2, TIMING, CARRIER, EQUALIZER, FEC Bit error rate estimate Bit error rate estimate based on frame synchronization word Number of uncorrectable frames Symbol rate frequency offset with respect to SYMRATE Frequency offset recovered by DDS Residual frequency offset (normalized to symbol rate) Phase noise estimation Additive noise estimation AGC1 current value (external) W/R W/R W/R W/R PID1 PID2 PID3 PIDMSK3 First PID filter Second PID filter Third MPEG-TS header filter Mask for third MPEG-TS header filter W/R W/R W/R W/R W/R W/R FECIQINV FECFLEN FECFSW FECDILVILEN FECDILVMLEN FECDINH I/Q invert mode Frame length Frame synchronization word Number of branches in interleaver Memory step size of interleaver FEC inhibitions configuration W/R W/R W/R R R EQUCFG EQUCENTRAL EQUTAPTORD EQUTAPREAL EQUTAPIMAG Equalizer configuration Central tap configuration Coefficient to monitor Real part of selected tap Imaginary part of selected tap R/W Name & Function Meaning
0x92 - 0x93 R AGC2LEVEL AGC2 current value (internal) Note: All parameters identified by * are automatically configured when writing 0x01 into SETAUTOCFG register.
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AT76C651
Performance Specification
Modulation
Supports QPSK and 16, 32, 64, 128, 256, 512, 1024 QAM. Up to fXTAL/(2(1 + )) (13M baud for fREF = 30 MHz, = 0.15) with IF input, 16-taps equalizer. Up to fREF/4 (18.75M baud for fREF = 75 MHz, fXTAL = 30 MHz) with baseband input, 16-taps equalizer. Note however, that the standard MPEG2-TS frame recovery and forward error correction part of the chip can only be used when bitrate =fREF. It is possible to use the constellation mode in the opposite case in order to use the demodulation part of the chip only and receive the symbols at the output. (See OUTPUTCFG register I2C to configure this operating mode.)
Roll-off Factor
Greater than 0.11.
Symbol Rate
Up to fREF/8 (9.36M baud for fREF = 75 MHz, fXTAL = 30 MHz) with IF or baseband input, 32-taps equalizer. Table 4.
Bandwidth 6 MHz 8 MHz fXTAL = fADCLK 25 MHz 28.9 MHz DDS freq 2x25-44 = 6 MHz 36-28.9 = 7 MHz
n (CTRLPLL) 4 4
fREF 50 MHz 57.8 MHz
Dsym_max 50/8 = 6.25 Mbd 57.8/8 = 7.225 Mbd
Bit Error Rate
Figures in the section "Bit Error Rate Measurements (Uncoded)" on page 20 indicate Bit Error Rate (BER) as a function of carrier-to-noise ratio (C/N) for different QAM modulations schemes. Theoretical curves are given to indicate how much degradation is observed with the real performance of the chip. Table 5 indicates the degradation from theory (implementation margin) for uncoded QAM at BER = 10-4. Table 5.
Modulation Scheme QPSK QAM-16 QAM-32 QAM-64 QAM-128 QAM-256 QAM-512 QAM-1024 C/N Degradation at BER = 10-4 0.1 dB 0.2 dB 0.2 dB 0.2 dB 0.3 dB 0.4 dB 0.5 dB 0.7 dB
Echo Cancellation
Table 6 indicates the additional degradation between use of a theoretical equalizer and the real chip equalizer, for uncoded QAM at BER = 10 -4, when the channel has the transfer response shown in Figure 6. Table 6.
Modulation Scheme QPSK QAM-16 QAM-32 QAM-64 QAM-128 QAM-256 QAM-512 QAM-1024 C/N Degradation at BER = 10-4 0.3 dB 0.3 dB 0.3 dB 0.3 dB 0.3 dB 0.3 dB 0.3 dB 0.4 dB
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Figure 6. Received Spectrum Used to Measure Degradation with Echoes
Phase Noise Tolerance
Table 7 indicates the additional degradation when a phase noise of -80 dBc at 10 kHz is present after the tuner, for uncoded QAM at BER = 10-4. Table 7.
Modulation Scheme
QPSK QAM-16 QAM-32 QAM-64 QAM-128 QAM-256 QAM-512 QAM-1024
AM Hum Tolerance
Input amplitude variation of 20% peak-to-peak can be supported by the demodulation at frequencies 100 - 120 Hz.
Locking Time
* 5 to 10 ms, when no echoes are present
C/N Degradation at BER = 10-4 0.1 dB 0.1 dB 0.1 dB 0.1 dB 0.1 dB 0.1 dB 0.3 dB 0.9 dB
* 20 ms typical when echoes are present (see Figure 6)
Carrier Offset
Up to 12% of the symbol rate: 1 MHz at 8M baud.
Timing Offset
Up to 4000 ppm of the symbol rate (30 kHz at 8M baud).
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Electrical Characteristics
Table 8. Electrical Specification - Recommended Operating Conditions
Symbol VDD5 VDD3 VSS TEMP Parameter I2CVDD, I C DC supply voltage VDD, DC supply voltage GND, I2CGND Operating free air temperature range Commercial 0
2
Conditions I C and AGC1 I/Os Core and standard I/Os
2
Min VDD3 3.0
Typ 5 3.3 0
Max 5.5 3.6
Unit V V V
+70
C
Table 9. Absolute Maximum Ratings - Before Damage
Symbol VDD3 VI Parameter DC supply voltage DC input voltage, 3.3V I/Os DC input voltage, 5V I/Os VO DC output voltage, 3.3V I/Os DC output voltage, 5V I/Os TEMP Operating free air temperature range Commercial Conditions Core and standard I/Os Min -0.3 -0.3 -0.3 -0.3 -0.3 0 Max 4.6 VDD3 + 0.3, 4.6 max VDD5 + 0.3, 5.5 max VDD3 + 0.3, 4.6 max VDD5 + 0.3, 5.5 max +70 Unit V V V V V C
Table 10. DC Characteristics for Pins Using VDD3 - CMOS Technology
Symbol TEMP VIL VIH VOL VOH CI Parameter Temperature Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage Input capacitance Guaranteed input low voltage Guaranteed input high voltage IOL = 0.3mA IOH = 0.3mA 3.0 to 3.6 3.0 to 3.6 3.0 3.0 VDD3 VDD3 - 0.1 6 (typ) Conditions VDD Min 0 -0.3 +0.7 x VDD3 Max +70 0.3 x VDD3 VDD3 + 0.1V VSS + 0.1V Unit C V V V V pF
Table 11. DC Characteristics for Pins Using VDD5
Symbol VIL VIH VOL VOH Parameter Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage Conditions Guaranteed input low voltage Guaranteed input high voltage IOL = 2mA IOH = 2mA VDD5 - 0.4 Min -0.3 2.0 Max +0.8 VDD5 + 0.3 0.4 Unit V V V V
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Schematic Diagrams
Figure 7. Standard Use of AT76C651 in Set Top Box Front End
Tuner
ADC DVB/PAL/NTSC Downconverter
AT76C651 QAM DEMODULATOR
DVB
MPEG2
VID
Xtal
SND
Analog AGC
Figure 8. Simplified Use of AT76C651 when No Analog TV Demodulation Required
Tuner
AT76C651 QAM DEMODULATOR
ADC
DVB
MPEG2
Xtal AGC
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Packaging Information
100-lead TQFP package. Commercial temperatures: 0 to 70C. Thermal resistance of the package: 40C/W. Figure 9. Package Outline
VDD TESTMODE PLLCTRL2 PLLCTRL1 PLLCTRL0 RESET* ADCLK REF2CLK TESTADC GND VDD PHASYM ENSYM GND VDD GND IFIBB5 IFIBB4 IFIBB3 IFIBB2 GND IFIBB1 IFIBB0 VDD GND 88 76
VDD VDD OSCMODE LFTPLL XOCLK XTAL_I XTAL_O GND NC NC NC NC NC I2CVDD TUNCLK CSTPWM AGC I2CSCL I2CSDA TI2CSCL TI2CSDA I2CGND VDD TDI GND
1
12
63
GND VDD TMS TCK GND
26
FLAGPID0 FLAGPID1 GND
38
51
GND IFQBB3 IFQBB2 IFQBB1 VDD IFQBB0 QBB1 QBB0 VDD GND GND VDD SMPLPHASE LOCK1 GND VDD LOCK2 CORFAIL CORBYTE GND FRMVALID FRMSTART DATAVALID DATAOUT7 VDD
VDD DATAOUT0 DATAOUT1 DATAOUT2 DATAOUT3 GND VDD DATAOUT4
TRST TDO I2CADDR1 I2CADDR0 VDD IRQ
Note:
The I/Os located between pins I2CVDD (14) and I2CGND (22) must use VDD5 voltage. All other I/Os must use VDD3 voltage.
DATAOUT5 DATAOUT6 VDD
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Figure 10. 100-lead TQFP Package
aaa
bbb
PIN 1
2 S
ccc
3
ddd
R1
1
R2 0.25
c
c1 L1
Table 12. Lead Count Dimensions (mm)
Pin Count 100 D/E BSC 16.0 D1/E1 BSC 14.0 b Min 0.17 Nom 0.22 Max 0.27 Min 0.17 b1 Nom 0.2 Max 0.23 e BSC 0.50 ccc 0.10 ddd 0.06
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Table 13. Common Dimensions (mm)
Symbol c c1 L L1 R2 R1 S q 0.08 0.08 0.2 0 0 11 11 12 12 13 13 1.6 0.05 1.35 1.4 0.15 1.45 3.5 7 Min 0.09 0.09 0.45 0.6 1.00 REF 0.2 Nom Max 0.2 0.16 0.75
1 2 3
A A1 A2
Tolerances of Form and Position aaa bbb 0.2 0.2
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Bit Error Rate Measurements (Uncoded)
Figure 11. QAM-64
Figure 12. QAM-256
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AT76C651
Figure 13. QAM-1024
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Configuration and Monitoring Registers
Description
The AT76C651 device is controlled by an I C interface. Most internal registers are in read/write mode (configuration registers). However, monitoring registers are in readonly mode. Note also that two special registers are writeonly: SETAUTOCFG and RESTART. In most applications, very few of these registers need to be configured since the SETAUTOCFG can be used. Some registers are not described in this document. They are used internally and should not be written with a different value after SETAUTOCFG; otherwise performance degradation may result. This means that no other address than the ones specified in this document should be used in I2C write mode. Also, reserved bits in a register should always be written with the value 0.
2
Example: For a 30 MHz crystal and pllctrl = 5, fREF = 75 MHz A symbol rate of 5M bauds gives: exponent = 6 (0x6) mantissa = 1 118 481(0 x 11 11 11) So the register value is 0x 88 88 8E. A symbol rate of 6.875M bauds gives: exponent = 6 (0x6) mantissa = 1 537 911(0 x 17 77 77) So the register value is 0 x BB BB BE (default value). QAMSEL: 0x03 (read/write) Specifies the used modulation scheme. This register indicates the number of QAM levels and other parameters such as the used mapping type (DVB or others), whether coherent demodulation or differential demodulation is used for QPSK, and whether intermediate frequency (IF) or baseband (BB) input is used.
b7 0x03 ifor bb b6 dem typ b5 b4 b3 b2 b1 b0
General Registers
SYMRATE: 0x00 to 0x02 (read/write) Transmission symbol rate, fSYMBOL, registers give the initial symbol rate of the timing recovery algorithm. A maximum offset of 4000 ppm between the actual symbol rate and this value can be tolerated by the device. The internally compensated frequency offset can be monitored in the register TIMFREQOFF. The symbol rate is given as a fraction of the REFCLK frequency. The value must be given with a mantissa (21 bits) and an exponent (3 bits).
b7 0x00 0x01 0x02 b6 b5 b4 b3 b2 b1 b0
maptyp
qamtyp
* iforbb: 0 for IF input signal, 1 for BB input signal * demtyp: 0 for coherent demodulation, 1 for differential demodulation (in QPSK only) * maptyp: 00 for DVB mapping, 10 for DAVIC mapping, other values reserved * qamtyp: Number of bits to specify a QAM symbol. Example: 2 for QPSK, 4 for QAM-16, 5 for QAM-32, 6 for QAM-64, 7 for QAM-128, 8 for QAM-256, 9 for QAM-512, 10 for QAM-1024 (0, 1, 3, and greater or equal to 11 are reserved values.)
mantissa (20:13) mantissa (12:5) mantissa (4:0) exponent (2:0)
To compute these values, the following equations can be used: f XTAL with pllctrl = 2 ,4 ,5 ,6 ,7 f REF = ae -------------o pllctrl e2 f symbol exponent = 10 + floor ae log 2 ae ---------------- o o e e f REF o f symbol 30 - exp onent mantissa = ae ----------------o 2 e f REF o
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BBFREQ: 0x04 to 0x05 (read/write) Intermediate frequency to baseband-down conversion frequency registers indicate the initial frequency used to down-convert the signal from IF to BB. The value is between 0 and fADCLK/2, where fADCLK is the sampling frequency of the ADC. A maximum offset between the actual IF and this value of 12% of the symbol rate can be tolerated by this device. This offset can be monitored in the DDSFREQOFFSET and CARFREQOFFSET registers.
b7 0x04 0x05 b6 b5 b4 b3 b2 b1 b0 bbfreq1 (15:8) bbfreq0 (7:0)
Note:
Table 14.
Register 0x10 0x11 0x15 0x20 0x24 0x30 0x35 0x37 1. In 32-QAM only. Value 0x06 0x10 0x28 0x09 0x90 0x94 0x2A(1) 0x13(1)
The frequency is computed by: f IF Example: For a 30 MHz crystal and a signal at IF frequency fIF = 6 MHz, bbfreq1 = 51 (0x33) and bbfreq0 = 51 (0x33). Note also that subsampling can be used with this device. This means that the IF can be greater than the sampling frequency of the signal. For example, it is possible to have a sampling frequency fADCLK = 30 MHz, and the IF at fIF = 36 MHz. In that case, an image of the spectrum after sampling is present at fIF2 = 36 - 30 = 6 MHz, thus the content of BBFREQ should correspond to fIF2. SETAUTOCFG: 0x06 (write-only) The automatic configuration address, when written with the value 0x01, automatically updates all registers of the device except for SYMRATE, QAMSEL and BBFREQ, which remain the same. All values are derived from these non-modified registers, thus offering a very straightforward configuration of the entire device without necessarily understanding the meaning of all other parameters. However, if necessary, it is possible to modify some register values after having used SETAUTOCFG. In order to optimize the performance of the IC, the following values must be written into the IC after SETAUTOCFG has been performed. bbfreq1 x 256 + bbfreq0 = ---------------------------------------------------------------- x f ADCLK 65536
RESTART: 0x07 (write-only) This address, when written with the value 0x01, restarts the device without modifying the content of I2C registers. All recovery loops (AGC, timing, carrier) and the equalizer restart from their initial value. This should always be done after a SETAUTOCFG or any reconfiguration of I 2 C registers. OUTPUTCFG: 0x08 (read/write) The data output configuration register configures the output format on pins DATAOUT7 to DATAOUT0 of the device.
b7 0x08 b6 b5 b4 b3 irq pol b2 b1 b0
reserved
tundiv
outputmode
* tundiv specifies the frequency of the clock signal output on TUNCLK pin. The frequency of this clock is given by: TUNDIV + 1 1 f TUNCLK = -- f XTAL with p=2 p So p can take the values: 2, 4 or 8. When tundiv = 3, there is no output on TUNCLK pin in order to reduce power consumption if not needed. * outputmode can take the following binary values: 000: MPEG2-TS parallel (DVB common interface) 001: MPEG2-TS serial 010: Constellation before decision 011: I output after AGC1 and baseband conversion 100: I output after timing recovery 101: I output after A/D sampling * irqpol configures the polarity of the IRQ output pin: 0: IRQ is in high impedance or has value 0 when interruptions occur (see IRQMASK register).
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1: IRQ is in high impedance or has value 1 when interruptions occur (see IRQMASK register). Example: 0x0 configures MPEG2-TS parallel output with IRQ going low when interruptions occur. The default value after SETAUTOCFG is 0x30. MASKLOCK1: 0x09 (read/write) This register specifies the lock signals that must be monitored on the LOCK1 output pin. If all internal lock signals configured by this mask go high, then LOCK1 goes high.
b7 0x09 fec b6 car b5 equ b4 tim b3 agc 2 b2 agc 1 b1 adc b0 pll
* unlck1: IRQ when LOCK1 signal goes from 1 to 0 * lck1: IRQ when LOCK1 signal goes from 0 to 1 * unlck2: IRQ when LOCK2 signal goes from 1 to 0 * lck2: IRQ when LOCK2 signal goes from 0 to 1 * sat: IRQ when signal input loss (AGC saturation) * frmlst: IRQ when frame was lost * time_win: Periodic generation of IRQ 00: IRQ not activated by time delay 01: IRQ activated every 2048 frames 10: IRQ activated every 16384 frames 11: IRQ activated every 108 bits SETAUTOCFG configures the mask on UNLOCK1. TUNI2CADD: 0x0C (read/write) I2C address of tuner when connected to I2C bus of device (pins TI2CSCL and TI2CSDA). For more details on the tuner I2C switch principle, see "I2C Read Mode" on page 9.
b7 0x0C b6 b5 b4 b3 b2 b1 b0 EN Tuner I2C address
* fec: Mask on forward error correction lock signal * car: Mask on carrier recovery loop lock signal * equ: Mask on equalizer lock signal * tim: Mask on symbol rate recovery lock signal * agc2: Mask on digital agc lock signal * agc1: Mask on analog agc lock signal * adc: Mask on analog agc level lock signal * pll: Mask on Phase Locked Loop (PLL) lock signal SETAUTOCFG configures MASKLOCK1 at value 0x80, corresponding to the FEC lock signal only. MASKLOCK2: 0x0A (read/write) This register specifies the lock signals that must be monitored on the LOCK2 output pin. If all internal lock signals configured by this mask go high, then LOCK2 goes high.
b7 0x0A fec b6 car b5 equ b4 tim b3 agc 2 b2 agc 1 b1 adc b0 pll
EN enables the switch when set to 1.
Note: EN should be set to 1 when tuner is configured. Then EN must be set back to 0.
CHIPID: 0x0E to 0x0F (read) Gives information about chip number and version. Value is 0x6510 (AT76C651, version A).
b7 0x0E 0x0F 0 0 b6 1 0 b5 1 0 b4 0 1 b3 0 0 b2 1 0 b1 0 0 b0 1 0
SETAUTOCFG configures MASKLOCK2 at value 0x70, corresponding to the lock signals of the carrier recovery, the equalizer and the timing recovery, which is the full demodulator. IRQMASK: 0x0B (read/write) Mask for IRQ output pin. This register specifies the mask on events that should activate the IRQ pin. IRQ goes to the value specified by irqpol (see OUTPUTCFG configuration) when any of the events specified by the mask described below occur and goes back to high impedance when any I2C register is written by the microcontroller.
b7 0x0A unlck 1 b6 lck 1 b5 unlck 2 b4 lck 2 b3 sat b2 frm lst b1 b0
Baseband Conversion and AGC1
AGC1NMIN: 0x13 (read/write) Specifies the minimum (or maximum) amplification value of AGC1 given by the PWM output pin, which is between 0 and 255 when BBCFG(4) = 0 or BBCFG(4) = 1. For more details about the BBCFG register, see the description below. This value can be used to saturate amplification in case of non-linearities of the amplifier at extreme values.
b7 0x13 b6 b5 b4 b3 b2 b1 b0
agc1nmin
Example: 0x00 (for maximum amplifying range)
time_win
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AGC1NMAX: 0x14 (read/write) Specifies the maximum (or minimum) amplification value of AGC1 given by the PWM output pin, which is between 0 and 255 when BBCFG(4) = 0 or BBCFG(4) = 1. For more details about the BBCFG register, see the description below. This value can be used to saturate amplification in case of non-linearities of the amplifier at extreme values.
b7 0x14 b6 b5 b4 b3 b2 b1 b0
* pwmcon: Specifies output format for AGC and CSTPWM pins. If set to 0, the AGC control is output in PWM format on AGC pin, and a completely configurable value (see CSTPWM register) is output in PWM format on CSTPWM pin. If set to 1, the AGC control is output in differential format on AGC and CSTPWM pins. In this case, differential integration must be performed in the analog domain. In case of a PWM output, the AGC pin should be connected to an RC filter with a cut-off frequency of maximum 1 kHz. Example: R = 1.5 k, C = 1 F
Note: The PWM output pin can be power supplied by 5V through the I2CVDD power supply. This assumes I2C bus functions at 5V.
agc1nmax
Example: 0xFF (for maximum amplifying range) BBCFG: 0x15 (read/write) General control of IF to BB conversion. This register controls several parameters of the AGC1 control loop, internal DC-offset compensation and AGC output format.
b7 0x15 res b6 res b5 dc con b4 sgn am b3 adc con b2 res b1 pwm con b0 res
CSTPWM: 0x17 (read/write) Specifies a configurable value between 0 and 255, which is given in PWM format on CSTPWM pin in case BBCFG(1) = 0. The CSTPWM pin should be connected to an RC filter with a cut-off frequency of maximum 1 kHz. Example: R = 1.5 k, C = 1 F This voltage output can be used to control any other device on the board, like other amplifier gain control, variable capacitor, etc.
Note: This pin can output 5V since it is power-supplied by the I2CVDD power supply (this assumes I2C bus functions at 5V).
* res: Reserved (must be configured with 0 when writing register) * dccon: DC-offset control. If set to 0, the internal DCoffset compensation is ON. If set to 1, the internal DCoffset control is OFF. The DC-offset should be ON when the input signal is in BB. * sgnam: Sign of the amplifier control command (see Figure 14) Figure 14. sgnam Configuration for Amplifier Gain Control
sgnam = 0
b7 0x17
b6
b5
b4 cstpwm
b3
b2
b1
b0
Example: cstpwm = 0x7F (2.5V in case 5V is connected to I2CVDD)
Amplifier Gain
BBTOPCNT: 0x19 (read) This monitoring register indicates the number of A/D saturations over 16384 successive samples. This register can take values between 0 and 255. 255 indicates that more than 255 A/D saturations have occurred during the last 16384 samples.
b7 0x19 b6 b5 b4 b3 b2 b1 b0
sgnam = 1 Control Voltage
* adccon: Specifies whether ADCLEVEL must be automatically adapted in the presence of adjacent channels or if it must keep its initial value defined by register AGC1INITADC. Automatic adaptation is configured by 0; no adaptation is configured by 1.
bbtopcnt
When the demodulator is working properly, this value should indicate 0x00.
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Timing Recovery
TIMLOOPCFG: 0x23 to 0x24 (read/write) These two registers configure the loop bandwidth of the timing recovery loop.
b7 0x23 0x24 b6 b5 b4 b3 b2 b1 b0 blmax_mexp bltrack_mexp blmin_mexp reserved
Carrier Recovery
CARALPHAACQ/CARBETAACQ: 0x31/0x32 (read/write) These two registers select the carrier loop bandwidth during acquisition phase. Through those 2 bytes one can control the bandwidth and the damping factor () of the loop filter.
b7 0x31 0x32 b6 b5 b4 b3 b2 b1 b0
caralphaacq carbetaacq
Example: 0x7F for register 0x23 and 0x9 for register 0x24 The three parameters blmax_mexp, blmin_mexp and bltrack_mexp are 4-bit unsigned numbers that must follow the conditions: * 7 blmax_mexp blmin_mexp 15 * 7 bltrack_mexp 15 They are related to the bandwidth blmax, blmin and bltrack by the formula: blx = 2
-Blx_mexp
Table 15 depicts some typical values for CARALPHAACQ and CARBETAACQ. Table 15.
Bl fsymbol 0.005 0.005 0.005 0.005 0.010 0.010 0.010 0.010 0.030 0.030 0.030 0.030
0.7 1.0 2.0 4.0 0.7 1.0 2.0 4.0 0.7 1.0 2.0 4.0
CARALPHAACQ 0xAE 0x98 0x9A 0x9A 0x9E 0x88 0x8A 0x8A 0x7A 0x7C 0x7E 0x7F
CARBETAACQ 0x9C 0x98 0xBC 0xDD 0x7C 0x78 0x9C 0xBD 0x4D 0x49 0x6D 0x8E
blmax is the maximal and initial bandwidth value used with a robust (Gardner type) comparator. blmin is the minimal bandwidth value that can be taken by the loop bandwidth with the same comparator. When blmax > blmin, the loop can automatically decrease when the lock indicator is positive or increase when this signal detects that the timing recovery system is out of lock. This variable bandwidth allows fast convergence, large timing frequency lock-in range in initial acquisitio1 n phase and low timing jitter when the system is locked. bltrack is the fixed value of the bandwidth used with decision base comparator. Typical values corresponding to the example above are: blmax = 2-7 blmax_mexp = 7 blmin = 2-15 blmin_mexp = 15 bltrack = 2-9 bltrack_mexp = 9 TIMLOOPMONIT: 0x29 (read) This monitoring register indicates the value of the automatically variable loop bandwidth.
b7 0x29 b6 b5 b4 b3 b2 b1 b0 Bl_mexp
-Bl_mexp
In automatic configuration, these parameters correspond to Bl fsymbol = 0.03 and = 1.0. CARALPHATRACK/CARBETATRACK: 0x33/0x34 (read/write) These two registers select the carrier loop bandwidth during tracking phase (after acquisition). The same table as given for (0x31/0x32) configures these parameters. The switch between tracking phase and acquisition phase takes place when agc2, equalizer and carrier are locked.
b7 0x33 0x34 b6 b5 b4 b3 b2 b1 b0 caralphatrack carbetatrack
reserved
Bandwidth Bl, which is given by formula: Bl = 2 Bl_mexp is an unsigned value, taking values from blmax_mexp to blmin_mexp (see TIMLOOPCFG). When timing is well recovered, Bl is equal to blmin.
In automatic configuration, these parameters correspond to Bl fsymbol = 0.03 and = 4.0.
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CARCONST: 0x39/0x3A/0x3B (read)
b7 0x39 0x3A 0x3B I (3:0) b6 b5 b4 b3 b2 b1 b0 I (11:4) Q (11:4) Q (3:0)
Table 16.
QAM QPSK QAM-16 QAM-32 QAM-64 QAM-128 QAM-256 QAM-512 QAM-1024 AGC2CFG 0x34 0x35 0x35 0x34 0x33 0x32 0x31 0x30
The constellation points after gain adjustment, timing recovery, equalization and carrier recovery can be collected without breaking down the demodulation and the channel decoding. The two components (I, Q), with 12-bit precision, are collected in three bytes: * Byte 1 (0x39): 8 MSB of I * Byte 2 (0x3A): 8 MSB of Q * Byte 3 (0x3B): The 4 MSB of byte 3 are equal to the 4 LSB of I and the 4 LSB of byte 3 are equal to the 4 LSB of Q. Byte 1 should be collected first. When the address of this byte is detected by the AT76C651, then a constellation point (I: 12 bits, Q: 12 bits) is memorized and only the 8 MSBs of I are sent as data on the I2C bus. Byte 2 and byte 3 can be collected later; their content does not change unless byte 1 is collected again.
AGC2INIT: 0x43 and 0x44 (read/write) These registers configure the initial agc2 gain.
b7 0x43 0x44 mantissa (2:0) b6 b5 b4 b3 b2 b1 b0 mantissa (10:3) exponent (4:0)
AGC2INIT is coded in a floating format with a mantissa coded with 11 unsigned bits and an exponent coded with 5 signed bits, defined as follows: exponent = floor ( log 2 ( agc2gain ) )
AGC2
AGC2CFG: 0x42 (read/write)
b7 0x42 res b6 b5 b4 loopbw1 b3 b2 b1 loopbw2 b0
mantissa = floor ( agc2gain x 2
- exponent
x 1024 )
Exponent must be in the range -6 to 13, and mantissa takes its value in the range 1024 to 2047.
Two operating modes exist for agc2: boost mode and normal mode. After a reset or a soft clear, the agc2 is in boost mode and unlocked. During this phase, equalizer and carrier are inhibited. The switch from boost mode to normal mode happens when agc2 locks. The agc2 loop bandwidth can be controlled through loopbw2 during boost mode and by loopbw1 during normal mode. In both cases the loop bandwidth is proportional to loopbw. Table 16 gives the value of AGC2CFG for the different QAM in automatic configuration.
Equalizer
EQUCFG: 0x51 (read/write) This register controls the equalizer operating mode.
b7 0x51 inh b6 fre b5 len b4 b3 b2 b1 step b0 structure
* inh: When set to 1, this parameter inhibits the equalizer; all equalizer taps are set to 0 except central tap, which is equal to 1 (in complex format). In standard configuration it is set to 0. * fre: When set to 1 it freezes the equalizer taps adaptation. The equalizer behaves as a complex FIR (finite impulse response). In standard configuration it is set to 0. * len: The equalizer has 32 taps when this parameter is set to 1 and only 16 taps when set to 0. The first mode can be selected only if the ratio between fref and fsymbol is higher or equal to 8(fref/fsymbol =8). In standard configuration it is set to 1.
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* structure: Two equalizer structures are implemented in the AT76C651: LE (linear equalizer) and DFE (decision feedback equalizer). When b5 = 1, only LE structure can be selected. In DFE mode two substructures, depending on the position of the central tap, can be configured. Table 17 shows the different possibilities. * step: This parameter controls the step used to adapt the equalizer taps. The higher the step, the higher the adaptation step. Table 17.
b4b3 00 10 01 11 Structure LE LE DFE with central tap position between 0 and 7 DFE with central tap position between 8 and 15
* adapt: The central tap adaptation mode can be selected between the configurations shown in Table 18: Table 18.
b6b5 00 01 10 11 Real Part adapted adapted fixed to 1 fixed to 1 Imag Part adapted fixed to 0 adapted fixed to 0
In standard configuration it is set to 11. EQUTAPRORD: 0x53 (read/write)
b7 0x53 b6 reserved b5 b4 b3 b2 b1 b0 equalizer tap position
EQUCENTRAL: 0x52 (read/write)
b7 0x52 res b6 b5 b4 b3 b2 b1 b0
adapt
central tap position
This parameter selects the position of the equalizer tap that we want to collect (see "EQUTAPREAL: 0x54/0x55 (read) and EQUTAPIMAG: 0x56/0x57 (read)"). The number of taps that can be read depends on the equalizer length (see "EQUCFG: 0x51 (read/write)"). EQUTAPREAL: 0x54/0x55 (read) and EQUTAPIMAG: 0x56/0x57 (read)
b7 0x54 MSB 0x55 LSB 0x56 MSB 0x57 LSB b6 b5 b4 b3 b2 b1 b0 equtapreal (15:8) equtapreal (7:0) equtapimag (15:8) equtapimag (7:0)
central tap position: EQUCENTRAL (4:0) gives the position of the equalizer central tap. This position should be set between 0 and 31 when EQUCFG(5) = 1 and between 0 and 15 when EQUCFG(5) = 0. In standard configuration this parameter is set to 7.
After selecting the equalizer tap to read (see "EQUTAPRORD: 0x53 (read/write)"), the real part and the imaginary part of the tap are collected in four bytes. The first byte to read must be 0x54. When the AT76C651 detects this address, it memorizes the equalizer tap value (4 bytes) and sends the 8 MSBs of the real part as read data. The three other bytes can be collected later. The value of the tap is equal to:
( ( signed ) ( EQUTAPREAL ) ) + ( j signed ( EQUTAPIMAG ) ) ( real + j imag ) = -------------------------------------------------------------------------------------------------------------------------------------------------16384
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FEC
FECIQINV: 0x60 (read/write) Configuration of I and Q inversion. This register indicates if the I and Q channel must be swapped before de-mapping. An automatic mode is also provided.
b7 0x60 b6 b5 reserved b4 b3 b2 iqinv b1 b0 iqinvcmd
FECDILVILEN: 0x63 (read/write) Number of branches in the de-interleaver.
b7 0x63 b6 reserved b5 b4 b3 b2 dilvilen b1 b0
dilvilen is a 5-bit value that gives the number of branches in the de-interleaver. See fecdilvmlen below for constraints. Example: for standard DVB-C MPEG2-TS, dilvilen should be set to 12 (default value). FECDILVMLEN: 0x64 (read/write) Memory step size of the de-interleaver.
b7 0x64 b6 reserved b5 b4 b3 b2 dilvmlen b1 b0
* iqinv is a read-only single bit that indicates if I and Q channel are swapped (in manual mode it is equal to b0). * iqinvcmd is composed of two bits (read/write): the msb (b1) controls the use of the automatic mode (= 0) or the manual mode (= 1); the lsb (b0) is used in manual mode to swap I and Q channel.
Note: The automatic mode uses the frame structure to choose the right configuration. If the frame is not recovered, iqinv can change at any time.
FECFLEN: 0x61 (read/write) Frame length configuration. The size of frame can be configured.
b7 0x61 b6 b5 b4 flen b3 b2 b1 b0
dilvmlen is a 5-bit value that gives the memory step size of the de-interleaver (described in the DVB standard). * The first branch has (dilvilen-1) x dilvmlen memory byte. * The second branch has (dilvilen-2) x dilvmlen memory bytes. * The third branch has (dilvilen-3) x dilvmlen memory bytes. * ... * The dilvilenth branch has 0 memory bytes. The first byte of a frame is always routed to the first branch in the de-interleaver. To allow a correct synchronization, the following formula must be respected by the user: fecdilvilen x fecdilvmlen = flen The internal memory is limited to 2K bytes of RAM: flen ( fecdilvilen - 1 ) ---------------------------------------------------- + fecdilvilen < 2048 2
flen is an 8-bit value that gives the length of the frame. This value should be higher than 50 to guarantee a correct functioning of the FEC decoder. Example: for DVB MPEG2-TS, the frame length is 204. This is the default value.
Note: The Reed-Solomon parity length is always 16 bytes and is counted in the frame length.
FECFSW: 0x62 (read/write) Frame synchronization word configuration.
b7 0x62 b6 b5 b4 fsw b3 b2 b1 b0
Example: for DVB MPEG2-TS, dilvmlen must be set to 17 (default value). However, it can sometimes be advantageous to use fecdivilen = 17 with fecdilvmlen = 12 (keeping fecflen = 204) to get a better impulsive errors spreading.
fsw is an 8-bit value that gives the normal value of the first byte in a frame. In DVB, the first byte of the frame is periodically bit-to-bit inverted to synchronize the descrambler. Example: For DVB MPEG2-TS, the frame synchronization word is 0x47, which is also the default value.
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FECINH: 0x65 (read/write) Inhibition of selected parts of the forward error correction blocks.
b7 0x65 b6 b5 b4 scrm b3 rs b2 dilv b1 frm b0 diff res beind force
enable. When this function is enabled and if the 13-bit PID of an incoming frame matches PID1, the FLAGPID0 pin takes the value 1 and the FLAGPID1 pin takes the value 0. This filter has a higher priority than PID2 and PID3. The default value is 0x0000 so the function is disabled. PID2: 0x72 to 0x73 (read/write) Second MPEG PID to filter. This function can be disabled.
b7 0x72 0x73 b6 b5 enpid2 b4 b3 b2 pid2 (12:8) pid2 (7:0) b1 b0 reserved
FECINH is a 7-bit value. Each bit set to 1 indicates that the selected function is inhibited. The hardware block is then in a transparent mode. Table 19.
FECINH Bits b0: diff b1: frm b2: dilv b3: rs b4: scrm b5: force b6: beind Functions Inhibited differential decoder frame synchronization de-interleaver Reed-Solomon decoder scrambler 1st byte forced to FECFSW Bit Error Indicator (MSB of 2nd byte) Comments useful for non-coherent demodulation prevent bit skipping if frames not needed cannot be synchronized without frames error detection without correction need inverted FECFSW for synchronization cannot be used without frame recovery enable external bit error rate measure
PID2 is a 14-bit value that gives the second MPEG PID to flag. This function is provided to enable the use of simple software MPEG de-multiplexer. Bit 5 of the register 0x72 is an enable. When this function is enabled, if the 13-bit PID of an incoming frame matches PID2 and if PID1 flag is not s et, the FLAG P ID1 pin ta ke s the va lue 1 an d th e FLAGPID0 pin takes the value 0. This filter has a higher priority than PID3, but lower than PID1. The default value is 0x0000, so the function is disabled. PID3: 0x74 to 0x76 (read/write) and PIDMSK3: 0x77to 0x79 (read/write) Third PID to filter. This filter has a 24-bit length with a mask of the same length.
b7 0x74 0x75 0x76 0x77 0x78 0x79 b6 b5 b4 b3 b2 b1 b0
pid3 (23:16) pid3 (15:8) pid3 (7:0) pidmsk3 (23:16) pidmsk3 (15:8) pidmsk3 (7:0)
Example: For DVB MPEG2-TS, FECINH should be set to 0x00 (default value) but to execute an external bit error rate measure, b3, b5 and b6 should probably be set to 1 (FECINH = 0x68). For non-DVB applications, with FECINH = 0x7E, it is possible to get data after QAM de-mapping and differential decoder in serial mode or in parallel mode (bytes are not aligned).
PID Filtering
PID1: 0x70 to 0x71 (read/write) First MPEG PID to filter. This function can be disabled.
b7 0x70 0x71 b6 b5 enpid1 b4 b3 b2 pid1 (12:8) pid1 (7:0) b1 b0 reserved
PID3 is a 24-bit value that gives the third PID (the 2nd, 3rd and 4th bytes of frame) to flag. This function is provided to enable the use of a simple software MPEG de-multiplexer. A 24-bit mask is also provided by registers 0x77 to 0x79. The MPEG header bits are only checked with PID3 if the corresponding bits in PIDMSK3 are set to 1. If PIDMSK3 is set to 0x000000, the function is disabled. If PID1 or PID2 get a match for a particular frame, PID3 filter is not performed for this frame. When PID3 gets a match, both pins FLAGPID0 and FLAGPID1 are set to 1. This filter has a lower priority than PID1 and PID2. The default value is 0x000000 for PID3 and PIDMSK3. This function is disabled.
PID1 is a 14-bit value that gives the first MPEG PID to flag. This function is provided to enable the use of a simple software MPEG de-multiplexer. Bit 5 of the register 0x70 is an
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General Monitoring
b7 b6 b5 b4 b3 ber2 b2 b1 b0
LOCK: 0x80 (read) This monitoring register indicates the lock status of AGC1, AGC2, timing recovery, carrier recovery, equalizer, FEC and the PLL.
b7 0x80 fec b6 car b5 equ b4 tim b3 agc 2 b2 agc 1 b1 adc b0 pll
0x84
NPERR: 0x85 (read) This monitoring register indicates the number of uncorrectable frames in the last 108 bits. The value is saturated at 255 if more than 255 uncorrectable frames have occurred.
b7 0x85 b6 b5 b4 b3 b2 b1 b0
* fec: Lock signal for FEC * car: Lock signal for carrier recovery * equ: Lock signal for equalizer * tim: Lock signal for timing recovery * agc2: Lock signal for digital AGC (AGC2) * agc1: Lock signal for analog AGC (AGC1) * adc: Lock signal for AGC1 power reference value adaptation * pll: Lock signal for PLL BER1: 0x81 to 0x83 (read) This monitoring register indicates the bit error rate estimate over the last 108 bits. This register indicates the number of corrected bit errors in the last 108 bits, but does not take into account the frames that are not correctable, i.e., the frames in which more than eight errors have occurred (this value can be monitored in register NPERR).
b7 0x81 0x82 0x83 b6 b5 b4 b3 b2 b1 b0 reserved ber1(15:8) ber1(7:0) ber1(20:16)
nperr
TIMFREQOFF: 0x86 to 0x88 (read) This monitoring register indicates the value of the recovered symbol rate offset with respect to the configured symbol rate (see "Symbol Rate" on page 13).
b7 0x86 0x87 0x88 b6 b5 b4 b3 b2 b1 b0
timfreqoff (23:16) timfreqoff (15:8) timfreqoff (7:0)
Timfreqoff is a positive integer value directly read in the loop filter memory. This value is scaled by a gain factor Kl inside the chip and is added to the configured symbol rate. The result is used to control the timing of the numerically controlled oscillator, and is the recovered symbol rate. Therefore, it is possible to compute the real recovered symbol rate offset T (in Hz) with the following formula: timfreqoff x K T = -------------------------------------l 29 2 The scaling factor Kl is internally defined as the approximation of the configured symbol rate given in the following formula: K l = floor ( mantissa x 2
- 16
BER2: 0x84 (read) This monitoring register indicates another bit error rate estimate based on a counter of false frame synchronization words. This register is meaningful when the bit error rate is greater than 10-3. The bit error rate is given by: ber2 -----------4096
)2
-4
x2
exponent-10
where exponent and mantissa are the configured symbol rate exponent plus 10 and symbol rate mantissa (see "Symbol Rate" on page 13).
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DDSFREQOFFSET: 0x89 to 0x8A (read) This monitoring register indicates the frequency offset recovered by the DDS (at IF to BB down conversion). This value, added to the frequency entered in register BBFREQ, gives the corrected IF frequency of the input signal. This value is a fraction of the crystal frequency fXTAL.
b7 0x89 0x8A b6 b5 b4 b3 b2 b1 b0 ddsfreqoffset (15:8) ddsfreqoffset (7:0)
In the following formula:
2 ( dB )
= A ( dB ) + ( 10 x log 10 ( phasenoise ) )
denotes the residual phase noise and the mean of squared.
The parameter A depends on the QAM format and is given in Table 20: Table 20.
QAM QPSK QAM-16 QAM-32 QAM-64 QAM-128 QAM-256 QAM-512 QAM-1024 A (dB) -45.15 -54.69 -54.69 -62.05 -62.05 -68.67 -68.67 -74.98
The offset frequency is given by: f DDSFREQOFFSET ddsfreqoffset x f XTAL = ------------------------------------------------------20 2
CARFREQOFFSET: 0x8B to 0x8C (read) This monitoring register indicates the frequency offset recovered by the carrier. The collected value is normalized to symbol rate.
b7 0x8B 0x8C b6 b5 b4 b3 b2 b1 b0 carfreqoffset (15:8) carfreqoffset (7:0)
The phase noise portion due to the integration of the additive noise by the loop filter is given by:
Address 0x8B (MSBs) must be read from the device first in order to ensure the correctness of the content of 0x8C (LSBs). The offset frequency is given by: signed ( carfreqoffset ) x f symbol f CARFREQOFFSET = -------------------------------------------------------------------------------17 2 The total frequency offset recovered is given by:
2
n
= Bl x 2 x n
f = f DDSFREQOFFSET + f CARFREQOFFSET
PHASENOISE: 0x8D to 0x8E (read) The residual phase noise (after carrier recovery) is estimated. The collected information contains the phase noise due to oscillators and also the phase noise due to the additive noise integrated by the carrier loop filter. Below is an explanation of how to compute the total residual phase noise and how to extract the phase noise due to additive noise.
b7 0x8D 0x8E b6 b5 b4 b3 b2 b1 b0 phasenoise (15:8) phasenoise (7:0)
The parameter depends of the QAM format and is given by the table below. = denotes the mean square of the additive noise description (see "ADDITIVENOISE: 0x8F to 0x90 (read)" on page 33), and Bl the selected carrier loop bandwidth for tracking phase. Table 21.
QAM QPSK QAM-16 to QAM-1024 = 2.53e-2 2.83e-2
The residual phase noise due to oscillator impairments is then equal to:
2 = 2 - 2 osc n
Using osc, the configured loop bandwidth, the symbol rate and an assumption about the tuner phase noise shaping, an estimate of the phase noise at a given frequency offset can be obtained.
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AT76C651
The example below shows how to make this computation when the tuner phase noise level decreases by 20 dB each time frequency offset is multiplied by 10. The result is given by the following formula: The following formula shows how to compute the S/N (dB) or the Eb/N (dB) for each QAM format. additivenoise 2 ( dB ) = 10 x log 10 ae ----------------------------------- o e 16 n 2 n denotes the additive noise and n the mean of n square. S/N (dB) = 10 x log10(A) - n (dB) Eb/N (dB) = 10 x log10(B) - n (dB) Table 23 gives the values of A and B for each QAM. Table 23.
QAM 0.7 1.0 2.0 4.0 0.7 1.0 2.0 4.0 0.7 1.0 2.0 4.0 1460 1250 1030 980 720 600 510 480 225 180 160 150 QPSK QAM-16 QAM-32 QAM-64 QAM-128 QAM-256 QAM-512 QAM-1024 A 2 10 20 42 82 170 330 682 B 1 10/4 20/5 42/6 82/7 170/8 330/9 682/10
phasenoise spd
2 x f symbol ( Hz ) osc = -------------------------------------------------------- ( dBc ) ( Hz ) 2 ( f )
phasenoisespd is the phase noise spectral density at frequency offset (f) given in Hz. is a constant that depends on the carrier loop filter. See Table 22. Table 22.
Bl 0.005 0.005 0.005 0.005 0.010 0.010 0.010 0.010 0.030 0.030 0.030 0.030 Note:
AGC1LEVEL: 0x91 (read) This monitoring register indicates the present level of AGC1, which is output in PWM format to AGC output pin. The value is between AGC1NMIN and AGC1NMAX.
b7 0x91 b6 b5 b4 b3 b2 b1 b0 agc1level
The phase noise information is not relevant if the demodulator is not locked.
ADDITIVENOISE: 0x8F to 0x90 (read) An estimate of the additive noise level is implemented in the AT76C651. It can be used to compute the S/N (signalto-noise) ratio. Byte 0x8F should be collected first in order to ensure the correctness of 0x90. When the demodulator is not locked, this information is not relevant.
b7 0x8F 0x90 b6 b5 b4 b3 b2 b1 b0
AGC1LEVEL indicates the control voltage value (V) applied at the input of the external amplifier, through the RC filter, connected to the AGC pin. It is given by: agc1level V = ------------------------- x I2CVDD 255 where I2CVDD is the power supply connected to pin I2CVDD (5V or 3.3V).
additivnoise (15:8) additivnoise 0 (7:0)
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AGC2LEVEL: 0x92 to 0x93 (read) These registers allow the user to monitor the current value of agc2 gain.
b7 0x92 0x93 b6 b5 b4 b3 b2 b1 b0 mantissa (10:3) mantissa (2:0) exponent (4:0)
exponent = floor ( log 2 ( agc2gain ) ) mantissa = floor ( agc2gain x 2
- exponent
x 1024 )
Exponent takes its value in the range -6 to 13, and mantissa takes its value in the range 1024 to 2047.
AGC2LEVEL is coded in a floating format with a mantissa coded with 11 unsigned bits and an exponent coded with 5 signed bits, and is defined as follows:
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AT76C651
Timing Waveforms
Output Interface
Figure 15. Parallel MPEG2-TS Output
Datavalid
2/fREF 4/fREF 2/fREF
Dataout[7..0] Frmstart Frmvalid Corbyte Corfail
16 bytes
FSW
188 bytes
Figure 16. Serial Output Mode
Datavalid Dataout (7) Dataout (6) Dataout (5) ... Dataout (1) Dataout (0) b0 b7 b6 b5 b4 b3 b2 b1 Frmstart
b0
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4
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Input Interface
The input pin SAMPLEPHASE must be connected to GND or VDD, as indicated in the following table. See Figure 17 for the definition of tPAD and tADCLK. Table 24.
SAMPLEPHASE 0 1 tPAD Typ tPAD tADCLK/4 or tPAD 3tADCLK/4 tADCLK/4 tPAD 3tADCLK/4
Figure 17. External A/D Converter Input
tADCLK
ADCLK A/D output
tPAD
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