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Features
* Monolithic Field Programmable System Level Integrated Circuit (FPSLICTM) *
- AT40K SRAM-based FPGA with Embedded High-performance RISC AVR(R) Core, Extensive Data and Instruction SRAM and JTAG ICE 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAMTM - 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM - High-performance DSP Optimized FPGA Core Cell - Dynamically Reconfigurable In-System - FPGA Configuration Access Available On-chip from AVR Microcontroller Core to Support Cache Logic(R) Designs - Very Low Static and Dynamic Power Consumption - Ideal for Portable and Handheld Applications Patented AVR Enhanced RISC Architecture - 120+ Powerful Instructions - Most Single Clock Cycle Execution - High-performance Hardware Multiplier for DSP-based Systems - Approaching 1 MIPS per MHz Performance - C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers - Low-power Idle, Power-save and Power-down Modes - 100 A Standby and Typical 2-3 mA per MHz Active Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM - Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM - Up to 16 Kbytes x 8 Internal 15 ns Data SRAM JTAG (IEEE std. 1149.1 Compliant) Interface - Extensive On-chip Debug Support - Limited Boundary-scan Capabilities According to the JTAG Standard (AVR Ports) AVR Fixed Peripherals - Industry-standard 2-wire Serial Interface - Two Programmable Serial UARTs - Two 8-bit Timer/Counters with Separate Prescaler and PWM - One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-bit PWM Support for FPGA Custom Peripherals - AVR Peripheral Control - 16 Decoded AVR Address Lines Directly Accessible to FPGA - FPGA Macro Library of Custom Peripherals 16 FPGA Supplied Internal Interrupts to AVR Up to Four External Interrupts to AVR 8 Global FPGA Clocks - Two FPGA Clocks Driven from AVR Logic - FPGA Global Clock Access Available from FPGA Core Multiple Oscillator Circuits - Programmable Watchdog Timer with On-chip Oscillator - Oscillator to AVR Internal Clock Circuit - Software-selectable Clock Frequency - Oscillator to Timer/Counter for Real-time Clock VCC: 3.0V - 3.6V 3.3V 33 MHz PCI-compliant FPGA I/O - 20 mA Sink/Source High-performance I/O Structures - All FPGA I/O Individually Programmable High-performance, Low-power 0.35 CMOS Five-layer Metal Process State-of-the-art Integrated PC-based Software Suite including Co-verification 5V I/O Tolerant
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5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE AT94K Series Field Programmable System Level Integrated Circuit Summary
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Rev. 1138FS-FPSLI-06/02
Note: This is a summary document. A complete document is available on our web site at www.atmel.com.
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Description
The AT94K Series FPSLIC family shown in Table 1 is a combination of the popular Atmel AT40K Series SRAM FPGAs and the high-performance Atmel AVR 8-bit RISC microcontroller with standard peripherals. Extensive data and instruction SRAM as well as device control and management logic are included on this monolithic device, fabricated on Atmel's 0.35 five-layer metal CMOS process. The AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data) and 5,000 to 40,000 usable gates. Table 1. The AT94K Series Characteristics
Device FPGA Gates FPGA Core Cells FPGA SRAM Bits FPGA Registers (Total) Maximum FPGA User I/O AVR Programmable I/O Lines Program SRAM Data SRAM Hardware Multiplier (8-bit) 2-wire Serial Interface UARTs Watchdog Timer Timer/Counters Real-time Clock JTAG ICE @ 25 MHz @ 40 MHz AT94K05AL/AX 5K 256 2048 436 96 8 4 Kbytes - 16 Kbytes 4 Kbytes - 16 Kbytes Yes Yes 2 Yes 3 Yes Yes
(1)
AT94K10AL/AX 10K 576 4096 846 144 16 20 Kbytes - 32 Kbytes 4 Kbytes- 16 Kbytes Yes Yes 2 Yes 3 Yes Yes
(1)
AT94K40AL/AX 40K 2304 18432 2862 288 16 20 Kbytes - 32 Kbytes 4 Kbytes - 16 Kbytes Yes Yes 2 Yes 3 Yes Yes(1) 19 MIPS 30 MIPS 3.0 - 3.6V (2) 1.6 - 2.0V (2)
19 MIPS 30 MIPS 3.0 - 3.6V(2) 1.6 - 2.0V(2)
19 MIPS 30 MIPS 3.0 - 3.6V(2) 1.6 - 2.0V(2)
Typical AVR throughput
Operating Voltage(2)
AL AX
Notes:
1. FPSLIC parts with JTAG ICE support can be identified by the letter "J" after the device date code, e.g., 4201 (no ICE support) and 4201J (with ICE support), see Figure 1. 2. FPSLIC devices should be laid out during PCB design to support a split power supply. Please refer to the "Designing in Split Power Supply Support for AT94KAL/AX and AT94SAL/AX Devices" application note, available on the Atmel web site at http://www.atmel.com/atmel/acrobat/doc2308.pdf.
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AT94K Series FPSLIC (Summary)
1138FS-FPSLI-06/02
AT94K Series FPSLIC (Summary)
Figure 1. FPSLIC Device Date Code with JTAG ICE Support
(R)
AT94K40AL-25DQC
0H1230 4201J
Date Code "J" indicates JTAG ICE support
The AT94K series architecture is shown in Figure 2. Figure 2. AT94K Series Architecture
PROGRAMMABLE I/O
5 - 40K Gates FPGA
Up to 16 Addr Decoder
Up to 16K x 16 Program SRAM Memory
Up to 16 Interrupt Lines
4 Interrupt Lines 2-wire Serial Unit
I/O
I/O with Multiply
Two 8-bit Timer/Counters
JTAG ICE
Up to 16K x 8 Data SRAM
16 Prog. I/O Lines
I/O
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1138FS-FPSLI-06/02
The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by executing powerful instructions in a single-clock cycle, and allows system designers to optimize power consumption versus processing speed. The AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 general-purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code-efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers at the same clock frequency. The AVR executes out of on-chip SRAM. Both the FPGA configuration SRAM and the AVR instruction code SRAM can be automatically loaded at system power-up using Atmel's in-system programmable (ISP) AT17 Series EEPROM Configuration Memories. State-of-the-art FPSLIC design tools, System DesignerTM, were developed in conjunction with the FPSLIC architecture to help reduce overall time-to-market by integrating microcontroller development and debug, FPGA development and Place and Route, and complete system co-verification in one easy-to-use software tool.
FPGA Core
The AT40K core can be used for high-performance designs, by implementing a variety of compute-intensive arithmetic functions. These include adaptive finite impulse response (FIR) filters, fast Fourier transforms (FFT), convolvers, interpolators, and discre te -co sine tran sfo rms (DC T) that are re quired for vide o compression an d decompression, encryption, convolution and other multimedia applications. The AT40K core offers a patented distributed 10 ns SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual-port or single-port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel's macro generator tool. The AT40K cores patented 8-sided core cell with direct horizontal, vertical and diagonal cell-to-cell connections implements ultra-fast array multipliers without using any busing resources. The AT40K core's Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed. The AT40K FPGA core is capable of implementing Cache Logic (dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As new logic functions are required, they can be loaded into the logic cache without losing the data already there or disrupting the operation of the rest of the chip; replacing or complementing the active logic. The AT40K FPGA core can act as a reconfigurable resource within the FPSLIC environment.
Fast, Flexible and Efficient SRAM
Fast, Efficient Array and Vector Multipliers
Cache Logic Design
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AT94K Series FPSLIC (Summary)
1138FS-FPSLI-06/02
AT94K Series FPSLIC (Summary)
Automatic Component Generators
The AT40K is capable of implementing user-defined, automatically generated, macros; speed and functionality are unaffected by the macro orientation or density of the target device. This enables the fastest, most predictable and efficient FPGA design approach and minimizes design risk by reusing already proven functions. The Automatic Component Generators work seamlessly with industry-standard schematic and synthesis tools to create fast, efficient designs. The patented AT40K architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. Independently controlled clocks and resets govern every column of four cells. The FPSLIC device is surrounded on three sides by programmable I/Os. Core usable gate counts range from 5,000 to 40,000 gates and 436 to 2,864 registers. Pin locations are consistent throughout the FPSLIC family for easy design migration in the same package footprint. The Atmel AT40K FPGA core architecture was developed to provide the highest levels of performance, functional density and design flexibility. The cells in the FPGA core array are small, efficient and can implement any pair of Boolean functions of (the same) three inputs or any single Boolean function of four inputs. The cell's small size leads to arrays with large numbers of cells. A simple, high-speed busing network provides fast, efficient communication over medium and long distances.
For a complete version of this datasheet, refer to the FPSLIC section of the Atmel web site, www.atmel.com.
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1138FS-FPSLI-06/02
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1138FS-FPSLI-06/02 xM

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