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Features
* Advanced, High-speed Programmable Logic Device - Superset of 22V10
- Improved Performance - 7.5 ns tPD, 95 MHz External Operation - Enhanced Logic Flexibility - Backward Compatible with ATV750(L) Software and Hardware * New Flip-flop Features - D- or T-type - Product Term or Direct Input Pin Clocking * High-speed Erasable Programmable Logic Devices - 7.5 ns Maximum Pin-to-pin Delay Device ATV750B ATV750BL ICC, Standby 125 mA 15 mA
* Highest Density Programmable Logic Available in a 24-pin Package * Increased Logic Flexibility
- 42 Array Inputs, 20 Sum Terms and 20 Flip-flops
High-speed UV Erasable Programmable Logic Device ATV750B ATV750BL
Commercial and industrial versions are obsolete. Please use ATF750C. Military versions continue to be available, but please do not use for new designs. For new military applications, recommend multiple ATF22V10s.
* Enhanced Output Logic Flexibility
- All 20 Flip-flops Feed Back Internally - 10 Flip-flops are Also Available as Outputs * Full Military, Commercial and Industrial Temperature Ranges
Logic Diagram
Description
The ATV750B(L) is twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform, predictable delays guarantee fast in-system performance.
DIP/SOIC
CLK/IN IN IN IN IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN
Pin Name CLK IN I/O * VCC
Function Clock Logic Inputs Bi-directional Buffers No Internal Connection +5V Supply
4 3 2 1 28 27 26
IN IN CLK/IN * VCC I/O I/O IN IN GND * IN I/O I/O 12 13 14 15 16 17 18 IN IN IN * IN IN IN 5 6 7 8 9 10 11 25 24 23 22 21 20 19 I/O I/O I/O * I/O I/O I/O
Pin Configurations
PLCC/LCC
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Each of the ATV750B(L) 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either Dor T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops. There are 171 total product terms available. A variable format is used to assign between four to eight product terms per sum term. There are two sum terms per output, providing added flexibility. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare. Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flipflop may also be individually configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. The ATV750BL is a low-power device with speeds as fast as 15 ns. The ATV750BL provides the optimum low-power PLD solution, with full CMOS output levels. This device significantly reduces total system power, thereby allowing battery-powered operation.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) Integrated UV Erase Dose..............................7258 W*sec/cm2 *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note:
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns.Maximum output pin voltage is VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns.
Logic Options
Combinatorial Output
Combined Terms Separate Terms
Registered Output
Combined Terms Separate Terms
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Clock Mux
CKMUX CKi CLOCK PRODUCT TERM CLK PIN TO LOGIC CELL SELECT
Output Options
DC and AC Operating Conditions(1)
Commercial -7, -10, -15 Operating Temperature 0C - 70C (Ambient) Commercial -25 0C - 70C (Ambient) Industrial -40C - 85C (Ambient) 5V 10% Military -55C - 125C (Case) 5V 10%
VCC Power Supply 5V 5% 5V 10% Note: 1. See ordering information for valid speed and temperature combination.
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DC Characteristics
Symbol ILI ILO Parameter Input Load Current Output Leakage Current Condition VIN = -0.1V to VCC + 1V VOUT = -0.1V to VCC + 0.1V Com. B-7, -10 Ind., Mil. Com. B-15, -25 Power Supply Current, Standby Output Short Circuit Current Input Low Voltage Input High Voltage IOL = 16 mA Output Low Voltage Output High Voltage VIN = VIH or VIL, VCC = MIN VIN = VIH or VIL, VCC = MIN IOL = 12 mA IOL = 24 mA IOH = -100 A IOH = -4.0 mA Com., Ind. Mil. Com. VCC - 0.3 2.4 VCC = MAX, VIN = MAX, Outputs Open VOUT = 0.5V 4.5 VCC 5.5V -0.6 2.0 0.8 VCC + 0.75 0.5 0.5 0.8 V V V V V V V Ind., Mil. Com. BL-15 Ind., Mil. 125 125 125 125 15 15 180 190 180 190 30 30 -120 mA mA mA mA mA mA mA Min Typ Max 10 10 Units A A
ICC IOS(1) VIL VIH
VOL
VOH Note:
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Input Test Waveforms and Measurement Levels
tR, tF < 3 ns (10% to 90%)
Output Test Load
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AC Waveforms, Product Term Clock(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Product Term Clock(1)
-7 Symbol tPD tEA tER tCO tCF tS tSF tH tP tW fMAX Parameter Input or Feedback to Non-Registered Output Input to Output Enable Input to Output Disable Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time Hold Time Clock Period Clock Width External Feedback 1/(tS+tCO) Internal Feedback 1/(tSF+tCF) No Feedback 1/(tP) tAW tAR tAP tSP Note: Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Reset Setup Time, Synchronous Preset 4 5 3 8 7 3 1 3 3 1 7 3.5 95 125 142 10 10 12 8 Min Max 7.5 7.5 7.5 7.5 5 4 4 4 4 2 11 5.5 71 86 90 15 15 15 15 Min -10 Max 10 10 10 10 7.5 5 5 8/12 7 5/7 14 7 50/41 62 71 20 20 25 B/BL-15 Min Max 15 15 15 12 9 6 5 14 7 5/7 17 8.5 29 58 58 B/BL-25 Min Max 25 25 25 20 10 Units ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns
1. See ordering information for valid part numbers.
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AC Waveforms, Input Pin Clock(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Input Pin Clock
-7 Symbol tPD tEA tER tCOS tCFS tSS tSFS tHS tPS tWS fMAXS Parameter Input or Feedback to Non-Registered Output Input to Output Enable Input to Output Disable Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time Hold Time Clock Period Clock Width External Feedback 1/(tSS+tCOS) Internal Feedback 1/(tSFS+tCFS) No Feedback 1/(tPS) tAW tARS tAP tSPS Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Reset Setup Time, Synchronous Preset 5 5 5 8 5/9 0 0 4 4 0 7 3.5 95 133 142 10 10 10 11 Min Max 7.5 7.5 7.5 6.5 3.5 0 0 6.5 5 0 10 5 74 100 100 15 15 15 15 Min -10 Max 10 10 10 7 5 0 0 8/12.5 7 0 12 6 55/44 80 83 20 25 25 Min B/BL -15 Max 15 15 15 10 5.5 0 0 9/15 9 0 16 8 48/37 62 62 Min B/BL -25 Max 25 25 25 12 7 Units ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns
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Functional Logic Diagram ATV750B, Upper Half
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Functional Logic Diagram ATV750B, Lower Half
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Preload of Registered Outputs
The ATV750B(L) registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A VIH level on the I/O pin will force the register high; a VIL will force it low, independent of the output polarity. The PRELOAD state is entered by placing a 10.25V to 10.75V signal on pin 8 on DIPs, and lead 10 on SMDs. When the clock term is pulsed high, the data on the I/O pins is placed into the register chosen by the Select Pin.
Level Forced on Registered Output Pin during PRELOAD Cycle VIH VIL VIH VIL
Select Pin State Low Low High High
Register #0 State after Cycle High Low X X
Register #1 State after Cycle X X High Low
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Power-up Reset
The registers in the ATV750B(L) is designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock terms or pin high, and 3. The clock pin, or signals from which clock terms are derived, must remain stable during tPR.
Parameter tPR VRST
Description Power-up Reset Time Power-up Reset Voltage
Typ 600 3.8
Max 1000 4.5
Units ns V
Pin Capacitance
f = 1 MHz, T = 25C(1)
Typ CIN COUT 5 6 Max 8 8 Units pF pF Conditions VIN = 0V VOUT = 0V
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Using the ATV750B(L) Many Advanced Features
The ATV750B(L) advanced flexibility packs more usable gates into 24-pins than any other logic device. The ATV750B(L) starts with the popular 22V10 architecture, and add several enhanced features: * Selectable D- and T-type Registers - Each ATV750B flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage. Selectable Asynchronous Clocks - Each of the ATV750B(L) flip-flops may be clocked by its own clock product term or directly from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. A Full Bank of Ten More Registers - The ATV750B provides two flip-flops per output logic cell for a total of 20. Each register has its own sum term, its own reset term and its own clock term. Independent I/O Pin and Feedback Paths - Each I/O pin on the ATV750B has a dedicated input path. Each of the 20 registers has its own feedback terms into the array as well. This feature, combined with individual product terms for each I/O's output enable, facilitates true bi-directional I/O design.
*
*
*
Programming Software Support
As with all other Atmel PLDs, several third-party development software products support the ATV750B(L). Several third-party programmers support the ATV750B as well. Additionally, the ATV750B may be programmed to perform the ATV750(L)'s functional subset (no T-type flipflops or pin clocking) using the ATV750(L) JEDEC file. In this case, the ATV750B becomes a direct replacement or speed upgrade for the ATV750(L). The ATV750(L) programming algorithm is different from the ATV750B algorithm. Choose the appropriate device in your programmer menu to ensure proper programming. Please refer to the Programmable Logic Development Tools section for a complete PLD software and programmer listing. One synchronous preset line is provided for all 20 registers in the ATV750B. The appropriate input signals to cause the internal clocks to go to a high state must be received during a synchronous preset. Appropriate setup and hold times must be met, as shown in the switching waveform diagram. An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and slave halves of the flip-flops are reset when the input signals received force the internal resets high. A single fuse is provided to prevent unauthorized copying of the ATV750B fuse patterns. Once the security fuse is programmed, all fuses will appear programmed during verify. The security fuse should be programmed last, as its effect is immediate.
Synchronous Preset and Asynchronous Reset
Security Fuse Usage
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Erasure Characteristics
The entire memory array of an ATV750B is erased after exposure to ultraviolet light at a wavelength of 2537 A. Complete erasure is assured after a minimum of 20 minutes exposure using 12,000 W/cm2 intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W*sec/cm2. To prevent unintentional erasure, an opaque label is recommended to cover the clear window on any UV-erasable PLD which will be subjected to continuous fluorescent indoor lighting or sunlight. The ATV750B utilizes an advanced 0.65-micron CMOS EPROM technology. This technology's state-of-art features are the optimum combination for PLDs: * * CMOS technology provides high-speed, low-power, and high noise immunity. EPROM technology is the most cos-effective method for producing PLDs - surpassing bipolar fusible link technology in low cost, while providing the necessary reprogrammability. EPROM reprogrammability, which is 100% tested before shipment, provides inherently better programmability and reliability than one-time fusible PLDs.
Atmel CMOS PLDs
*
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Ordering Information
tPD (ns) 7.5 10 tCOS (ns) 6.5 7 Ext. fMAXS (MHz) 95 74 Ordering Code ATV750B-7JC ATV750B-7PC(1) ATV750B-10JC(1) ATV750B-10PC(1) ATV750B-10SC(1) ATV750B-10JI(1) ATV750B-10PI(1) ATV750B-10SI(1) ATV750B-10DM/883(2) ATV750B-10LM/883(2) 15 10 58 ATV750B-15JC(1) ATV750B-15PC(1) ATV750B-15SC(1) ATV750B-15JI(1) ATV750B-15PI(1) ATV750B-15SI(1) ATV750B-15DM/883(2) ATV750B-15LM/883(2) 25 15 41 ATV750B-25JC(1) ATV750B-25PC(1) ATV750B-25SC(1) ATV750B-25JI(1) ATV750B-25PI(1) ATV750B-25SI(1) 10 7 74 5962-88726 08 LA(2) 5962-88726 08 3X(2) 5962-88726 09 LA(2) 5962-88726 09 3X(2)
(1)
Package 28J 24P3 28J 24P3 24S 28J 24P3 24S 24DW3 28LW 28J 24P3 24S 28J 24P3 24S 24DW3 28LW 28J 24P3 24S 28J 24P3 24S 24DW3 28LW 24DW3 28LW
Operation Range Commercial (0C to 70C) Commercial (0C to 70C) Industrial (-40C to 85C) Military/883C (-55C to 125C) Class B, Fully Compliant Commercial (0C to 70C) Industrial (-40C to 85C) Military/883C (-55C to 125C) Class B, Fully Compliant Commercial (0C to 70C) Industrial (-40C to 85C) Military/883C (-55C to 125C) Class B, Fully Compliant Military/883C (-55C to 125C) Class B, Fully Compliant
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Notes:
1. Obsolete, please use ATF750C versions. 2. Continue to be available, but please do not use for new designs. For new designs recommend multiple ATF22V10s.
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Ordering Information (Continued)
tPD (ns) 15 tCOS (ns) 9 Ext. fMAXS (MHz) 92 Ordering Code ATV750BL-15JC ATV750BL-15PC(1) ATV750BL-15SC(1) ATV750BL-15JI(1) ATV750BL-15PI(1) ATV750BL-15SI(1) ATV750BL-15DM/883(2) ATV750BL-15LM/883(2) 25 15 37 ATV750BL-25JC(1) ATV750BL-25PC(1) ATV750BL-25SC(1) ATV750BL-25JI19 ATV750BL-25PI(1) ATV750BL-25SI(1) 15 9 92 5962-88726 11 LX(2) 5962-88726 11 3X(2)
(1)
Package 28J 24P3 24S 28J 24P3 24S 24DW3 28LW 28J 24P3 24S 28J 24P3 24S 24DW3 28LW
Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Military/883C (-55C to 125C) Class B, Fully Compliant Commercial (0C to 70C) Industrial (-40C to 85C) Military/883C (-55C to 125C) Class B, Fully Compliant
Notes:
1. Obsolete, please use ATF750C versions. 2. Continue to be available, but please do not use for new designs. For new designs recommend multiple ATF22V10s.
Using "C" Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the "I" to the "C" device (7 ns "C" = 10 ns "I") and de-rate power by 30%.
Package Type 24DW3 28J 28LW 24P3 24S 24-lead, 0.300" Wide, Windowed, Ceramic Dual Inline Package (Cerdip) 28-lead, Plastic J-leaded Chip Carrier OTP (PLCC) 28-pad, Windowed, Ceramic Leadless Chip Carrier (LCC) 24-lead, 0.300" Wide, Plastic Dual Inline Package OTP (PDIP) 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline OTP (SOIC)
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Packaging Information
24DW3, 24-lead, 0.300" Wide, WIndowed, Ceramic Dual Inline Package (Cerdip) Dimensions in Inches and (Millimeters)
MIL-STD-1835 D-9 CONFIG A
.045(1.14) X 30 - 45
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AB
.045(1.14) X 45 PIN NO. 1 IDENTIFY
.012(.305) .008(.203)
.032(.813) .026(.660)
.456(11.6) SQ .450(11.4) .495(12.6) SQ .485(12.3) .300(7.62) REF SQ
.430(10.9) SQ .390(9.91) .021(.533) .013(.330)
.050(1.27) TYP
.043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19)
.022(.559) X 45 MAX (3X)
28LW, 28-pad, Windowed, Ceramic Leadless Chip Carrier (LCC) Dimensions in Inches and (Millimeters)*
MIL-STD-1835 C-4
24P3, 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 AF
1.27(32.3) 1.25(31.7)
PIN 1 .266(6.76) .250(6.35) .090(2.29) MAX .005(.127) MIN
1.100(27.94) REF .200(5.06) MAX SEATING PLANE .151(3.84) .125(3.18) .110(2.79) .090(2.29) .065(1.65) .040(1.02) .325(8.26) .300(7.62) .012(.305) .008(.203) 0 REF 15
.070(1.78) .020(.508) .023(.584) .014(.356)
.400(10.2) MAX
*Controlling dimension: millimeters 17
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ATV750B(L)
Packaging Information
24S, 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters)
.020(.508) .013(.330)
.299(7.60) .420(10.7) .291(7.39) .393(9.98) PIN 1 ID
.050(1.27) BSC .616(15.6) .598(15.2)
.105(2.67) .092(2.34)
.012(.305) .003(.076)
.013(.330) .009(.229) 0 REF 8 .050(1.27) .015(.381)
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