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CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
SCAS688 - JUNE 2003
D 1.8-V Phase Lock Loop Clock Driver for D D D D D D
Double Data Rate ( DDR II ) Applications Spread Spectrum Clock Compatible Operating Frequency: 125 MHz to 400 MHz Low Jitter (Cycle-Cycle): 40 ps Low Static Phase Offset: 50 ps Distributes One Differential Clock Input to Ten Differential Outputs 52-Ball BGA (TI's Micro Star Junior BGA, 0.65mm pitch) and 40-Pin MLF
D External Feedback Pins (FBIN, FBIN) are D D D
Used to Synchronize the Outputs to the Input Clocks Single-Ended Input and Single-Ended Output Modes Meets or Exceeds JEDEC Specification for DDR II Memory PLLs JEDEC Specification Numbers
description
The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and one differential pair of feedback clock output (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS) and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time. CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from -40C to 85C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar Junior is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
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PRODUCT PREVIEW
CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
SCAS688 - JUNE 2003
MicroStar Junior (GQL) Package (TOP VIEW) GND GND
Y1
Y0
Y0
Y5
1 A
2
3
4
Y5
5
Y1 GND Y2 GND Y2 VDDQ CK VDDQ CK VDDQ AGND VDDQ AVDD GND Y3 GND
B
Y6 6
Y6 GND NB NB
C D
Y7 GND Y7 OS
VDDQ
VDDQ
E
NB
NB
PRODUCT PREVIEW
FBIN VDDQ FBIN OE FBOUT VDDQ
F G
NB
NB
VDDQ
VDDQ
H
NB
NB
FBOUT GND Y8 GND
J
K RTB PACKAGE (TOP VIEW) GND Y4 GND Y9 Y3 Y4 Y9 Y8
NC - No Connection NB - No Ball
40 39 38 37 36 35 34 33 32 31
VDDQ Y2 Y2 CK CK VDDQ AGND AVDD VDDQ GND
Y1 Y1 Y0 Y0 VDDQ Y5 Y5 Y6 Y6 VDDQ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21
Y7 Y7 VDDQ FBIN FBIN FBOUT FBOUT VDDQ OE OS
Y3 Y3 Y4 Y4
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VDDQ Y9 Y9 Y8 Y8 VDDQ
CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
SCAS688 - JUNE 2003
Table 1. Terminal Functions
NAME AGND AVDD CK CK FBIN FBIN FBOUT FBOUT OE OS GND BGA G1 H1 E1 F1 E6 F6 H6 G6 F5 D5 B2, B3, B4, B5, C2, C5, H2, H5, J2, J3, J4, J5 D2, D3, D4, E2, E5, F2, G2, G3, G4, G5 A2, A1, D1, J1, K3, A5, A6, D6, J6, K4 A3, B1, C1, K1, K2, A4, B6, C6, K6, K5 MLF 7 8 4 5 27 26 24 25 22 21 10 I I I I O O I I I/O Analog ground Analog power Clock input with a (10 k - 100 k) pull-down resistor Complementary clock input with a (10 k - 100 k) pull-down resistor Feedback clock input Complementary feedback clock input Feedback clock output Complementary feedback clock output Output enable (asynchronous) Output select (tied to GND or VDD) Ground DESCRIPTION
VDDQ
Y[0:9]
38, 39, 3, 11, 14, 34, 33, 29, 19, 16 37, 40, 2, 12, 13, 35, 32, 30, 18, 17
O
Clock outputs
Y[0:9]
O
Complementary clock outputs
Table 2. Function Table
INPUTS AVDD GND GND GND GND 1.8 V Nom 1.8 V Nom 1.8 V Nom 1.8 V Nom 1.8 V Nom X OE H H L L L L H H X X OS X X H L H L X X X X CK L H L H L H L H L H CK H L H L H L H L L H Y L H LZ LZ Y7 Active LZ LZ Y7 Active L H LZ Y H L LZ LZ Y7 Active LZ LZ Y7 Active H L LZ OUTPUTS FBOUT L H L H L H L H LZ Reserved FBOUT H L H L H L H L LZ PLL Bypassed/ Off Bypassed/ Off Bypassed/ Off Bypassed/ Off ON ON ON ON OFF
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PRODUCT PREVIEW
1, 6, 9, 15, 20, 23, 28, 31, 36
Logic and output power
CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
SCAS688 - JUNE 2003
PRODUCT PREVIEW
Figure 1. Logic Diagram (Positive Logic)
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CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
SCAS688 - JUNE 2003
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VDDQ or AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 2.5 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDDQ + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDDQ + 0.5 V Input clamp current, IIK (VI < 0 or VI > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Output clamp voltage, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Continuous current through each VDDQ or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Storage temperature range, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed 2. This value is limited to 2.5 V maximum.
recommended operating conditionsNO TAG
MIN VDDQ Output supply voltage AVDD Supply voltage VIL VIH IOH IOL VIX VI VID TA Low-level input voltage (see Note 2) High-level input voltage (see Note 2) High-level output current (see Figure 2) Low-level output current (see Figure 2) Input differential-pair cross voltage Input voltage level Input differential voltage g (see N t 2 and Fi ( Note d Figure 9) Operating free-air temperature DC AC (VDDQ/2) -0.15 -0.3 0.3 0.6 0 1.7 See Note 1 OE, OS CK, CK 0.65 x VDDQ -9 9 (VDDQ/2)+ 0.15 VDDQ+0.3 VDDQ+0.4 VDDQ+0.4 70 NOM 1.8 VDDQ 0.35 x VDDQ V V mA mA V V V V C MAX 1.9 UNIT V
NOTE 1: The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are ensured. 2. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK and CK VIH and VIL limits are used to define the DC low and high levels for the logic detect state.
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PRODUCT PREVIEW
CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
SCAS688 - JUNE 2003
electrical characteristics over recommended operating free-air temperature range
PARAMETER VIK VOH Input cl inputs) High-level out ut voltage output TEST CONDITIONS II = 18 mA IOH = -100 A IOH = -9 mA IOL = 100 A IOL = 9 mA VO(DL) = 100 mV, OE = L AVDD, VDDQ 1.7 V 1.7 V to 1.9 V 1.7 V 1.7 V 1.7 V 1.7 V 1.9 V 1.9 V CK and CK = L CK and CK = 270 MHz, All outputs are open (not connected to a PCB) VI = VDD or GND VI = VDD or GND VI = VDD or GND VI = VDD or GND 1.9 V 1.9 V 1.8 V 1.8 V 1.8 V 1.8 V 2 2 100 0.5 250 10 500 300 3 3 0.25 0.25 pF pF A A mA MIN TYP MAX -1.2 VDDQ - 0.2 1.1 0.1 0.6 V A V UNIT V V
VOL IO(DL) VOD II
Low-level Low level output voltage Low-level output current, disabled Differential output voltage (see Note 1) CK, CK Input current OE, OS, FBIN, FBIN
IDD(LD) Supply current, static (IDDQ + IADD) IDD Supply current, dynamic (IDDQ + IADD) (see Note 2 for CPD calculation) CK, CK CI CI() Input capacitance Change in input current FBIN, FBIN CK, CK FBIN, FBIN
PRODUCT PREVIEW
NOTE 1: VOD is the magnitude of the difference between the true and complimentary outputs. See Figure 9 for a definition. 2. Total IDD = IDDQ + IADD = fCK x CPD x VDDQ, solving for CPD = (IDDQ + IADD)/(fCK x VDDQ) where fCK is the input frequency, VDDQ is the power supply, and CPD is the power dissipation capacitance.
timing requirements over recommended operating free-air temperature range
PARAMETER fCK fCK tL Clock frequency (operating, see Notes 1 and 2) Clock frequency (application, see Notes 1 and 3) Duty cycle, input clock Stabilization time (see Note 4) TEST CONDITIONS AVDD, VDD = 1.8 V 0.1 V AVDD, VDD = 1.8 V 0.1 V AVDD, VDD = 1.8 V 0.1 V AVDD, VDD = 1.8 V 0.1 V MIN 125 160 40% TYP MAX 400 370 60% 15 s UNIT MHz MHz
NOTE 1: The PLL must be able to handle spread spectrum induced skew. 2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for low speed system debug). 3. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle.
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CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
SCAS688 - JUNE 2003
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Note 1)
PARAMETER ten tdis Enable time, OE to any Y/Y Disable time, OE to any Y/Y Cycle-to-cycle period jitter Static phase offset time (see Note 2) Dynamic phase offset time tsk(o) Output clock skew Period jitter (see Note 3) Half-period jitter (see Notes 3 and 4) Slew rate, OE SR Input clock skew rate Output clock slew rate (see Notes 5 and 6) Output differential-pair cross voltage (see Note 7) SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth TEST CONDITIONS AVDD, VDD = 1.8 V 0.1 V, See Figure 11 AVDD, VDD = 1.8 V 0.1 V, See Figure 11 AVDD, VDD = 1.8 V 0.1 V, See Figure 4 AVDD, VDD = 1.8 V 0.1 V AVDD, VDD = 1.8 V 0.1 V, See Figure 5 AVDD, VDD = 1.8 V 0.1 V, See Figure 10 AVDD, VDD = 1.8 V 0.1 V, See Figure 6 AVDD, VDD = 1.8 V 0.1 V, See Figure 7 AVDD, VDD = 1.8 V 0.1 V, See Figure 8 AVDD, VDD = 1.8 V 0.1 V, See Figures 3 and 9 AVDD, VDD = 1.8 V 0.1 V, See Figures 3 and 9 AVDD, VDD = 1.8 V 0.1 V, See Figures 3 and 9 AVDD, VDD = 1.8 V 0.1 V, See Figure 2 AVDD, VDD = 1.8 V 0.1 V AVDD, VDD = 1.8 V 0.1 V AVDD, VDD = 1.8 V 0.1 V 0 0 -50 TBD -40 -75 0.5 1 1.5 (VDDQ/2) - 0.1 30 0% 2 2.5 2.5 4 3 (VDDQ/2) + 0.1 33 -0.5% MHz MIN TYP MAX 8 8 40 -40 50 TBD 40 40 75 UNIT ns ns ps ps ps ps ps ps ps V/ns V/ns
V kHz
NOTE 1: There are two different termination that are used with the following tests. The load/board in Figure 2 is used to measure the input and output differential-pair cross voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables should be used. 2. Phase static offset time does not include jitter. 3. Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other. 4. The design target is 60 ps. 5. The output slew rate is determined from the IBIS model into the load shown in Figure 3. 6. To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target. Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements of the registered DDR2 DIMM application. 7. Output differential-pair cross voltage specified at the DRAM clock input or the test load.
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PRODUCT PREVIEW
V/ns
CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
SCAS688 - JUNE 2003
Figure 2. Output Load Test Circuit 1
PRODUCT PREVIEW
Figure 3. Output Load Test Circuit 2
Figure 4. Cycle-To-Cycle Period Jitter
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CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
SCAS688 - JUNE 2003
Figure 5. Static Phase Offset
Figure 6. Output Skew
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PRODUCT PREVIEW
CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
SCAS688 - JUNE 2003
PRODUCT PREVIEW
Figure 7. Period Jitter
Figure 8. Half-Period Jitter
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CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
SCAS688 - JUNE 2003
Figure 9. Input and Output Slew Rates
Figure 10. Dynamic Phase Offset
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PRODUCT PREVIEW
CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
SCAS688 - JUNE 2003
Figure 11. Time Delay Between OE and Clock Output (Y, Y)
PRODUCT PREVIEW
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CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
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MECHANICAL DATA
GQL (R-PBGA-N56)
4,60 4,40 0,65 0,325 K J 3X Via Hole Without Ball 0,65 5,85 0,325 H G F E
PLASTIC BALL GRID ARRAY
3,25
C B A 1 2 3 4 5 6
A1 Corner
Bottom View
1,00 MAX 0,08
Seating Plane 56x 0,45 0,35 0,25 0,15 4200583/D 06/2002 NOTES: A. B. C. D. E. All linear dimensions are in millimeters. This drawing is subject to change without notice. MicroStar Junior BGA configuration Falls within JEDEC MO-225 variation BA. This package is tin-lead (SnPb). Refer to the 56 ZQL package (drawing 4204437) for lead-free.
0,05 M
MicroStar Junior is a trademark of Texas Instruments.
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PRODUCT PREVIEW
EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE EEEEE
7,10 6,90
Missing Via Hole Indicates Pin A1 Quadrant
D
CDCU877 1.8-V PHASE CLOCK LOOP CLOCK DRIVER
SCAS688 - JUNE 2003
MECHANICAL DATA
RTB (MLF2-N40)
2X 0.10 A D b 4X P D1 D2 D2/2 D1/2 2X N 0.10 C B 4X P 1 5 0.60 DIA. 6 0.45 1 2 3 (Ne-1)Xe E2 E1 E E2/2 REF. E1/2 E/2 2 3 N PIN1 ID 0.20 R. C A 4 D/2 0.10
M
HIGH-DENSITY MATRIX LEADFRAME
SEE DETAIL "A" FOR PIN #1 ID AND TIE BAR MARK OPTION
CA
B
0.25 MIN. L
0.10
C
B B e (Nd-1)Xe
0.25 MIN.
PRODUCT PREVIEW
2X
0.10 2X
C
A
TOP VIEW
REF.
BOTTOM VIEW
10 0.05 A A1 A2 A3 C b 4 A1 11
S Y M B O L
COMMON DIMENSIONS MIN.
- 0.00 -
N O T E
NOM.
0.85 0.01 0.65 0.20 REF. 6.00 BSC 5.75 BSC 6.00 BSC 5.75 BSC
MAX.
0.90 0.05 0.80 D
SECTION "C-C"
SCALE: NONE C C C L
A A1 A2 A3 D D1 E E1 0 P R
e
S Y M B O L
12 0.24 0.13 0.42 0.17 0.60 0.23 C
PITCH VARIATION D MIN. NOM.
0.50 BSC 40 10 10 0.30 0.18 0.00 2.75 2.75 0.40 0.23 0.20 2.90 2.90 0.50 0.30 0.45 3.05 3.05
N O T E
MAX.
A A A B C
FOR EVEN TERMINAL/SIDE
C L 0
e N Nd Ne L b Q
C SEATING PLANE
e
D2 E2
TERMINAL TIP
SIDE VIEW FOR ODD TERMINAL/SIDE
NOTES: A. B. C. D. E.
N is the number of terminals Dimension b applies to the plated terminal and is measured Q and R apply only for the straight tiebar shapes. Applied only for terminals 40-pin HP-VFQFP-N, 6.0 x 6.0 mm body size, 0.5-mm pitch, variation VJJD-2, E2 & D2 = 2.9 mm 0.15 mm
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Copyright 2003, Texas Instruments Incorporated

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