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| CDB5540 CDB5541 CDB5540/41 Evaluation Board and Software Features l RS-232 General Description The CDB5540/41 is an inexpensive tool designed to evaluate the performance of the CS5540/41 16-pin Analog to Digital Converters. This document, as well as the CS5540 or CS5541 data sheet should be read thoroughly before using the CDB5540/41 Evaluation System. The evaluation system consists of a CDB5540/41 Board and PC software which allows the user to easily capture and analyze data. The provided analysis functions in the software include Time Domain Analysis, Histogram Analysis, and Frequency Domain Analysis. ORDERING INFORMATION: CDB5540 Evaluation System CDB5541 Evaluation System Serial Communication with PC l On-board Microcontroller l On-board Voltage Reference l LabWindows/CVI Evaluation Software - Chip Control and Data Capture - FFT Analysis - Time Domain Analysis - Noise Histogram Analysis l Supports the CS5540 and CS5541 16-pin ADCs VOLTAGE REFERENCE VA+ REF+ REFVARESET CIRCUITRY AGND VA+ LEDs AIN1+ AIN1AIN2+ AIN2CS SDI SDO SCLK CS5540 CS5541 TEST SWITCHES AVR Microcontroller RS232 TRANSCEIVER RS232 CONNECTOR CRYSTAL 32.768 kHz CRYSTAL 3.684 MHz Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2001 (All Rights Reserved) JUL `01 DS503DB1 1 CDB5540 CDB5541 TABLE OF CONTENTS 1. HARDWARE ............................................................................................................................. 4 1.1 Introduction ........................................................................................................................ 4 1.2 Evaluation Board Overview ................................................................................................ 4 1.2.1 Analog Section ...................................................................................................... 4 1.2.2 Digital Section ....................................................................................................... 4 1.2.3 Serial Interface ...................................................................................................... 5 1.2.4 Clock Source Options ........................................................................................... 5 1.2.5 Headers, Jumpers, and DIP Switches .................................................................. 5 2. SOFTWARE .............................................................................................................................. 7 2.1 Installation Procedure ........................................................................................................ 7 2.2 Using the Software ............................................................................................................. 7 2.2.1 Selecting the COM Port and Part .......................................................................... 7 2.2.2 Setup Window Functions ...................................................................................... 7 2.3 Data Collection Window Overview ..................................................................................... 8 2.3.1 Histogram Plots ..................................................................................................... 9 2.3.2 Frequency Domain (FFT) Plots ........................................................................... 10 2.3.3 Time Domain Plots .............................................................................................. 10 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales/cfm LabWindows and CVI are registered trademarks of National Instruments Corporation, MICROWIRE is a trademark of National Semiconductor Corporation, SPI is a registered trademark of International Business Machines Corporation, Windows 95 is a registered trademark of Microsoft Corporation. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS503DB1 CDB5540 CDB5541 LIST OF FIGURES Figure 1. Title Screen................................................................................................................... 11 Figure 2. Setup Window............................................................................................................... 11 Figure 3. Frequency Domain Analysis ......................................................................................... 12 Figure 4. Configuration Panel ...................................................................................................... 12 Figure 5. Time Domain Analysis .................................................................................................. 13 Figure 6. Histogram Analysis ....................................................................................................... 13 Figure 7. Power Supply Configuration ......................................................................................... 14 Figure 8. CDB5540/41 ADC Section............................................................................................ 15 Figure 9. Voltage Reference and External Connectors................................................................ 16 Figure 10.Microcontroller, Test Switches and LED's .................................................................... 17 Figure 11.CDB5540/41 Layout (Silkscreen).................................................................................. 18 Figure 12.CDB5540/41 Layout (Top) ............................................................................................ 19 Figure 13.CDB5540/41 Layout (Bottom)....................................................................................... 20 LIST OF TABLES Table 1. Default Header and DIP Switch Settings .......................................................................... 6 Table 2. Voltage Reference Settings .............................................................................................. 6 Table 3. MCLK Settings .................................................................................................................. 6 Table 4. DIP Switch SW1 Settings.................................................................................................. 6 DS503DB1 3 CDB5540 CDB5541 1. HARDWARE 1.1 Introduction The CDB5540 and CDB5541 evaluation systems provide a quick means of testing the CS5540 and CS5541 Analog-to-Digital Converters (ADCs). The CS5540/41 are low-power, low-voltage - analog-to-digital converters (ADC), targeted at temperature and pressure measurement, and various portable devices where low power consumption is required. The CDB5540/41 evaluation boards are equipped with either a CS5540 or a CS5541 and interfaces directly to a PC though an RS-232 serial interface. The included analysis software allows the user to control the various functions of the CS5540/41, as well as capture and save data. The software also provides data analysis tools to display the time domain, frequency domain, and noise histogram performance for a captured set of data. VCC, the board logic supply voltage, and VD+, the digital ADC supply voltage. HDR13 is populated such that AGND, the analog ADC ground, is directly connected to DGND, GND1, and VA- (the digital ADC ground, board logic ground, and VAof the ADC, respectively). All of this is represented in Figure 7, which depicts the power supply configuration. Figures 11-13 show layout plots of the evaluation board, with the ground planes removed, so that signal traces may be seen easier. This can serve as an aid when designing a board. 1.2.1 Analog Section The evaluation board runs at 32.768 kHz. However, by configuring HDR2, a variable clock may be provided from either the microcontroller or from an external source connected to the XOSC connector on J5. Analog input signals can be connected to the converter via connectors J2 (CH 1) and J12 (CH 2). Note that a simple RC network filters the input to reduce broadband noise. The evaluation system provides three voltage reference options: the on-board 2.5V reference, the power supply voltage, or an external voltage reference source, as shown in Table 2. When using an external reference, the signal must be connected to XREF+ and XREF- on connector J3. A schematic of the ADC and the components directly around it, are depicted in Figure 8. A schematic representation of the voltage reference circuit, as well as the external signal connectors, is portrayed in Figure 9. 1.2 Evaluation Board Overview The evaluation board is partitioned into two main sections: analog and digital. The analog section consists of the ADC and a voltage reference. The digital section consists of the AVR microcontroller, the hardware test switches, the reset circuitry and the RS-232 interface. The evaluation board's analog and digital sections operate from a single +3.0 V power supply and interface to an IBM compatible PC through the RS232 interface. The board comes equipped with an AVR microcontroller and a 9-pin RS-232 cable which physically interfaces the evaluation board to the PC. The software provides a means to display and evaluate the performance of the ADC in the time or frequency domains. The evaluation board supports a single supply configuration. The AGND post should be connected to 0 V, and the VA+ post should be connected to 3.0 V. HDR14 is populated such that VA+ powers 1.2.2 Digital Section Figure 10 represents the schematic of the digital section of the evaluation board. It contains the microcontroller, test switches, and an RS-232 interface IC. The test switches aid in debugging communication problems between the board and the PC. The microcontroller, which derives its clock from a 3.684 MHz crystal, is initially configDS503DB1 4 CDB5540 CDB5541 ured to communicate via RS-232 at 19200 baud, no parity, 8-bit data, and 1 stop bit. The baud rate can be changed with software to go as fast as 38400 baud. The microcontroller can be reset by depressing pushbutton switch S1. On reset or upon power-up, the LED's on the board will count down, until only LED4 remains lit. This LED is the POWER LED, and informs the user that the board is powered on. LED1, the BUSY LED, lights when the microcontroller is busy performing an operation. It is normal for the LED to turn on and off, and is useful when collecting large data sets. vides the 3.6864 MHz clock by integer values to produce the clock output. 3) An external clock can be provided by the user, and connected to the XOSC post on J5. The "External Clock Source" option in the software should be selected when using an external clock source, and HDR2 on the evaluation board should be set according to Table 3. 1.2.5 Headers, Jumpers, and DIP Switches Table 1 describes the headers and DIP switches on the evaluation board, with their appropriate default settings. Table 2 describes the various jumper settings for HDR11 and HDR9, which select the voltage reference that is used. HDR2 selects the MCLK source that is used. Jumper settings are depicted in Table 3. DIP switch SW1 is used to control the AVR modes and Table 4 illustrates the various modes it can be set to. When testing the RS-232 link in the PC software, the DIP switches should all be in the CLOSED position. Configurations other than those specified are not recommended. 1.2.3 Serial Interface The CS5540/41 serial interface is SPI and MICROWIRETM compatible. The interface control lines (CS, SDO, and SCLK) are connected to the AVR microcontroller on the CDB5540/41. 1.2.4 Clock Source Options The evaluation board provides three sources for the master clock: the on-board crystal, the microcontroller, and an external clock signal. 1) The 32.768 kHz crystal oscillator can be chosen by selecting the "Crystal Oscillator - 32.768 kHz" option in the software. HDR2 on the evaluation board should be set according to Table 3. 2) The microcontroller can be used to generate a clock for the ADC. The microcontroller's clock can be chosen by selecting the "Microcontroller" option in the software. HDR2 on the evaluation board should be set according to Table 3. The clock frequency can be selected by changing the "Oscillator Frequency" box in the software. Note that the frequency options are limited by the microcontroller's counter/timer circuitry, which di- DS503DB1 5 CDB5540 CDB5541 Name HDR1. HDR2. HDR9. Functional Description Tests UART/RS-232 communication link between the microcontroller and the PC. Selects MCLK source. Selects VREF-. Default Setting RS-232 set to Normal Mode. 32.768 kHz Crystal On-Board Reference. Default Jumpers O O XTAL O uC O XOSC O XREF- O VA- O VA+ O REF- O XREF+ O VA- O VA+ O REF+ O O O O MCLK O MCLK O MCLK O O O O O O O O VREFVREFVREFVREFVREF+ VREF+ VREF+ VREF+ HDR11. Selects VREF+. On-Board Reference. SW1. . Controls AVR modes. CS5540 CS5541 SW1, SW2, SW3 - OPEN SW1, SW3 - OPEN SW2 - CLOSED Table 1. Default Header and DIP Switch Settings Reference REF. Description Selects On-Board Reference Selects Power Supply Voltage Selects External Reference HDR11 XREF+ O VA- O VA+ O REF+ O XREF+ O VA- O VA+ O REF+ O XREF+ O VA- O VA+ O REF+ O O O O O O O O O O O O O VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ HDR9 XREF- O VA- O VA+ O REF- O XREF- O VA- O VA+ O REF- O XREF- O VA- O VA+ O REF- O O O O O O O O O O O O O VREFVREFVREFVREFVREFVREFVREFVREFVREFVREFVREFVREF- Supply. XREF. Table 2. Voltage Reference Settings Reference XTAL. uC. XOSC. Description Selects OnBoard Crystal Selects Microcontroller Clock Selects External MCLK HDR2 MCLK O MCLK O MCLK O MCLK O MCLK O MCLK O MCLK O MCLK O MCLK O O XTAL O uC O XOSC O XTAL O uC O XOSC O XTAL O uC O XOSC Eval Board Mode CS5540 SW1 is OPEN SW2 is OPEN SW3 is OPEN CS5541 SW1 is OPEN SW2 is CLOSED SW3 is OPEN RS-232 Test Mode SW1 is CLOSED SW2 is CLOSED SW3 is CLOSED SW1 Settings 1 2 3 OPEN SW3 SW2 SW1 1 2 3 Table 3. MCLK Settings OPEN SW3 SW2 SW1 1 2 3 OPEN SW3 SW2 SW1 Table 4. DIP Switch SW1 Settings 6 DS503DB1 CDB5540 CDB5541 2. SOFTWARE The evaluation system comes with software and an RS-232 cable to link the evaluation board to the PC. The executable software was developed with LabWindows/CVI and meant to run under Windows 95 or later. After installing the software, read the readme.txt file for any last minute changes in the software. software's title, revision number, copyright date, etc. Additionally, at the top of the screen is a menu bar which displays user options. Notice, the menu bar item Window is initially disabled. This eliminates any conflicts with the mouse or concurrent use of modems. Before proceeding any further, the user is prompted to select the serial communication port. 2.1 Installation Procedure 1) 2) 3) 4) 5) 6) Turn on the PC, running Windows 95 or 98. Insert the Installation Diskette #1 into the PC. Select the Run option from the Start menu. At the prompt, type: A:\SETUP.EXE 2.2.1 Selecting the COM Port and Part To initialize a port, pull down option ComPorts from the menu bar and select either COM1 or COM2. Next, the user is prompted to select the appropriate part under the Parts menu. After a port is initialized and the correct part is selected, it is a good idea to test the RS-232 link between the PC and the evaluation board. To do this, pull down the Setup menu from the menu bar and select the option TEST RS232. The user is then prompted to set all the evaluation board's test switches to the CLOSED position and then reset the board. Once this is done, proceed with the test. If the test fails, check the hardware connection and repeat again. Otherwise, set the test switches back to the correct mode as specified in this document, and press reset again. If the user wishes to change the speed of communications between the PC and the microcontroller, this can be achieved through the BAUD RATE option. 7) 8) 2.2.2 Setup Window Functions To make sure that the software and evaluation board are set up correctly, it is recommended that the user proceed to the Setup Window and test the functionality of the part before proceeding (Figure 2). To access the Setup Window, the user can pull down the Window menu item, or press F1 on the keyboard. The following describes the various options and indicators in the Setup Window. Clock Source: This pull-down menu allows the user to select the type of clock that will be used 7 Note: The software is written to run with 640 x 480 resolution; however, it will work with 1024 x 768 resolution. If the user interface seems to be a little small, the user might consider setting the display settings to 640 x 480. (640 x 480 was chosen to accommodate a variety of computers). 2.2 Using the Software At start-up, the title screen appears first (Figure 1). This window contains information concerning the DS503DB1 CDB5540 CDB5541 with the ADC, so that the software knows what to expect from the microcontroller. Selecting from this menu also gives the user a warning to examine the jumper settings on HDR2 of the evaluation board. There are three options available on this menu: On-board Crystal Oscillator - 32 kHz - This option tells the software that the master clock for the ADC is coming from the on-board 32.768 kHz crystal. This option is selected by default. Microcontroller - This option tells the software that the microcontroller will provide the ADC with a master clock. The microcontroller's clock frequency is user-selectable from the Setup Window. The clock frequency is limited to integer sub-multiples of the microcontroller's 3.6864 MHz master clock (3.6864 MHz / N). Be sure that the jumper is set properly on HDR2 when this option is selected. External Clock Source - This option tells the software that the master clock for the ADC will be coming from an outside source. The clock source should be connected to the XOSC post on J5. Oscillator Frequency: This box displays the frequency of the oscillator that the ADC is running on. When using an external clock source, the user can type in the frequency of the clock source, and the FFT plots will scale accordingly. When using the microcontroller as a clock source, the user should adjust this value until it is close to the desired frequency. The value in this box will automatically be adjusted to a frequency that the microcontroller can provide. Power-down Mode: This pull-down menu allows the user to put the ADC in sleep or standby mode. The ADC will power down according to the data sheet specifications. SPI Init: This button issues an SPI Initialization command to the CS5541. Command Word Components Channel Select: This pull-down menu allows the user to select which channel the ADC will convert. In the CS5541, this affects the command word. Default selection is "AIN1+/-". Unipolar/Bipolar: This pull-down menu controls whether unipolar or bipolar mode is used. In the CS5541, this affects the command word. Default selection is "Bipolar". Filter Select: This pull-down menu controls which digital filter is used for the CS5541. In the CS5541, this affects the command word. Default selection is "Four Cycle Settling - 53.7 Hz". Conversion Calibration Select: This pull-down menu controls which calibration mode is used in the CS5541. In the CS5541, this affects the command word. Default selection is "One-Time Calibration". Command Word: This box displays the command word that is sent to the CS5541. For more information on the command word and command word format refer to the CS5541 data sheet. Sampling Frequency: This box displays the computed sampling frequency for the specified oscillator frequency. This number is used when performing FFT analysis. 2.3 Data Collection Window Overview The Data Collection Window is used to collect and analyze data sets using the evaluation board. The software supports Time Domain, Frequency Domain (FFT) and Histogram analysis of collected data sets. To go to the Data Collection Window, pull down the Window menu item and select "Data Collection Window", or press F2 on the keyboard. The following controls and indicators are present in the Data Collection Window regardless of what test is being performed. COLLECT: Initiates the data conversion collection process. COLLECT has two modes of opera- 8 DS503DB1 CDB5540 CDB5541 tion: collect from file or collect from converter. To collect from a file, a previously saved file from the ComPorts->DISK menu bar option must be selected. Once a file is selected, its content will displayed on the graph when the COLLECT button is pressed. If the user is collecting conversions from the evaluation board to analyze, the appropriate COM port must be selected. The user is then free to collect the preset number of conversions (preset by the CONFIG pop-up menu discussed below). Notice, there is a significant acquisition time difference between collecting from a file and collecting from the evaluation board. Data can only be collected from the evaluation board at the converter's current sampling frequency, and will take much longer than retrieving previously collected data from a file. CANCEL: This button allows the user to exit from the COLLECT algorithm during a collection. It is recommended that the user reset the evaluation board after pressing this button, so that the evaluation board will stop collecting data and wait for the next command. OUTPUT: This button calls up a pop-up window which allows the user to save the collected data set to a file or print out the information on the screen. Two printing options are available: printing only the plot data, and printing the entire screen including the calculated statistics for the current analysis mode. ZOOM: Pressing this button allows the user to zoom in on a specific portion of the current graph. To zoom, click on the ZOOM icon, then click on the graph to select one corner of the desired Zoom area. When prompted, click on the graph again to select the opposite corner of the desired zoom area. Once an area has been zoomed to, the printing functions can be used to print a hard copy of that region. Click on RESTORE when done with the zoom function to display the entire data set graph. A region can also be magnified further by clicking on the ZOOM button again. RESTORE: Restores the display of the graph after zoom has been entered. No matter how far in the user has magnified the data plot, the RESTORE button will return to the fully zoomed-out data plot. TIME DOMAIN / FFT / HISTOGRAM Selector: This pull-down menu selects between time domain, frequency domain, and histogram mode to perform and display the appropriate analysis of the data set. CONFIG: Opens a pop-up panel (Figure 4) to configure how much data is to be collected, and how to process the data once it is collected. The following are controls and indicators associated with the CONFIG panel. SAMPLES: Allows the user to select the number of conversions to collect, between 16 and 32,768. WINDOW: Used in the Power Spectrum Window to calculate the FFT. Windowing algorithms include the Blackman, Blackman-Harris, Hanning, 5-term Hodie, and 7-term Hodie. The 5-term Hodie and 7-term Hodie are windowing algorithms developed at Cirrus Logic. If information concerning these algorithms is needed, call technical support. AVERAGE: Sets the number of consecutive FFT's to perform and average. LIMITED NOISE BANDWIDTH: Limits the amount of noise in the converters bandwidth. Default is 0 Hz. OK: Accept the changes and close the window 2.3.1 Histogram Plots The following is a description of the indicators associated with Histogram analysis (Figure 6). BIN: Displays the x-axis value of the cursor on the Histogram. This represents the output code from the part. MAGNITUDE: Displays the y-axis value of the cursor on the Histogram. This represents the num9 DS503DB1 CDB5540 CDB5541 ber of times a certain output code occurred in the collected data set. MAXIMUM: Indicator for the maximum value of the collected data set. MEAN: Indicator for the mean (average) of the data sample set. MINIMUM: Indicator for the minimum value of the collected data set. STD. DEV.: Indicator for the Standard Deviation of the collected data set. VARIANCE: Indicates the Variance for the current data set. nitude to the magnitude of the first four harmonics and the noise. SNR: Indicator for the Signal-to-Noise Ratio in dB. This is the ratio of the signal magnitude to the magnitude of the noise (an average noise value is included in place of the first four harmonics). S/PN: Indicator for the Signal-to-Peak Noise Ratio in dB. This is the ratio of the signal magnitude to the magnitude of the highest noise component not included in the harmonics of the signal. # of AVG: Displays the number of FFT's averaged in the current display. 2.3.2 Frequency Domain (FFT) Plots The following describe the indicators associated with Frequency Domain (FFT) analysis (Figure 3). FREQUENCY: Displays the x-axis value of the cursor on the FFT display. This represents the center frequency of the currently selected bin in Hz. MAGNITUDE: Displays the y-axis value of the cursor on the FFT display. This represents the total power in dB contained in the selected bin. S/D: Indicator for the Signal-to-Distortion Ratio, in dB. This is the ratio of the signal magnitude to the magnitude of the first four harmonics. S/N+D: Indicator for the Signal-to-Noise + Distortion Ratio in dB. This is the ratio of the signal mag- 2.3.3 Time Domain Plots The following indicators are associated with Time Domain analysis (Figure 5). COUNT: Displays current x-position of the cursor on the time domain display. This represents the position of the code within the collected sample set. MAGNITUDE: Displays current y-position of the cursor on the time domain display. This represents the actual code from the converter. MAXIMUM: Indicator for the maximum value of the collected data set. MINIMUM: Indicator for the minimum value of the collected data set. 10 DS503DB1 CDB5540 CDB5541 Figure 1. Title Screen Figure 2. Setup Window DS503DB1 11 CDB5540 CDB5541 Figure 3. Frequency Domain Analysis Figure 4. Configuration Panel 12 DS503DB1 CDB5540 CDB5541 Figure 5. Time Domain Analysis Figure 6. Histogram Analysis DS503DB1 13 14 CON_BANANA VA+ L1 10 R3 D6 1N5228B VCC VD+ HDR14 VA+ J9 FERRITE_BEAD C27 47UF .1UF C33 AGND AGND AGND CON_BANANA HDR13 AGND VA- J11 AGND DGND GND1 CDB5540 CDB5541 Figure 7. Power Supply Configuration DS503DB1 DS503DB1 AIN2VREF+ HDR3 AIN1+ 10 10 R12 C23 .01UF C10 AGND AGND 10 C9 .01UF C6 4700PF COG 4700PF COG C8 R25 HDR11 HDR6 R22 C30 .01UF AGND 4700PF COG AIN1HDR4 10 AIN2+ 10 R11 C24 C20 .01UF AGND 10 VREF- HDR5 R21 R26 .01UF AGND C29 HDR9 .01UF U6 AGND VA- 10 R18 10 C36 .1UF DGND C21 VD+ .1UF CS5541_BP U1 TP60 TP61 TP64 TP66 TP67 TP69 TP72 TP73 1 2 3 4 5 6 7 8 TP59 TP62 TP63 TP65 TP68 TP70 TP71 TP74 AIN1+ AIN1VAVA+ /CS SCLK SDI OSC1 R27 AIN2+ AIN2VREF+ VREFDGND VD+ SDO OSC2 16 15 14 13 12 11 10 9 TP43 TP46 TP47 TP50 TP51 TP54 TP55 TP58 TP44 TP45 TP48 TP49 TP52 TP53 TP56 TP57 C22 .1UF C19 R10 10 AGND .01UF DGND DGND VA+ 10 Y2 32.768KHZ R17 R19 10M C34 CS5541_BS 1 2 3 4 5 6 7 8 AIN1+ AIN1VAVA+ /CS SCLK SDI OSC1 AIN2+ AIN2VREF+ VREFDGND VD+ SDO OSC2 16 15 14 13 12 11 10 9 VD+ .1UF R44 51.1K PD5 R45 51.1K R46 51.1K R47 51.1K AGND HDR3X2 HDR2 1 2 3 4 5 6 R1 301 XOSC /CS PB5 HDR7 SDO SCLK Reference XTAL. uC. Description Selects OnBoard Crystal Selects Microcontroller Clock Selects External MCLK HDR2 MCLK O MCLK O MCLK O MCLK O MCLK O MCLK O MCLK O MCLK O MCLK O O XTAL O uC O XOSC O XTAL O uC O XOSC O XTAL O uC O XOSC XOSC. CDB5540 CDB5541 Figure 8. CDB5540/41 ADC Section 15 CDB5540 CDB5541 J2 AGND AIN1+ AIN1AGND 1 2 3 4 J12 AIN1+ AIN1AGND AIN2+ AIN2AGND 1 2 3 4 TERM_BLOCK AIN2+ AIN2XOSC DGND 2 1 XOSC TERM_BLOCK AGND TERM_BLOCK AGND J5 DGND U2 1 2 3 4 NC IN NC GND NC NC OUT NC 8 7 6 5 VA+ R2 200 C4 C7 .1UF REF+ C5 .1UF MAX6192 4.7UF TANT R4 200 REF- AGND REF+ VA+ VAXREF+ HDR4X2 HDR11 1 2 3 4 5 6 7 8 VREF+ REFVA+ VAXREF- HDR4X2 HDR9 1 2 3 4 5 6 7 8 TERM_BLOCK XREF+ VREFXREF2 1 XREF+ XREF- J3 Reference REF. Description Selects On-Board Reference Selects Power Supply Voltage Selects External Reference HDR11 XREF+ O VA- O VA+ O REF+ O XREF+ O VA- O VA+ O REF+ O XREF+ O VA- O VA+ O REF+ O O O O O O O O O O O O O VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ VREF+ HDR9 XREF- O VA- O VA+ O REF- O XREF- O VA- O VA+ O REF- O XREF- O VA- O VA+ O REF- O O O O O O O O O O O O O VREFVREFVREFVREFVREFVREFVREFVREFVREFVREFVREFVREF- Supply. XREF. Voltage Reference Settings Figure 9. Voltage Reference and External Connectors 16 DS503DB1 VCC VCC C17 D2 C11 750K GND1 C13 RESET S1 U5 GND1 8 7 6 C16 D1 .1UF LED1 LED2 LED3 R7 3.6864MHZ R13 AT90S8515_4PC GND1 10K 1 6 2 7 3 8 4 9 5 33PF COG GND1 GND1 GND1 SW1 Settings 1 2 3 Eval Board Mode CS5540 SW1 is OPEN SW2 is OPEN SW3 is OPEN OPEN SW3 SW2 SW1 CS5541 SW1 is OPEN SW2 is CLOSED SW3 is OPEN 1 2 3 OPEN SW3 SW2 SW1 RS-232 Test Mode SW1 is CLOSED SW2 is CLOSED SW3 is CLOSED 1 2 3 OPEN SW3 SW2 SW1 DIP Switch SW1 Settings CDB5540 CDB5541 Figure 10. Microcontroller, Test Switches and LED's R14 R15 R16 C1 5.11K 5.11K 5.11K DS503DB1 C3 VCC 1N4001 C15 .1UF .1UF .1UF U3 10UF TANT VCC 1 2 3 5 4 C18 GND1 GND1 HDR1 1 2 3 4 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 .1UF SW_B3W_1100 .1UF /CS PB5 SDO SCLK ALEPROG C12 R29 R30 R31 R32 LED4 VCC C1+ V+ GND C1T1OUT \ R1IN C2+ R1OUT C2VT1IN T2OUT T2IN R2IN R2OUT MAX3232CPE 200 200 200 200 .1UF GND1 HDR2X2 P3_2 PD5 GND1 LED_555_5003 SW_DIP_3 DE9F_RA J4 R20 200 P3_6 P3_7 OPEN C2 33PF COG RS-232 to PC TP27 TP28 TP40 TP39 TP38 TP37 TP36 TP35 TP34 TP33 TP32 TP31 TP30 TP29 TP26 TP25 TP24 TP23 TP22 TP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PB0(T0) PB1(T1) PB2(AIN0) PB3(AIN1) PB4(/SS) PB5(MOSI) PB6(MISO) PB7(SCK) /RESET PD0(RXD) PD1(TXD) PD2(/INT0) PD3(/INT1) PD4 PD5(OC1A) PD6(/WR) PD7(/RD) XTAL2 XTAL1 GND SW1 SW2 SW3 VCC (AD0)PA0 (AD1)PA1 (AD2)PA2 (AD3)PA3 (AD4)PA4 (AD5)PA5 (AD6)PA6 (AD7)PA7 ICP ALE OC1B (A15)PC7 (A14)PC6 (A13)PC5 (A12)PC4 (A11)PC3 (A10)PC2 (A9)PC1 (A8)PC0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 TP18 TP17 TP20 TP21 TP19 TP14 TP8 TP16 TP15 TP13 TP7 TP12 TP11 TP10 TP9 TP6 TP5 TP4 TP3 TP2 1 2 3 SW1 Y1 17 18 CDB5540 CDB5541 DS503DB1 Figure 11. CDB5540/41 Layout (Silkscreen) DS503DB1 CDB5540 CDB5541 Figure 12. CDB5540/41 Layout (Top) 19 20 CDB5540 CDB5541 Figure 13. CDB5540/41 Layout (Bottom) DS503DB1 * Notes * |
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