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CY26404
PacketClockTM One-PLL General Purpose Clock Generator
Features * Integrated phase-locked loop * Low-skew, low-jitter, high-accuracy outputs * 3.3V operation with 2.5V output option * 16-TSSOP Part Number CY26404 Outputs 6 Input Frequency 20 MHz Benefits Internal PLL with up to 400-MHz internal operation Meets critical timing requirements in complex system designs Enables application compatibility Industry standard package saves on board space Output Frequency Range 2 x 50 MHz, 1 x 100 MHz
Logic Block Diagram
XIN XOUT P OSC. Q VCO OUTPUT MULTIPLEXER AND DIVIDERS CLK1 50 MHz CLK2 50 MHz CLK3 off CLK4 off CLK5 100 MHz CLK6 off SCL SDA
Pin Configuration
CY26404 16-pin TSSOP
XIN VDD AVDD SDA AVSS VSSL CLK1 CLK2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT CLK6 CLK5 VSS CLK4 VDDL SCL CLK3
PLL
SPI Control
VDDL
VSSL
VDD
AVDD
AVSS
VSS
Output CLK1 CLK2 CLK3 CLK4 CLK5 CLK6
Pin 7 8 9 12 14 15
Default Frequency 50 50 OFF OFF 100 OFF
Unit MHz MHz
MHz
Cypress Semiconductor Corporation Document #: 38-07470 Rev. **
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised December 9, 2002
CY26404
Pin Description
Name XIN VDD AVDD SDA AVSS VSSL CLK 1 CLK 2 CLK 3 SCL VDDL CLK 4 VSS CLK 5 CLK 6 XOUT[1] Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 All programmable registers in the CY26404 are addressed with eight bits and contain eight bits of data. The CY26404 is Description a slave device with an address of 1101010 (6AH). Reference Table 1 lists the SPI registers and their definitions. Specific Input register definitions and their allowable values are listed below. Voltage Supply Analog Voltage SupplyFrequency Reference Serial DataThe REF can be a crystal or a driven frequency. For crystals, Input the frequency range must be between 8 MHz and 30 MHz. For Analog Ground a driven frequency, the frequency range must be between CLK1-CLK4 Ground 133 MHz. 1 MHz and Clock Output 1 = 50 MHz at VDDL Level Using a Crystal as the Reference Input Clock Output 2 = 50 MHz at VDDL Level The input crystal oscillator of the CY26404 is an important Default is Off feature because of the flexibility it allows the user in selecting a crystal Serial Clock Input as a REF source. The input oscillator has programmable gain, allowing for maximum compatibility with a CLK1-CLK4 Voltage Supply (2.5V or 3.3V)manufacturer, process, perforreference crystal, regardless of mance and quality. Default is Off Ground Programmable Crystal Input Oscillator Gain Settings Clock Output 5 = 100 crystal oscillator gain (XDRV) is controlled by two The Input MHz at VDD Level bits Default is Off in register 12H, and are set according to Table 2. The parameters controlling the gain are the crystal frequency, the Reference internal crystal parasitic resistance (ESR, available from the Output manufacturer), and the CapLoad setting during crystal start-up. Bits 3 and 4 of register 12H control the input crystal oscillator gain setting. Bit 4 is the MSB of the setting, and bit 3 is the LSB. The setting is programmed according to Table 2. All other bits in the register are reserved and should be programmed low. See Table 3 for bit locations and values. Using an External Clock as the Reference Input The CY26404 can also accept an external clock as reference, with speeds up to 133 MHz. With an external clock, the XDRV (register 12H) bits must be set according to Table 4.
Frequency Calculations and Register Definitions Using the Serial Programming Interface (SPI)
The CY26404 provides an industry-standard serial interface for volatile, in-system programming of unique frequencies and options. Serial programming allows for quick design changes and product enhancements, eliminates inventory of old design parts, and simplifies manufacturing. The SPI provides volatile programming, i.e., when the target system is powered down, the CY26404 reverts back to its default state. When the system is powered back up, the SPI registers will need to be reconfigured again. Table 1. Summary Table - CY26404 Programmable Registers Register 09H 0CH 12H 13H 40H 41H 42H Description CLKOE control DIV1SRC mux and DIV1N divider Input crystal oscillator drive control Input load capacitor control Charge Pump and PB counter PO counter, Q counter D7 0 D6 0 D5
D4 CLK5
D3 CLK4
D2 CLK3
D1 CLK2
D0 CLK1
CLK6
DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0) 0 CapLoad(7) 1 PB(7) PO 0 CapLoad(6) 1 PB(6) Q(6) 0 CapLoad(5) 0 PB(5) Q(5) XDRV(1) CapLoad(4) Pump(2) PB(4) Q(4) XDRV(0) CapLoad(3) Pump(1) PB(3) Q(3) 0 CapLoad(2) Pump(0) PB(2) Q(2) 0 CapLoad(1) PB(9) PB(1) Q(1) 0 CapLoad(0) PB(8) PB(0) Q(0)
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CY26404
Table 1. Summary Table - CY26404 Programmable Registers (continued) Register 44H 45H 46H 47H DIV2SRC mux and DIV2N divider Description Crosspoint switch matrix control D7 D6 D5 D4 D3 D2 D1 D0
CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 for CLK1 for CLK1 for CLK1 for CLK2 for CLK2 for CLK2 for CLK3 for CLK3 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 for CLK3 for CLK4 for CLK4 for CLK4 for CLK5 for CLK5 for CLK5 for CLK6 CLKSRC1 CLKSRC0 for CLK6 for CLK6 1 1 1 1 1 1
DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0)
Table 2. Programmable Crystal Input Oscillator Gain Settings Calculated CapLoad Value Crystal ESR Crystal Input Frequency 8-15 MHz 15-20 MHz 20-25 MHz 25-30 MHz Table 3. Bit Locations and Values Address 12H D7 0 D6 0 D5 0 D4 XDRV(1) D3 XDRV(0) D2 0 D1 0 D0 0 30 00 01 01 10 00H 20H 60 01 10 10 10 20H-30H 30 01 01 10 10 60 10 10 10 11 30H-40H 30 01 10 10 11 60 10 10 11 N/A
Table 4. Programmable External Reference Input Oscillator Drive Settings Reference Frequency Drive Setting 1-25 MHz 00 25-50 MHz 01 50-90 MHz 10 90-133 MHz 11
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CY26404
Input Load Capacitors Input load capacitors allow the user to set the load capacitance of the CY26404 to match the load capacitance from a crystal. The value of the load capacitors is determined by 8 bits in a programmable register [13H]. Total load capacitance is determined by the formula: CapLoad = (CL - CBRD - CCHIP)/0.09375 pF where: * CL = specified load capacitance of your crystal. * CBRD = the total board capacitance, due to external capacitors and board trace capacitance. In CyClocksRTTM, this value defaults to 2 pF. * CCHIP = 6 pF. * 0.09375 pF = the step resolution available due to the 8-bit register. In CyclocksRT the CY26404 is matched to the CY22150, and only the crystal capacitance (CL) is specified. CCHIP is set to 6 pF, and CBRD defaults to 2 pF. If your board capacitance is higher or lower than 2 pF, the formula above can be used to calculate a new CapLoad value and programmed into register 13H. In CyClocksRT, enter the crystal capacitance (CL). The value of CapLoad will be determined automatically and programmed into the CY26404. Through the SDAT and SCLK pins, the value can be adjusted up or down if your board capacitance is greater or less than 2 pF. For an external clock source, CapLoad defaults to 0. See Table 5 for CapLoad bit locations and values. The input load capacitors are placed on the CY26404 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply and temperature changes. PLL Frequency, Q Counter [42H(6..0)] The first counter is known as the Q counter. The Q counter divides REF by its calculated value. Q is a 7-bit divider with a maximum value of 127 and minimum value of 0. The primary value of Q is determined by 7 bits in register 42H (6..0), but 2 is added to this register value to achieve the total Q, or Qtotal. Qtotal is defined by the formula: Qtotal = Q + 2 The minimum value of Qtotal is 2. The maximum value of Qtotal is 129. Register 42H is defined in the table. Stable operation of the CY26404 cannot be guaranteed if REF/Qtotal falls below 250 kHz. Qtotal bit locations and values are defined in Table 6. PLL Frequency, P Counter [40H(1..0)], [41H(7..0)], [42H(7) The next counter definition is the P (product) counter. The P counter is multiplied with the (REF/Qtotal) value to achieve the VCO frequency. The product counter, defined as Ptotal, is Table 5. Input Load Capacitor Register Bit Settings Address 13H D7 D6 D5 D4 D3 D2 D1 D0 made up of two internal variables, PB and PO. The formula for calculating Ptotal is: Ptotal = (2(PB + 4) + PO) PB is a 10-bit variable, defined by registers 40H(1:0) and 41H(7:0). The 2 LSBs of register 40H are the two MSBs of variable PB. Bits 4..2 of register 40H are used to determine the charge pump settings (see Section 5). The 3 MSBs of register 40H are preset and reserved and cannot be changed. PO is a single-bit variable, defined in register 42H(7). This allows for odd numbers in Ptotal. The remaining 7 bits of 42H are used to define the Q counter, as shown in Table 6. The minimum value of Ptotal is 8. The maximum value of Ptotal is 2055. To achieve the minimum value of Ptotal, PB and PO should both be programmed to 0. To achieve the maximum value of Ptotal, PB should be programmed to 1023, and PO should be programmed to 1. Stable operation of the CY26404 cannot be guaranteed if the value of (Ptotal*(REF/Qtotal)) is above 400 MHz or below 100 MHz. Registers 40H, 41H and 42H are defined in Table 7. PLL Post Divider Options [OCH(7..0)], [47H(7..0)] The output of the VCO is routed through two independent muxes, then to two divider banks to determine the final clock output frequency. The mux determines if the clock signal feeding into the divider banks is the calculated VCO frequency or REF. There are two select muxes (DIV1SRC and DIV2SRC) and two divider banks (Divider Bank 1 and Divider Bank 2) used to determine this clock signal. The clock signal passing through DIV1SRC and DIV2SRC is referred to as DIV1CLK and DIV2CLK, respectively. The divider banks have 4 unique divider options available: /2, /3, /4, and /DIVxN. DIVxN is a variable that can be independently programmed (DIV1N and DIV2N) for each of the 2 divider banks. The minimum value of DIVxN is 4. The maximum value of DIVxN is 127. A value of DIVxN below 4 is not guaranteed to work properly. DIV1SRC is a single bit variable, controlled by register OCH. The remaining 7 bits of register OCH determine the value of post divider DIV1N. DIV2SRC is a single-bit variable, controlled by register 47H. The remaining 7 bits of register 47H determine the value of post divider DIV2N. Register OCH and 47H are defined in Table 8. Charge Pump Settings [40H(2..0)] The correct pump setting is important for PLL stability. Charge pump settings are controlled by bits (4..2) of register 40H, and are dependent on internal variable PB (see "PLL Frequency, P Counter[40H(1..0)], [41H(7..0)], [42H(7)]"). Table 9 summarizes the proper charge pump settings, based on Ptotal. See Table 10 for register 40H bit locations and values.
CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0)
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CY26404
Table 6. Q Counter Register Definition Address 42H 41H 42H D7 PO PB(7) PO D6 Q(6) PB(6) Q(6) D5 Q(5) PB(5) Q(5) D4 Q(4) PB(4) Q(4) D3 Q(3) PB(3) Q(3) D2 Q(2) PB(2) Q(2) D1 Q(1) PB(1) Q(1) D0 Q(0) PB(0) Q(0)
Table 7. P Counter Register Definition Address 40H 41H 42H D7 1 PB(7) PO D6 1 PB(6) Q(6) D5 0 PB(5) Q(5) D4 Pump(2) PB(4) Q(4) D3 Pump(1) PB(3) Q(3) D2 Pump(0) PB(2) Q(2) D1 PB(9) PB(1) Q(1) D0 PB(8) PB(0) Q(0)
Table 8. PLL Post Divider Options Address OCH 47H D7 DIV1SRC DIV2SRC D6 DIV1N(6) DIV2N(6) D5 DIV1N(5) DIV2N(5) D4 DIV1N(4) DIV2N(4) D3 DIV1N(3) DIV2N(3) D2 DIV1N(2) DIV2N(2) D1 DIV1N(1) DIV2N(1) D0 DIV1N(0) DIV2N(0)
Table 9. Charge Pump Settings Charge Pump Setting - Pump(2..0) 000 001 010 011 100 101, 110, 111 Table 10. Register 40H Change Pump Bit Settings Address 40H D7 1 D6 1 D5 0 D4 Pump(2) D3 Pump(1) D2 Pump(0) D1 PB(9) D0 PB(8) Calculated Ptotal 16 - 44 45 - 479 480 - 639 640 - 799 800 - 1023 Do not use - device will be unstable
Although using the above table will guarantee stability, it is recommended to use the Print Preview function in CyClocksRT to determine the correct charge pump settings for optimal jitter performance. PLL stability cannot be guaranteed for values below 16 and above 1023. If values above 1023 are needed, use CyClocksRT to determine the best charge pump setting. Clock Output Settings: CLKSRC - Clock Output Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)], [46H(7..6)] CLKOE - Clock Output Enable Control [09H(5..0)] Every clock output can be defined to come from one of seven unique frequency sources. The CLKSRC(2..0) crosspoint switch matrix defines which source is attached to each individual clock output. CLKSRC(2..0) is set in Registers 44H, 45H, and 46H. The remainder of register 46H(5:0) must be written with the values stated in the register table when writing register values 46H(7:6).
In addition, each clock output has individual CLKOE control, set by register 09H(5..0). When DIV1N is divisible by guaranteed to be rising CLKSRC(0,0,1). When DIV1N guaranteed to be rising CLKSRC(0,0,1). 4, then CLKSRC(0,1,0) is edge phase-aligned with is 6, then CLKSRC(0,1,1) is edge phase-aligned with
When DIV2N is divisible by 4, then CLKSRC(1,0,1) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). When DIV2N is divisible by 8, then CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). Each clock output has its own output enable, controlled by register 09H(5..0). To enable an output, set the corresponding CLKOE bit to 1. CLKOE settings are in Table 13. The output swing of CLK1 through CLK4 is set by VDDL. The output swing of CLK5 and CLK6 is set by VDD.
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CY26404
Test, Reserved, and Blank Registers Writing to any of the following registers will cause the part to exhibit abnormal behavior, as follows. [00H to 08H] - Reserved [0AH to 0BH] - Reserved Table 11. CLKSRC2 0 0 0 0 1 1 1 1 Table 12. Address 44H 45H 46H D7 CLKSRC2 for CLK1 CLKSRC0 for CLK3 CLKSRC1 for CLK6 D6 CLKSRC1 for CLK1 CLKSRC2 for CLK4 CLKSRC0 for CLK6 D5 CLKSRC0 for CLK1 CLKSRC1 for CLK4 1 D4 CLKSRC2 for CLK2 CLKSRC0 for CLK4 1 D3 CLKSRC1 for CLK2 CLKSRC2 for CLK5 1 D2 CLKSRC0 for CLK2 CLKSRC1 for CLK5 1 D1 CLKSRC2 for CLK3 CLKSRC0 for CLK5 1 D0 CLKSRC1 for CLK3 CLKSRC2 for CLK6 1 CLKSRC1 0 0 1 1 0 0 1 1 CLKSRC0 0 1 0 1 0 1 0 1 Reference input. DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are 4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8. DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4. DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6. DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are 4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8. DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4. DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8. Reserved - do not use. Definition and Notes [0DH to 11H] - Reserved [14H to 3FH] - Reserved [43H] - Reserved [48H to FFH] - Reserved.
Table 13. CLKOE Bit Setting Address 09H D7 0 D6 0 D5 CLK6 D4 CLK5 D3 CLK4 D2 CLK3 D1 CLK2 D0 CLK1
Programmable Interface Timing
The CY26404 utilizes a 2-wire serial-interface SDAT and SCLK that operates up to 400 kbits/second in Read or Write mode. The basic Write serial format is as follows. Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit data; ACK; 8-bit data in MA + 1 if desired; ACK; 8-bit data in MA+2; ACK; etc. until STOP bit.The basic serial format is illustrated in Figure 2. Data Valid Data is valid when the Clock is HIGH, and may only be transitioned when the clock is LOW, as illustrated in Figure 1. Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 3. Start Sequence - Start frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a Start signal is given, the next 8-bit data must be the device address (7 bits) and a R/W bit, followed by register address (8 bits) and register data (8 bits).
Stop Sequence - Stop frame is indicated by SDAT going HIGH when SCLK is HIGH. A Stop frame frees the bus for writing to another part on the same bus or writing to another random register address. Acknowledge Pulse During Write mode, the CY26404 will respond with an ACK pulse after every 8 bits. This is accomplished by pulling the SDAT line LOW during the N*9th clock cycle, as illustrated in Figure 4. (N = the number of 8-bit segments transmitted.) During Read mode, the ACK pulse after the data packet is sent is generated by the master.
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CY26404
Data valid Transition to next bit
SDAT
CLKHIGH VIH SCLK VIL
tDH
tSU
CLKLOW
Figure 1. Data Valid and Data Transition Periods 1-bit 1-bit 1-bit 1-bit 1-bit Slave Slave Slave Slave ACK ACK ACK ACK R/W = 0 7-bit 8-bit 8-bit 8-bit 8-bit Device Register Register Register Register Data Address Address Data Data (XXH) (XXH) (XXH+1) (XXH+2) 1-bit Slave ACK 1-bit Slave ACK 1-bit Slave ACK 1-bit Slave ACK
SDAT Write Multiple Contiguous Registers Start Signal
8-bit Register Data (FFH)
8-bit Register Data (00H) Stop Signal
SDAT Read Multiple Contiguous Registers Start Signal
1-bit 1-bit 1-bit 1-bit Slave Slave 1-bit Master ACK ACK R/W = 1 ACK R/W = 0 7-bit 8-bit 8-bit 8-bit Device Register 7-Bit Register Register Address Address Device Data Data (XXH) Address (XXH) (XXH+1)
1-bit Master ACK
1-bit Master ACK
1-bit Master ACK
1-bit Master ACK
8-bit Register Data (FFH)
8-bit Register Data (00H) Stop Signal
Figure 2. Data Frame Architecture
SDAT
START
Transition to next bit
SCLK STOP
Figure 3. Start and Stop Frame SDAT + START DA6 DA5DA0 R/W ACK RA7 + RA6RA1 RA0 ACK D7 D6 + D1 D0 ACK STOP
SCLK
+
+
+
Figure 4. Frame Format (Device Address, R/W, Register Address, Register Data
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CY26404
Parameter fSCLK CLKLOW CLKHIGH tSU tDH Description Frequency of SCLK Start mode time from SDA LOW to SCL LOW SCLK LOW period SCLK HIGH period Data transition to SCLK HIGH Data hold (SCLK LOW to data transition) Rise time of SCLK and SDAT Fall time of SCLK and SDAT Stop mode time from SCLK HIGH to SDAT HIGH Stop mode to Start mode 0.6 1.3 0.6 1.3 0.6 100 0 300 300 Min. Max. 400 Unit kHz s s s ns ns ns ns
s s
Absolute Maximum Conditions
Parameter VDD VDDL TJ Description Supply Voltage I/O Supply Voltage Junction Temperature Digital Inputs Digital Outputs referred to VDD Digital Outputs referred to VDDL Electro-Static Discharge AVSS - 0.3V VSS - 0.3V VSS - 0.3V 2 Min. -0.5 Max. 7.0 7.0 125 AVDD + 0.3V VDD + 0.3V VDDL +0.3V Unit V V C V V V kV
Recommended Operating Conditions
Parameter VDD VDDL TA CLOAD fREF Description Operating Voltage Operating Voltage Ambient Temperature Max. Load Capacitance Crystal or Driven Reference Frequency 20 Min. 3.135 2.375 0 Typ. 3.3 2.5 Max. 3.465 3.465 70 15 Unit V V C pF MHz
DC Electrical Specifications
Parameter[2] IOH IOL IOH IOL VIH VIL CIN IIZ IVDD IVDDL IVDDL Name Output High Current Output Low Current Output High Current Output Low Current Input High Voltage Input Low Voltage Input Capacitance Input Leakage Current Supply Current Supply Current Supply Current Description VOH = VDD - 0.5, VDD/VDDL = 3.3V VOL = 0.5, VDD/VDDL = 3.3V VOH = VDDL - 0.5, VDDL = 2.5V VOL = 0.5, VDDL = 2.5V CMOS levels, 70% of VDD CMOS levels, 30% of VDD OE Pin OE Pin AVDD/VDD Current VDDL Current (VDDL = 3.465V) VDDL Current (VDDL = 2.625V) 5 30 10 8 Min. 12 12 8 8 0.7 0.3 7 Typ. 24 24 16 16 Max. Unit mA mA mA mA VDD VDD pF A mA mA mA
Notes: 1. Float XOUT if XIN is externally driven. 2. Not 100% tested.
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CY26404
AC Electrical Specifications
Parameter[2] DC t3 t3 t4 t4 t5 t9 t10 Name Description Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDD/VDDL = 3.3V Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDDL = 2.5V Falling Edge Slew Rate Falling Edge Slew Rate Skew Clock Jitter PLL Lock Time Output Clock Fall Time, 80% - 20% of VDD/VDDL = 3.3V Output Clock Fall Time, 80% - 20% of VDDL = 2.5V Delay between related outputs at rising edge Peak to Peak period jitter Min. 40 0.8 0.6 0.8 0.6 Typ. 50 1.4 1.2 1.4 1.2 200 150[3] 3 Max. 60 Unit % V/ns V/ns V/ns V/ns ps ps ms
Note: 3. Applies only when device is in default mode. When programmed through the serial interface, the typical jitter is 250 ps.
Test and Measurement Set-up VDD 0.1 F OUTPUTS CLK out CLOAD
AVDD 0.1 F GND
t1 t2
CLK
50%
50%
Figure 5. Duty Cycle Definition; DC = t2/t1
t3 80% t4
CLK
20%
Figure 6. Rise and Fall Time Definitions
Ordering Information
Ordering Code CY26404ZC CY26404ZCT Package Name Z16 Z16 Package Type 16-Pin TSSOP 16-Pin TSSOP - Tape & Reel Operating Range Commercial Commercial Operating Voltage 3.3V 3.3V
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CY26404
Package Drawing and Dimensions
16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
51-85091-**
PacketClock and CyClocksRt are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY26404
Document History Page
Document Title: CY26404 PacketClockTM One-PLL General Purpose Clock Generator Document Number: 38-07470 REV. ** ECN NO. 118470 Issue Date 12/10/02 Orig. of Change CKN New Data Sheet Description of Change
Document #: 38-07470 Rev. **
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