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DAC7742
DAC 774 2
SBAS256 - DECEMBER 2002
16-Bit, Single Channel DIGITAL-TO-ANALOG CONVERTER With Internal Reference and Parallel Interface
FEATURES
q LOW POWER: 150mW Maximum q +10V INTERNAL REFERENCE q UNIPOLAR OR BIPOLAR OPERATION q SETTLING TIME: 5s to 0.003% FSR q 16-BIT MONOTINICITY, -40C TO +85C q 10V, 5V OR +10V CONFIGURABLE VOLTAGE OUTPUT q RESET TO MIN-SCALE OR MID-SCALE q DOUBLE-BUFFERED DATA INPUT q INPUT REGISTER DATA READBACK q SMALL LQFP-48 PACKAGE q SUPPORTS TRANSPARENT DATA INPUT OPERATION
DESCRIPTION
The DAC7742 is a 16-bit Digital-to-Analog Converter (DAC) that provides 16 bits of monotonic performance over the specified operating temperature range and offers a +10V, low-drift internal reference. Designed for automatic test equipment and industrial process control applications, the DAC7742 output swing can be configured in a 10V, 5V, or +10V range. The flexibility of the output configuration allows the DAC7742 to provide both unipolar and bipolar operation by pin strapping. The DAC7742 includes a high-speed output amplifier with a maximum settling time of 5s to 0.003% FSR for a 20V full-scale change and only consumes 100mW (typical) of power. The DAC7742 features a standard 16-bit parallel interface with double buffering to allow asynchronous updates of the analog output, and data read-back to support data integrity verification prior to an update. A user-programmable reset control allows the DAC output to reset to min-scale (FFFFH) or mid-scale (7FFFH) overriding the DAC register values. The DAC7742 is available in an LQFP-48 package and three performance grades specified to operate from -40C to +85C.
APPLICATIONS
q PROCESS CONTROL q ATE PIN ELECTRONICS q CLOSED-LOOP SERVO CONTROL q MOTOR CONTROL q DATA ACQUISITION SYSTEMS
VDD VSS VCC REFADJ REFOUT REFIN
VREF ROFFSET Buffer
REFEN CS R/W RST RSTSEL Control Logic
+10V Reference
RFB2
RFB1
SJ Data I/O 16 I/O Buffer Input Register DAC Register DAC VOUT
AGND
DGND
LDAC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2002, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
VCC to VSS ........................................................................... -0.3V to +32V VCC to AGND ...................................................................... -0.3V to +16V VSS to AGND ...................................................................... -16V to +0.3V AGND to DGND ................................................................. -0.3V to +0.3V REFIN to AGND ..................................................................... -9V to +11V VDD to DGND ................................................................. 0V to VCC - 1.4V Digital Input Voltage to DGND ................................. -0.3V to VDD + 0.3V Digital Output Voltage to DGND .............................. -0.3V to VDD + 0.3V Operating Temperature Range ........................................ -40C to +85C Storage Temperature Range ......................................... -65C to +150C Junction Temperature .................................................................... +150C NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
LINEARITY ERROR (LSB) 6 DIFFERENTIAL NONLINEARITY (LSB) 4 PACKAGE DESIGNATOR(1) PT SPECIFIED TEMPERATURE RANGE -40C to +85C ORDERING NUMBER DAC7742Y/250 DAC7742Y/2K DAC7742YB/250 DAC7742YB/2K DAC7742YC/250 DAC7742YC/2K PACKAGE MARKING DAC7742Y TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2000 Tape and Reel, 250 Tape and Reel, 2000 Tape and Reel, 250 Tape and Reel, 2000
PRODUCT DAC7742
PACKAGE-LEAD LQFP-48
"
DAC7742
"
4
"
2
"
LQFP-48
"
PT
"
-40C to +85C
"
DAC7742YB
"
DAC7742
"
3
"
1
"
LQFP-48
"
PT
"
-40C to +85C
"
DAC7742YC
"
"
"
"
"
"
"
NOTE: (1) For the most current specifications and package information refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = -15V, VDD = +5V, Internal reference enabled, unless otherwise noted. DAC7742Y PARAMETER ACCURACY Linearity Error (INL) TA = 25C Differential Linearity Error (DNL) Monotonicity Offset Error Offset Error Drift Gain Error Gain Error Drift PSRR (VCC or VSS) ANALOG OUTPUT(1) Voltage Output(2) 14 2 With Internal REF With External REF With Internal REF At Full-Scale +11.4/-4.75 +11.4/-11.4 +11.4/-6.4 5 0.1 0.4 0.25 200 0.25 0.1 CONDITIONS MIN TYP MAX 6 5 4 15 0.2 7 10.04 9.975 10 10.025 7 MIN DAC7742YB TYP MAX 4 3 2 16 MIN DAC7742YC TYP MAX 3 2 1 UNITS
15 50 0 to 10 10 5
10
LSB LSB LSB Bits % of FSR ppm/C % of FSR % of FSR ppm/C ppm/V V V V mA pF mA
Output Current Output Impedance Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration
AGND 9.96
0.1 200 15 Indefinite 10 400 15
REFERENCE Reference Output REFOUT Impedance REFOUT Voltage Drift REFOUT Voltage Adjustment(3) REFIN Input Range(4) REFIN Input Current REFADJ Input Range Absolute Max Value that can be applied is VCC REFADJ Input Impedance VREF Output Current VREF Impedance
25 4.75 0
VCC - 1.4 10 10 50

V ppm/C mV V nA V k mA
-2 1
+2

2
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ELECTRICAL CHARACTERISTICS (Cont.)
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = -15V, VDD = +5V, Internal reference enabled, unless otherwise noted. DAC7742Y PARAMETER DYNAMIC PERFORMANCE Settling Time to 0.003% CONDITIONS 20V Output Step RL = 5k, CL = 200pF, with external REFOUT to REFIN filter(5) at 10kHz |IH| < 10A |IL| < 10A 0.7 * VDD 0.3 * VDD See Table III IOH = -0.8mA IOL = 1.6mA 3.6 0.4 +4.75 +11.4 -15.75 -15.75 +5.0 +5.25 +15.75 -11.4 -4.75 6 150 +85 MIN TYP 3 MAX 4 MIN DAC7742YB TYP MAX MIN DAC7742YC TYP MAX UNITS s
Digital Feedthrough Output Noise Voltage DIGITAL INPUT VIH VIL Input Coding DIGITAL OUTPUT VOH VOL POWER SUPPLY VDD VCC VSS IDD ICC ISS Power TEMPERATURE RANGE Specified Performance Specifications same as DAC7742Y.
2 100

nV-s nV/Hz V V

V V V V V V A mA mA mW mW C
Bipolar Operation Unipolar Operation Unloaded Unloaded No Load, Ext. Reference No Load, Int. Reference
-4
100 4 -2.5 85 100

-40
NOTES: (1) With minimum VCC/VSS requirements, internal reference enabled. (2) Please refer to the "Theory of Operation" section for more information with respect to output voltage configurations. (3) See Figure 7 for gain and offset adjustment connection diagrams when using the internal reference. (4) The minimum value for REFIN must be equal to the greater of VSS +14V and +4.75V, where +4.75V is the minimum voltage allowed. (5) Reference low-pass filter values: 100k, 1.0F (See Figure 10).
DAC7742
SBAS256
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PIN CONFIGURATION
RSTSEL REFADJ REFOUT Top View REFIN NC LQFP DGND 37 36 NC 35 DB15 34 DB14 33 DB13 32 DB12 31 DB11 30 DB10 29 DB9 28 DB8 27 DB7 26 TEST 25 NC 13 NC 14 NC 15 NC 16 DB0 17 DB1 18 DB2 19 DB3 20 DB4 21 DB5 22 DB6 23 NC 24 NC DESCRIPTION Data Bit 8 Data Bit 9 Data Bit 10 Data Bit 11 Data Bit 12 Data Bit 13 Data Bit 14 Data Bit 15 (MSB) No Connection Digital Ground Digital Power Supply VOUT reset; active LOW, depending on the state of RSTSEL, the DAC register is either reset to midscale or min-scale. DAC register load control, active LOW. Data is loaded from the input register to the DAC register. Chip Select, Active LOW Enabled by CS, controls data read (HIGH) and write (LOW) from or to the input register. Reset Select; determines the action of RST. If HIGH, RST will reset the DAC register to midscale. If LOW, RST will reset the DAC register to min-scale. Enables internal +10V reference (REFOUT), active LOW. Internal Reference Output Internal Reference Trim. (Acts as a gain adjustment input when the internal reference is used.) Reference Input No Connection LDAC RST 39 R/W VDD 38 CS 41 REFEN
48 NC VSS VCC VREF ROFFSET AGND AGND RFB2 RFB1 1 2 3 4 5 6 7 8 9
47
46
45
44
43
42
40
DAC7742
SJ 10 VOUT 11 NC 12
PIN DESCRIPTIONS
PIN 1 2 3 4 NAME NC VSS VCC VREF DESCRIPTION No Connection Negative Analog Power Supply Positive Analog Power Supply Buffered Output from REFIN; can be used to drive external devices. Internally, this pin directly drives the DAC's circuitry. Offsetting Resistor Analog Ground (Must be tied to analog ground.) Analog Ground (Must be tied to analog ground.) Feedback Resistor 2, used to configure DAC output range. Feedback Resistor 1, used to configure DAC output range. Summing Junction of the Output Amplifier DAC Voltage Output No Connection No Connection No Connection No Connection Data Bit 0 (LSB) Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 No Connection No Connection No Connection Reserved, Connect to DGND Data Bit 7 47 48 REFIN NC 45 46 REFOUT REFADJ 44 REFEN 43 RSTSEL 41 42 CS R/W 40 LDAC PIN 28 29 30 31 32 33 34 35 36 37 38 39 NAME DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 NC DGND VDD RST
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
ROFFSET AGND AGND RFB2 RFB1 SJ VOUT NC NC NC NC DB0 DB1 DB2 DB3 DB4 DB5 DB6 NC NC NC TEST DB7
4
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TIMING DIAGRAMS
DATA WRITE CYCLE
tWCS CS tWS R/W tDS Data In DB15-DB0 Data Valid tDH tDS Data Valid tDH tWH tLS tLH
LDAC tLWD tS VOUT
READ CYCLE
RESET TIMING
tSS RSTSEL
CS tRDS R/W
tRCS tRDH
RST +FS
tSH tRSS tS Min-Scale
Data Out DB15-DB0
Data Valid tCSD
tDZ
VOUT
(RSTSEL = LOW) -FS +FS
VOUT
(RSTSEL = HIGH) -FS
Mid-Scale
TIMING CHARACTERISTICS
DAC7742Y PARAMETER READ tRCS tRDS tRDH tDZ tCSD WRITE tWS tWH tWCS tLWD tLS tLH tDS tDH RESET tRSS tSS tSH ANALOG tS DESCRIPTION CS LOW for Read R/W HIGH to CS LOW R/W HIGH After CS HIGH CS HIGH to Data Bus High Impedance CS LOW to Data Bus Valid R/W LOW to CS LOW R/W LOW After CS HIGH CS LOW for Write LDAC LOW for Write CS LOW to LDAC HIGH for Direct Update CS LOW After LDAC HIGH Data Valid to CS LOW Data Valid After CS HIGH RST LOW RSTSEL Valid Before RST LOW RSTSEL Valid After RST HIGH Voltage Output Settling Time MIN 90 10 10 10 70 10 10 25 20 30 0 0 20 30 0 10 5 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
70 100
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TYPICAL CHARACTERISTICS
TA = +25C (unless otherwise noted).
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 6 4 2 0 -2 -4 -6 6 4 2 0 -2 -4 -6
INL (LSB)
INL (LSB)
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
Bipolar Configuration: VOUT = -10V to +10V TA = 85C, Internal Reference Enabled
Bipolar Configuration: VOUT = -10V to +10V TA = 25C, Internal Reference Enabled
2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H Digital Input Code
2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H Digital Input Code
DNL (LSB)
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 6 4 2 0 -2 -4 -6
DNL (LSB)
OFFSET ERROR vs TEMPERATURE 5 4 3
INL (LSB)
Error (mV)
Bipolar Configuration: VOUT = -10V to +10V TA = -40C, Internal Reference Enabled
2 1 0 -1 -2 -3 -4 -5 -40 -15 10 35 60 85 VOUT = 0V to +10V VOUT = -10V to +10V
2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H Digital Input Code
DNL (LSB)
Temperature (C)
GAIN ERROR vs TEMPERATURE 0.15 Ext. Ref, Bipolar Mode: VOUT = -10V to +10V 0.10
Error (%)
4.4 4.3 4.2
VCC SUPPLY CURRENT vs DIGITAL INPUT CODE Bipolar Configuration: VOUT = -10V to +10V Internal Reference Enabled, TA = 25C
ICC (mA) 85
Int. Ref, Bipolar Mode: VOUT = -10V to +10V 0.05
4.1 4.0 3.9
0 Int. Ref, Unipolar Mode: VOUT = 0V to +10V -0.05 -40 -15 10 35 60 Temperature (C) Ext. Ref, Unipolar Mode: VOUT = 0V to +10V
3.8 3.7 FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H Digital Input Code
6
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SBAS256
TYPICAL CHARACTERISTICS (Cont.)
TA = +25C (unless otherwise noted).
VCC SUPPLY CURRENT vs DIGITAL INPUT CODE 3.4 3.3 3.2 Bipolar Configuration: VOUT = -10V to +10V External Reference, REFEN = 5V, TA = 25C
VSS SUPPLY CURRENT vs DIGITAL INPUT CODE -1.50
-1.75
ICC (mA)
3.1 3.0 2.9
ISS (mA)
-2.00
-2.25
-2.50
2.8 2.7 FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H Digital Input Code
Bipolar Configuration: VOUT = -10V to +10V TA = 25C -2.75 FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H Digital Input Code
SUPPLY CURRENT vs TEMPERATURE 6 5 4 3
800 1000
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE TA = 25C, Transition Shown for One Data Input (CS = 5V, R/W = 0)
ICC, ISS (mA)
1 0 -1 -2 -3 -4 -40
Load Current Excluded, VCC = +15V, VSS = -15V Bipolar VOUT Configuration: -10V to +10V
IDD (A)
2
ICC
600
400
ISS
200
0
-15
10
35
60
85
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Temperature (C)
VLOGIC (V)
HISTOGRAM OF VCC CURRENT CONSUMPTION 100 90 80 70 Frequency Frequency 60 50 40 30 20 10 0 3.000 3.500 4.000 ICC (mA) 4.500 5.000 Bipolar Output Configuration Internal Reference Enabled Code = AAAAH 100 90 80 70 60 50 40 30 20 10 0 -3.50
HISTOGRAM OF VSS CURRENT CONSUMPTION Bipolar Output Configuration Internal Reference Enabled Code = AAAAH
-3.00
-2.50 ISS (mA)
-2.00
-1.50
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25C (unless otherwise noted).
POWER-SUPPY REJECTION RATIO vs FREQUENCY (Measured at VOUT) 10 0 -10 -20 Bipolar Configuration: 10V VOUT Code 7FFFH -VSS, VCC = 15V + 1Vp-p VDD = 5V + 0.5Vp-p
POWER-SUPPY REJECTION RATIO vs FREQUENCY (Measured at VOUT) 10 0 -10 -20
PSRR (dB)
Bipolar Configuration: 10V VOUT, Code 0000H -VSS, VCC = 15V + 1Vp-p, VDD = 5V + 0.5Vp-p
PSRR (dB)
VSS VCC
-30 -40 -50 -60 -70 -80 0.1k 1k VDD 10k 100k 1M 10M VSS VCC
-30 -40 -50 -60 -70 -80 0.01k 0.1k
VDD
1k
Frequency (Hz)
10k 100k Frequency (Hz)
1M
10M
INTERNAL REFERENCE START-UP
10.015 VCC (5V/div)
INTERNAL REFERENCE OUTPUT vs TEMPERATURE
15V 0V
REFOUT (V)
10.010 10.005 10.000 9.995 9.990
REFOUT (2V/div)
10V
0V Time (2ms/div)
9.985 -40 -15 10 35 60 85
Temperature (C)
OUTPUT VOLTAGE vs RLOAD 12 Source 8 4
VOUT (V)
REFOUT VOLTAGE vs LOAD 11.0 Loaded to VCC 10.5
REFOUT (V)
VCC = +15V
10.0
0 -4 Sink -8 -12 0.0 0.1 1.0 RLOAD (k) 10.0 100.0
9.5
9.0 Loaded to AGND 8.5 1 10 100 1k REFOUT LOAD (k)
8
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25C (unless otherwise noted).
POWER-SUPPY REJECTION RATIO vs FREQUENCY (Measured at REFOUT) 10 0 -10 -20 Internal Reference Enabled -VSS, VCC = 15V + 1Vp-p, VDD = 5V + 0.5Vp-p VCC
OUTPUT NOISE vs FREQUENCY 900 800 Unipolar Configuration, Internal Reference Enabled
Output Noise (nV/Hz)
700 600 500 400 300 200 100 0 0.01k 0.1k 1k 10k 100k Frequency (Hz) 1M 10M Code FFFFH Code 0000H
PSRR (dB)
-30 -40 -50 -60 -70 -80 1 10 100 1k 10k Frequency (Hz) 100k 1M 10M VSS VDD
OUTPUT NOISE vs FREQUENCY 800 700 Bipolar Configuration: 10V, Internal Reference Enabled
BROADBAND NOISE
Output Noise (nV/rtHz)
500 400 Code FFFFH 300 200 100 0 0.01k Code 7FFFH Code 0000H
VOUT (V, 50V/div)
600
Internal Reference Enabled Filtered with 1.6Hz Low-Pass Code 0000H, Bipolar 10V Configuration 10kHz Measurement BW Time (100s/div)
0.1k
1k
10k 100k Frequency (Hz)
1M
10M
UNIPOLAR FULL-SCALE SETTLING TIME
BIPOLAR FULL-SCALE SETTLING TIME
Small-Signal Error (150V/div)
Small-Signal Error (300V/div)
Large-Signal Output (5V/div)
Large-Signal Output (5V/div)
Unipolar Configurtaion: VOUT = 0V to +10V + Full-Scale to Zero-Scale 5k, 200pF Load Time (2s/div)
Bipolar Configurtaion: VOUT = -10V to +10V +Full-Scale to -Full-Scale 5k, 200pF Load Time (2s/div)
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25C (unless otherwise noted).
UNIPOLAR FULL-SCALE SETTLING TIME
BIPOLAR FULL-SCALE SETTLING TIME
Large-Signal Output (5V/div) Small-Signal Error (150V/div)
Large-Signal Output (5V/div)
Small-Signal Error (300V/div)
Unipolar Configuration: VOUT = 0V to +10V Zero-Scale to +Full-Scale 5k, 200pF Load Time (2s/div)
Bipolar Configuration: VOUT = -10 to +10V -Full-Scale to +Full-Scale 5k, 200pF Load Time (2s/div)
MID-SCALE GLITCH Code 7FFFH to 8000H Bipolar Configuration: 10V VOUT
VOUT (V, 200mV/div) VOUT (V, 200mV/div)
MID-SCALE GLITCH Code 8000H to 7FFFH Bipolar Configuration: 10V VOUT
Time (1s/div)
Time (1s/div)
DIGITAL FEEDTHROUGH All Data Bits Toggling (5V/div)
VOUT = 7FFFH (100mV/div)
CS = 5V Time (200ns/div)
10
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THEORY OF OPERATION
The DAC7742 is a voltage output, 16-bit DAC with a +10V builtin internal reference. The architecture is an R-2R ladder configuration with the three MSBs segmented, followed by an operational amplifier that serves as a buffer, as shown in Figure 1. The output buffer is designed to allow user-configurable output adjustments giving the DAC7742 output voltage ranges of 0V to +10V, -5V to +5V, or -10V to +10V. Please refer to Figures 2, 3, and 4 for pin configuration information.
The digital input is a parallel word made up of the 16-bit DAC code and is loaded into the DAC register using the LDAC input pin. The converter can be powered from 12V to 15V dual analog supplies and a +5V logic supply. The device offers a reset function, which immediately sets the DAC output voltage and DAC register to min-scale (code FFFFH) or mid-scale (code 7FFFH). The data I/O and reset functions are discussed in more detail in the following sections.
REFADJ
REFOUT
REFIN
VREF R/4
ROFFSET RFB2
Buffer +10V Internal Reference R R/2 R/2
RFB1 R/4 SJ
VOUT 2R 2R 2R 2R 2R 2R 2R 2R 2R R/4
VREF AGND
FIGURE 1. DAC7742 Architecture.
Data Bus VDD
NC 36
DB15 35
DB14 34
DB13 33
DB12 32
DB11 31
DB10 30
DB9 29
DB8 28
DB7 27
TEST 26
37
DGND VDD RST LDAC CS R/W RSTSEL REFEN REFOUT REFADJ REFIN
NC NC DB6 DB5 DB4 DB3
38
39
40
41
Control Bus
42
19
20
21
22
23
24
0.1F
1F
NC 25
Data Bus
43
DB2 DB1 DB0 NC NC
44
45
46
47
ROFFSET
48
AGND
AGND
RFB2
RFB1
NC
NC
VOUT
VREF
VCC
VSS
NC
10
11
VSS
12
1
2
3
4
5
6
7
8
9
NC
SJ
0.1F VCC
1F
0.1F
1F
FIGURE 2. Basic Operation: VOUT = 0V to +10V.
DAC7742
SBAS256
13
(0V to +10V)
14
15
16
17
18
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Data Bus VDD
NC 36
DB15 35
DB14 34
DB13 33
DB12 32
DB11 31
DB10 30
DB9 29
DB8 28
DB7 27
TEST 26
37
DGND VDD RST LDAC CS R/W RSTSEL REFEN REFOUT REFADJ REFIN
NC NC DB6 DB5 DB4 DB3
38
39
40
41
Control Bus
42
19
20
21
22
23
24
0.1F
1F
NC 25
Data Bus
43
DB2 DB1 DB0 NC NC
44
45
46
47
ROFFSET
48
AGND
AGND
RFB2
RFB1
NC
VREF VCC VSS NC
NC
VOUT NC SJ
10
11
VSS
12
1
2
3
4
5
6
7
8
9
0.1F VCC
1F
0.1F
1F
FIGURE 3. Basic Operation: VOUT = -5V to +5V.
Data Bus VDD
NC 36
DB15 35
DB14 34
DB13 33
DB12 32
DB11 31
DB10 30
DB9 29
DB8 28
DB7 27
TEST 26
37
DGND VDD RST LDAC CS R/W RSTSEL REFEN REFOUT REFADJ REFIN
NC NC DB6 DB5 DB4 DB3
38
39
40
41
Control Bus
42
19
20
21
22
23
24
0.1F
1F
NC 25
13
14
15
16
17
18
DAC7742
(-5V to +5V)
Data Bus
43
DB2 DB1 DB0 NC NC
44
45
46
47
ROFFSET
48
AGND
AGND
RFB2
RFB1
NC
VREF VCC VSS NC
NC
VOUT NC SJ
10
11
VSS
12
1
2
3
4
5
6
7
8
9
0.1F VCC
1F
0.1F
1F
FIGURE 4. Basic Operation: VOUT = -10V to +10V.
13
14
15
16
17
18
DAC7742
(-10V to +10V)
12
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ANALOG OUTPUTS
The output amplifier can swing to within 1.4V of the supply rails, specified over the -40C to +85C temperature range. This allows for a 10V DAC voltage output operation from 12V supplies with a typical 5% tolerance. When the DAC7742 is configured for a unipolar, 0V to 10V output, a negative voltage supply is required. This is due to internal biasing of the output stage. Please refer to the "Electrical Characteristics" table for more information. The minimum and maximum voltage output values are dependent upon the output configuration implemented and reference voltage applied to the DAC7742. Please note that VSS (the negative power supply) must be in the range of -4.75V to -15.75V for unipolar operation. The voltage on VSS sets several bias points within the converter and is required in all modes of operation. If VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not ensured. Supply sequence is important in establishing correct startup of the DAC. The digital supply (VDD) needs to establish correct bias conditions before the analog supplies (VCC, VSS) are brought up. If the digital supply cannot be brought up first, it must come up before either analog supply (VCC or VSS), with the preferred sequence of: VSS (device substrate), VDD, and then VCC.
at the VREF pin. In this configuration, VREF is used to setup the DAC7742 output amplifier into one of three voltage output modes as discussed earlier. VREF can also be used to drive other system components requiring an external reference. The internal reference of the DAC7742 can be disabled when use of an external reference is desired. When using an external reference, the reference input, REFIN, can be any voltage between 4.75V (or VSS + 14V, whichever is greater) and VCC - 1.4V.
DIGITAL INTERFACE
Table III shows the data format for the DAC7742 and Table II illustrates the basic control logic of the device. The interface consists of a chip select input (CS), read/write control input (R/W), data inputs (DB0-DB15), and a load DAC input (LDAC). An asynchronous reset input (RST) which is active LOW, is provided to simplify start-up conditions, periodic resets, or emergency resets to a known state, depending on the status of the reset select (RSTSEL) signal. The DAC code is provided via a 16-bit parallel interface, as shown in Table II. The input word makes up the DAC code to be loaded into the data input register of the device. The data is latched into the input register on rising CS and is loaded into the DAC register upon reception of a LOW level on the LDAC input. This action updates the analog output, VOUT, to the desired value. LDAC inputs of multiple DAC7742s can be connected when a synchronized update of numerous DAC outputs is desired. Please refer to the timing section for more detailed data I/O information.
ANALOG OUTPUT DIGITAL INPUT 0xFFFF 0xFFFE : 0x7FFF 0x7FFE : 0x0000 Unipolar Configuration Zero (0V) Zero + 1LSB : 1/2 Full-Scale 1/2 Full-Scale + 1LSB : Full-Scale (VREF - 1LSB) Bipolar Configuration -Full-Scale (-VREF or -VREF/2) -Full-Scale + 1LSB : Bipolar Zero Bipolar Zero + 1LSB : +Full-Scale (+VREF - 1LSB or +VREF/2 - 1LSB)
REFERENCE INPUTS
The DAC7742 provides a built-in +10V voltage reference and on-chip buffer to allow external component reference drive. To use the internal reference, REFEN must be LOW, enabling the reference circuitry of the DAC7742 (as shown in Table I) and the REFOUT pin must be connected to REFIN. This is the input to the on-chip reference buffer. The buffer's output is provided
REFEN 1 0 ACTION Internal Reference disabled; REFOUT = High Impedance Internal Reference enabled; REFOUT = +10V
Complementary Straight Binary Complementary Offset Binary
TABLE I. REFEN Action.
CONTROL STATUS R/W L X L H X X X CS L H L L H X X RST H H H H H L L RSTSEL X X X X X L H LDAC H L L H, L H X X Input Register Write Hold Transparent Read Hold Reset to Min-Scale Reset to Mid-Scale
TABLE III. DAC7742 Data Format.
COMMAND DAC Register Hold Write Write Hold Hold Reset to Min-Scale Reset to Mid-Scale Mode Write Data to Input Register Update DAC Register with Data from Input Register Write DAC Register Directly from Data Bus Read Data in Input Register No Change Reset to Input and DAC Register (FFFFH) Min-Scale Reset to Input and DAC Register (7FFFH) Mid-Scale
TABLE II. DAC7742 Logic Truth Table.
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DAC RESET
The RST and RSTSEL inputs control the reset of the analog output. The reset command is level triggered by a LOW signal on RST. Once RST is LOW, the DAC output will begin settling to the mid-scale or min-scale code depending on the state of the RSTSEL input. A HIGH value on RSTSEL will cause VOUT to reset to the mid-scale code (7FFFH) and a LOW value will reset VOUT to min-scale (FFFFH). A change in the state of the RSTSEL input while RST is LOW will cause a corresponding change in the reset command selected internally and consequently change the output value of VOUT of the DAC. Note that a valid reset signal also resets the input register of the DAC to the value specified by the state of RSTSEL.
(+VREF) + Full-Scale 1LSB Full Scale Range Analog Output Gain Adjust Rotates the Line
Input = FFFFH
Input = 0000 H
Zero Scale (AGND)
Digital Input
Offset Adjust Translates the Line
GAIN AND OFFSET CALIBRATION
The architecture of the DAC7742 is designed in such a way as to allow for easily configurable offset and gain calibration using a minimum of external components. The DAC7742 has built-in feedback resistors and output amplifier summing points brought out of the package in order to make the absolute calibration possible. Figures 5 and 6 illustrate the relationship of offset and gain adjustments for the DAC7742 in a unipolar configuration and in a bipolar configuration, respectively. When calibrating the DAC's output, offset should be adjusted first to avoid 1st-order interaction of adjustments. In unipolar mode, the DAC7742's offset is adjusted from code FFFFH and for either bipolar mode, offset adjustments are made at code 7FFFH. Gain adjustment can then be made at code 0000H for each configuration, where the output of the DAC should be at +10V for the 0V to +10V - 1LSB or 10V output range and +5V - 1LSB for the 5V output range. Figure 7 shows the generalized external offset and gain adjustment circuitry using potentiometers.
FIGURE 5. Relationship of Offset and Gain Adjustments for VOUT = 0V to +10V Output Configuration.
(+VREF or +VREF/2) + FullScale 1LSB
Full-Scale Range
Input = FFFFH
Analog Output
Gain Adjust Rotates the Line
Input = 0000 H Input = 7FFFH - Full-Scale (-VREF OR -VREF/2) Digital Input
Offset Adjust Translates the Line
FIGURE 6. Relationship of Offset and Gain Adjustments for VOUT = -10V to +10V Output Configuration. (Same Theory Applies for VOUT = -5V to +5V.)
15 16 Optional Gain Adjust 17 18 RPOT1
REFOUT REFADJ
ROFFSET
REFIN
VCC VSS NC
AGND
AGND
RFB2
RFB1
10
SJ
NC
ISJ
R1 (Other Connections Omitted for Clarity) RS RPOT2 + VOADJ - Optional Offset Adjust
FIGURE 7. Generalized External Calibration Circuitry for Gain and Symmetrical Offset Adjustment.
11
1
2
3
4
5
6
7
8
9
VOUT
VREF
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OFFSET ADJUSTMENT
Offset adjustment is accomplished by introducing a small current into the summing junction (SJ) of the DAC7742. The voltage at SJ, or VSJ, is dependent on the output configuration of the DAC7742. Table IV shows the required pin strapping for a given configuration and the nominal values of VSJ for each output range.
REFERENCE OUTPUT PIN STRAPPING CONFIGURATION CONFIGURATION ROFFSET RFB1 RFB2 Internal Reference External Reference 0V to +10V -10V to +10V -5V to +5V VSJ(1)
REFADJ can be driven by a low impedance voltage source such as a unipolar, 0V to +10V DAC or a potentiometer (less than 100k), see Figure 7. Since the input impedance of REFADJ is typically 50k, the smaller the resistance of the potentiometer, the more linear the adjustment will be. A 10k potentiometer is suggested if linearity of the reference adjustment is of concern.
50 Offset Adjustment at VOUT (mV)
OFFSET ADJUST RANGE typ -10V to +10V VOUT Configuration
+5V to VREF to VOUT to VOUT NC NC to VOUT +3.333V to AGND to VOUT to VOUT +2.5V VREF/2 VREF/3 VREF/4
25 typ 0 min (75% of typ) -25
min (75% of typ)
to VREF to VOUT to VOUT 0V to VREF -VREF to VREF NC NC to VOUT -VREF/2 to VREF/2 to AGND to VOUT to VOUT
NOTE: (1) Voltage measured at VSJ for a given configuration.
TABLE IV. Nominal VSJ vs VOUT and Reference Configuration. The current level required to adjust the DAC7742's offset can be created by using a potentiometer divider, see Figure 7. Another alternative is to use a unipolar DAC in order to apply a voltage, VOADJ, to the resistor RS. A 1.2A current range applied to SJ will ensure offset adjustment coverage of the 0.1% maximum offset specification of the DAC7742. When in a unipolar configuration (VSJ = 5V), only a single resistor, RS, is needed for symmetrical offset adjustment with a 0V to 10V VOADJ range. When in one of the two bipolar configurations, VSJ is either +3.333v (10V range) or +2.5V (5V range), and circuit values chosen to match those given in Table V will provide symmetrical offset adjust. Please refer to Figure 7 for component configuration.
0V to 10V and -5V to +5V VOUT Configuration
-50 -2 -1 0 ISJ (A) 1 2
FIGURE 8. Offset Adjustment Transfer Characteristic. When the DAC7742's internal reference is not used, gain adjustments can be made via trimming the external reference applied to the DAC at REFIN. This can be accomplished through using a potentiometer, unipolar DAC, or other means of precision voltage adjustment to control the voltage presented to the DAC7742 by the external reference. Figure 9 and Table VI summarize the range of adjustment of the internal reference via REFADJ.
OUTPUT RPOT2 CONFIGURATION 0V to +10V -10V to +10V -5V to +5V 10k 10k 10k
R1
RS
ISJ RANGE 2A 2.2A 1.7A
NOMINAL OFFSET ADJUSTMENT 25mV 55mV 21mV
0 5k 10k
2.5M 1.5M 1.5M
40 30
REFOUT ADJUST RANGE Typical REFOUT Adjustment Range
TABLE V. Recommended External Component Values for Symmetrical Offset Adjustment (VREF = 10V). Figure 8 illustrates the typical and minimum offset adjustment ranges provided by forcing a current at SJ for a given output voltage configuration.
REFOUT Adjustment (mV)
20 10 0 -10 -20 -30 Minimum REFOUT Adjustment Range
GAIN ADJUSTMENT
When using the internal reference of the DAC7742, gain adjustment is performed by adjusting the device's internal reference voltage via the reference adjust pin, REFADJ. The effect of a reference voltage change on the gain of the DAC output can be seen in the generic equation (for unipolar configuration):
-40 0 2 4 6 8 10 REFADJ (V)
FIGURE 9. Internal Reference Adjustment Transfer Characteristic.
VOLTAGE AT REFADJ REFADJ = 0V REFADJ = 5V or NC(1) REFADJ = 10V NOTE: "NC" is "Not Connected". REFOUT VOLTAGE 10V + 25mV (min) 10V 10V - 25mV (max)
(65535 - N) VOUT = VREFIN * 65536
Where N is represented in decimal format and ranges from 0 to 65535.
TABLE VI. Minimum Internal Reference Adjustment Range.
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NOISE PERFORMANCE
Increased noise performance of the DAC output can be achieved by filtering the voltage reference input to the DAC7742. Figure 10 shows a typical internal reference filter schematic. A low-pass filter applied between the REFOUT and REFIN pins can increase noise immunity at the DAC and output amplifier. The REFOUT pin can source a maximum of 50A so care should be taken in order to avoid overloading the internal reference output.
LAYOUT
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC7742 offers separate digital and analog supplies, as it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more important it will become to separate the analog and digital ground and supply planes at the device. Since the DAC7742 has both analog and digital ground pins, return currents can be better controlled and have less effect on the DAC output error. Ideally, AGND would be connected directly to an analog ground plane and DGND to the digital ground plane. The analog ground plane would be separate from the ground connection for the digital components until they were connected at the power entry point of the system. The voltages applied to VCC and VSS should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. In addition, a 1F to 10F bypass capacitor in parallel with a 0.1F bypass capacitor is strongly recommended for each supply input. In some situations, additional bypassing may be required, such as a 100F electrolytic capacitor or even a "Pi" filter made up of inductors and capacitors-all designed to essentially low-pass filter the analog supplies, removing any high frequency noise components.
43 100k 1F 44 45 46 47 (Other Connections Omitted for Clarity) 48
RSTSEL REFEN REFOUT REFADJ REFIN
VCC 3 VSS 2 NC 1
NC
FIGURE 10. Internal Reference Filter.
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PACKAGE DRAWING
MTQF003A - OCTOBER 1994 - REVISED DECEMBER 1996
PT (S-PQFP-G48)
0,27 0,17 36 25
PLASTIC QUAD FLATPACK
0,50
0,08 M
37
24
48
13 0,13 NOM 1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,25 1,45 1,35 0,05 MIN 05- 75 Gage Plane 12
Seating Plane 1,60 MAX 0,10
0,75 0,45
4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 This may also be a thermally enhanced plastic package with leads conected to the die pads.
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