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DAC8531
SBAS192B - MARCH 2001 - REVISED JUNE 2003
Low-Power, Rail-to-Rail Output, 16-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER
FEATURES
q microPower OPERATION: 250A at 5V q POWER-ON RESET TO ZERO q POWER SUPPLY: +2.7V to +5.5V q ENSURED MONOTONIC BY DESIGN q SETTLING TIME: 10s to 0.003 FSR q LOW-POWER SERIAL INTERFACE WITH SCHMITT-TRIGGERED INPUTS q ON-CHIP OUTPUT BUFFER AMPLIFIER, RAIL-TO-RAIL OPERATION q SYNC INTERRUPT FACILITY q PACKAGES: MSOP-8 and 3x3 SON-8 (same size as QFN)
DESCRIPTION
The DAC8531 is a low-power, single, 16-bit buffered voltage output Digital-to-Analog Converter (DAC). Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The DAC8531 uses a versatile three-wire serial interface that operates at clock rates up to 30MHz and is compatible with standard SPITM, QSPITM, MicrowireTM, and Digital Signal Processor (DSP) interfaces. The DAC8531 requires an external reference voltage to set the output range of the DAC. The DAC8531 incorporates a power-on reset circuit that ensures that the DAC output powers up at 0V and remains there until a valid write takes place to the device. The DAC8531 contains a power-down feature, accessed over the serial interface, that reduces the current consumption of the device to 200nA at 5V. The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is 2mW at 5V reducing to 1W in power-down mode. The DAC8531 is available in both MSOP-8 and 3x3 SON-8 (same size as QFN) packages.
APPLICATIONS
q q q q q q PROCESS CONTROL DATA ACQUISITION SYSTEMS CLOSED-LOOP SERVO-CONTROL PC PERIPHERALS PORTABLE INSTRUMENTATION PROGRAMMABLE ATTENUATION
VDD
VFB
VREF
Ref (+) 16-Bit DAC
VOUT
16
DAC Register
16 SYNC SCLK DIN Power-Down Control Logic Resistor Network
Shift Register
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2001-2003, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS(1)
VDD to GND ........................................................................... -0.3V to +6V Digital Input Voltage to GND ................................. -0.3V to +VDD + 0.3V VOUT to GND .......................................................... -0.3V to +VDD + 0.3V Operating Temperature Range ...................................... -40C to +105C Storage Temperature Range ......................................... -65C to +150C Junction Temperature Range (TJ max) ........................................ +150C Power Dissipation ........................................................ (TJ max -- TA)/JA JA Thermal Impedance ......................................................... 206C/W JC Thermal Impedance .......................................................... 44C/W Lead Temperature, Soldering: Vapor Phase (60s) ............................................................... +215C Infrared (15s) ........................................................................ +220C NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
MINIMUM RELATIVE ACCURACY (LSB) 64 DIFFERENTIAL NONLINEARITY (LSB) 1 SPECIFICATION TEMPERATURE RANGE -40C to +105C
PRODUCT DAC8531E
PACKAGE-LEAD MSOP-8
PACKAGE DESIGNATOR(1) DGK
PACKAGE MARKING D31
ORDERING NUMBER DAC8531E/250 DAC8531E/2K5 DAC8531IDRBT DAC8531IDRBR
TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500
"
DAC8531I DAC8531I
"
64
"
1
"
SON-8
"
DRB
"
-40C to +105C
"
D31
"
"
"
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +5.5V. -40C to +105C, unless otherwise specified. DAC8531E PARAMETER STATIC PERFORMANCE (1) Resolution Relative Accuracy Differential Nonlinearity Zero Code Error Full-Scale Error Gain Error Zero Code Error Drift Gain Temperature Coefficient OUTPUT CHARACTERISTICS (2) Output Voltage Range Output Voltage Settling Time CONDITIONS MIN TYP MAX UNITS
16 Ensured Monotonic by Design All Zeroes Loaded to DAC Register All Ones Loaded to DAC Register 0.098 1 +20 -1.25 1.25
+5 -0.15 20 5 0
Bits % of FSR LSB mV % of FSR % of FSR V/C ppm of FSR/C V s s V/s pF pF nV-s nV-s mA mA s s
To 0.003% FSR 0200H to FD00H RL = 2k; 0pF < CL < 200pF RL = 2k; CL = 500pF RL = RL = 2k 1LSB Change Around Major Carry
VREF 8 12 1 470 1000 20 0.5 1 50 20 2.5 5 35 20 45 30 VDD 10
Slew Rate Capacitive Load Stability Code Change Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current Power-Up Time
VDD = +5V VDD = +3V Coming Out of Power-Down Mode VDD = +5V Coming Out of Power-Down Mode VDD = +3V VREF = VDD = +5V VREF = VDD = +3.6V 0
REFERENCE INPUT Reference Current Reference Input Range Reference Input Impedance
150
A A V k
NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested.
2
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ELECTRICAL CHARACTERISTICS (Cont.)
VDD = +2.7V to +5.5V. -40C to +105C, unless otherwise specified. DAC8531E PARAMETER LOGIC INPUTS (2) Input Current VINL, Input LOW Voltage VINL, Input LOW Voltage VINH, Input HIGH Voltage VINH, Input HIGH Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (normal mode) VDD = +3.6V to +5.5V VDD = +2.7V to +3.6V IDD (all power-down modes) VDD = +3.6V to +5.5V VDD = +2.7V to +3.6V POWER EFFICIENCY IOUT/IDD TEMPERATURE RANGE Specified Performance CONDITIONS MIN TYP MAX 1 0.8 0.6 2.4 2.1 3 2.7 DAC Active and Excluding Load Current VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND ILOAD = 2mA, VDD = +5V -40 250 240 0.2 0.05 89 +105 5.5 400 390 1 1 UNITS A V V V V pF V A A A A % C
VDD VDD VDD VDD
= = = =
+5V +3V +5V +3V
PIN CONFIGURATIONS
Top View MSOP-8, SON-8
PIN DESCRIPTION
PIN 1 2 3 4 NAME VDD VREF VFB VOUT SYNC DESCRIPTION Power-Supply Input, +2.7V to +5.5V. Reference Voltage Input Feedback connection for the output amplifier. Analog output voltage from DAC. The output amplifier has rail-to-rail operation. Level-triggered control input (active LOW). This is the frame sychronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken HIGH before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8531. Serial Clock Input. Data can be transferred at rates up to 30MHz. Serial Data Input. Data is clocked into the 24-bit input shift register on the falling edge of the serial clock input. Ground reference point for all circuitry on the part.
VDD VREF VFB VOUT
1 2 DAC8531 3 4
8 7 6 5
GND DIN SCLK SYNC
5
6 7
SCLK DIN
8
GND
DAC8531
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TIMING CHARACTERISTICS(1, 2)
VDD = +2.7V to +5.5V; all specifications -40C to +105C unless otherwise noted. DAC8531E PARAMETER t1
(3)
DESCRIPTION SCLK Cycle Time
CONDITIONS
MIN
TYP
MAX
UNITS
VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V t2 SCLK HIGH Time VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V t3 SCLK LOW Time VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V t4 SYNC to SCLK Rising Edge Setup Time VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V t5 Data Setup Time VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V t6 Data Hold Time VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V t7 SCLK Falling Edge to SYNC Rising Edge VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V t8 Minimum SYNC HIGH Time VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V
50 33 13 13 22.5 13
ns ns ns ns ns ns
0 0 5 5 4.5 4.5
ns ns ns ns ns ns
0 0 50 33
ns ns ns ns
NOTES: (1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation timing diagram, below. (3) Maximum SCLK frequency is 30MHz at VDD = +3.6V to +5.5V and 20MHz at VDD = +2.7V to +3.6V.
SERIAL WRITE OPERATION
t1 SCLK t8 t4 SYNC t6 t5 DIN DB23 DB0 t3 t2 t7
4
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SBAS192B
TYPICAL CHARACTERISTICS: VDD = 5V
At TA = +25C, VDD = 5V, unless otherwise noted. NOTE: All references to IDD include IREF current.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (-40C) 64 48 32 16 0 -16 -32 -48 -64 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 64 48 32 16 0 -16 -32 -48 -64
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25C)
LE (LSB)
LE (LSB) DLE (LSB)
2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
DLE (LSB)
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105C) 64 48 32 16 0 -16 -32 -48 -64 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
20 15 10
Error (mV)
ZERO-SCALE ERROR vs TEMPERATURE
LE (LSB)
5 0 -5 -10 -15 -20 -40
DLE (LSB)
0
40 Temperature (C)
80
120
FULL-SCALE ERROR vs TEMPERATURE 20 15 10
Error (mV)
IDD HISTOGRAM 2000
1500
Frequency
0 40 Temperature (C) 80 120
5 0 -5 -10 -15 -20 -40
1000
500
0 100 130 160 190 220 250 280 310 340 370 400 IDD (A)
DAC8531
SBAS192B
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TYPICAL CHARACTERISTICS: VDD = 5V (Cont.)
At TA = +25C, VDD = 5V, unless otherwise noted. NOTE: All references to IDD include IREF current.
SOURCE AND SINK CURRENT CAPABILITY 5 DAC Loaded with FFFFH 400 500
SUPPLY CURRENT vs DIGITAL INPUT CODE
4
VOUT (V)
2
IDD (A)
3
300
200
1 DAC Loaded with 0000H 0 0 5 ISOURCE/SINK (mA) 10 15
100
0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
POWER-SUPPLY CURRENT vs TEMPERATURE 350 300
Quiescent Current (A)
SUPPLY CURRENT vs SUPPLY VOLTAGE 350 VREF tied to VDD. 300 250
IDD (A)
250 200 150 100 50 0 -40 0 40 Temperature (C) 80 120
200 150 100 50 0 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2 5.7
POWER-DOWN CURRENT vs SUPPLY VOLTAGE 100 90 80 70
600 500 700
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
IDD (nA)
50 40 30 20 10 0 2.7 3.2 3.7 4.2 -40C
+105C
IDD (A)
+25C 5.2 5.7
60
400 300 200 100
4.7
0
1
2 VLOGIC (V)
3
4
5
VDD (V)
6
DAC8531
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SBAS192B
TYPICAL CHARACTERISTICS: VDD = 5V (Cont.)
At TA = +25C, VDD = 5V, unless otherwise noted.
FULL-SCALE SETTLING TIME Scope Trigger (5.0V/div) Large-Signal Output (1.0V/div)
FULL-SCALE SETTLING TIME Scope Trigger (5.0V/div)
Small-Signal Error (1mV/div)
Small-Signal Error (1mV/div) Full-Scale Code Change FFFFH to 0000H Output Loaded with 2k and 200pF to GND Large-Signal Output (1.0V/div) Time (2s/div)
Full-Scale Code Change 0000H to FFFFH Output Loaded with 2k and 200pF to GND Time (2s/div)
HALF-SCALE SETTLING TIME Scope Trigger (5.0V/div)
HALF-SCALE SETTLING TIME Scope Trigger (5.0V/div)
Large-Signal Output (1.0V/div) Small-Signal Error (1mV/div)
Small-Signal Error (1mV/div) Large-Signal Output (1V/div)
Half-Scale Code Change 4000H to C000H Output Loaded with 2k and 200pF to GND Time (2s/div)
Half-Scale Code Change C000H to 4000H Output Loaded with 2k and 200pF to GND Time (2s/div)
POWER-ON RESET TO 0V Loaded with 2k to VDD. VDD (2V/div)
EXITING POWER-DOWN (8000H Loaded) Scope Trigger (5.0V/div)
Output (1.0V/div)
VOUT (1V/div)
Time (50s/div)
Time (2s/div)
DAC8531
SBAS192B
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TYPICAL CHARACTERISTICS: VDD = 5V (Cont.)
At TA = +25C, VDD = 5V, unless otherwise noted.
CODE CHANGE GLITCH
VOUT (50mV/div)
Glitch Waveform (50mV/div)
Time (2s/div)
TYPICAL CHARACTERISTICS: VDD = 2.7V
At TA = +25C, VDD = 2.7V, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (-40C) 64 48 32 16 0 -16 -32 -48 -64 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 64 48 32 16 0 -16 -32 -48 -64 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25C)
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105C) 64 48 32 16 0 -16 -32 -48 -64 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
20 15 10
Error (mV)
DLE (LSB)
LE (LSB)
ZERO-SCALE ERROR vs TEMPERATURE
LE (LSB)
5 0 -5 -10 -15 -20 -40
DLE (LSB)
0
40 Temperature (C)
80
120
8
DAC8531
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SBAS192B
TYPICAL CHARACTERISTICS: VDD = 2.7V
At TA = +25C, VDD = 2.7V, unless otherwise noted. NOTE: All references to IDD include IREF current.
FULL-SCALE ERROR vs TEMPERATURE 20 15 10
1500 2000
IDD HISTOGRAM
Error (mV)
0 -5 -10 -15 -20 -40
Frequency
0 40 Temperature (C) 80 120
5
1000
500
0 100 130 160 190 220 250 280 310 340 370 400 IDD (A)
SOURCE AND SINK CURRENT CAPABILITY 3.0 2.5 DAC Loaded with FFFFH 2.0
VOUT (V)
SUPPLY CURRENT vs DIGITAL INPUT CODE 500
400
1.5 1.0 0.5 0.0 0 5 10 ISOURCE/SINK (mA) 15
IDD (A) DAC Loaded with 0000H
300
200
100
0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
POWER SUPPLY CURRENT vs TEMPERATURE 350 300 200 180 160
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
Quiescent Current (A)
250 200 150 100 50 0 -40 0 40 Temperature (C) 80 120
IDD (A)
140 120 100 80 0 0.5 1 1.5 VLOGIC (V) 2 2.5 3
DAC8531
SBAS192B
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9
TYPICAL CHARACTERISTICS: VDD = 2.7V (Cont.)
At TA = +25C, VDD = 2.7V, unless otherwise noted.
FULL-SCALE SETTLING TIME Scope Trigger (5.0V/div) Large-Signal Output (1.0V/div)
FULL-SCALE SETTLING TIME Scope Trigger (5.0V/div)
Small-Signal Error (1mV/div) Large-Signal Output (1.0V/div)
Small-Signal Error (1mV/div)
Full-Scale Code Change 0000H to FFFFH Output Loaded with 2k and 200pF to GND
Full-Scale Code Change FFFFH to 0000H Output Loaded with 2k and 200pF to GND
Time (2s/div)
Time (2s/div)
HALF-SCALE SETTLING TIME Scope Trigger (5.0V/div)
HALF-SCALE SETTLING TIME Scope Trigger (5.0V/div)
Large-Signal Output (1.0V/div) Small-Signal Error (1mV/div) Small-Signal Error (1mV/div) Half-Scale Code Change 4000H to C000H Output Loaded with 2k and 200pF to GND Time (2s/div) Large-Signal Output (1.0V/div) Half-Scale Code Change C000H to 4000H Output Loaded with 2k and 200pF to GND Time (2s/div)
POWER-ON RESET to 0V Loaded with 2k to VDD. VDD (1V/div)
EXITING POWER-DOWN (8000H Loaded) Scope Trigger (5.0V/div)
Output (1.0V/div)
VOUT (1V/div)
Time (50s/div)
Time (2s/div)
10
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SBAS192B
TYPICAL CHARACTERISTICS: VDD = 2.7V (Cont.)
At TA = +25C, VDD = 2.7V, unless otherwise noted.
CODE CHANGE GLITCH
VOUT (20mV/div)
Glitch Waveform (20mV/div)
Time (2s/div)
THEORY OF OPERATION
DAC SECTION
The architecture consists of a string DAC followed by an output buffer amplifier. Figure 1 shows a block diagram of the DAC architecture.
RESISTOR STRING
Figure 2 shows the resistor string section. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. It is ensured monotonic because it is a string of resistors.
VDD
VFB
R
DAC Register
REF (+) Resistor String REF(-)
VOUT Output Amplifier
R
GND
R
To Output Amplifier
FIGURE 1. DAC8531 Architecture. The input coding to the DAC8531 is straight binary, so the ideal output voltage is given by:
VOUT = VREF *
D 65536
R
where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535.
R
FIGURE 2. Resistor String.
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OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range of 0V to VDD. It is capable of driving a load of 2k in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1V/s with a full-scale settling time of 8s with the output unloaded. The inverting input of the output amplifier is brought out to the VFB pin. This allows for better accuracy in critical applications by tying the VFB point and the amplifier output together directly at the load. Other signal conditioning circuitry may also be connected between these points for specific applications.
SYNC buffer draws more current when the SYNC signal is HIGH than it does when it is LOW, SYNC should be idled LOW between write sequences for lowest power operation of the part. As mentioned above, it must be brought HIGH again just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide, as shown in Figure 3. The first six bits are "don't cares". The next two bits (PD1 and PD0) are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). There is a more complete description of the various modes in the Power-Down Modes section. The next 16 bits are the data bits. These are transferred to the DAC register on the 24th falling edge of SCLK.
SERIAL INTERFACE
The DAC8531 has a three-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPI, QSPI, and Microwire interface standards as well as most DSPs. See the Serial Write Operation timing diagram for an example of a typical write sequence. The write sequence begins by bringing the SYNC line LOW. Data from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30MHz, making the DAC8531 compatible with high-speed (DSPs). On the 24th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed (i.e., a change in DAC register contents and/or a change in the mode of operation). At this point, the SYNC line may be kept LOW or brought HIGH. In either case, it must be brought HIGH for a minimum of 33ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Since the
DB23 X X X X X X PD1 PD0 D15 D14 D13 D12
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the DAC is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents or a change in the operating mode occurs, as shown in Figure 4.
POWER-ON RESET
The DAC8531 contains a power-on reset circuit that controls the output voltage during power-up. On power-up, the DAC register is filled with zeros and the output voltage is 0V; it remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up.
DB0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FIGURE 3. Data Input Register.
24th Falling Edge CLK SYNC
24th Falling Edge
DIN
DB23
DB0
DB23
DB0
Invalid Write Sequence: SYNC HIGH before 24th Falling Edge
Valid Write Sequence: Output Updates on the 24th Falling Edge
FIGURE 4. SYNC Interrupt Facility.
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SBAS192B
POWER-DOWN MODES
The DAC8531 supports four separate modes of operation. These modes are programmable by setting two bits (PD1 and PD0) in the control register. Table I shows how the state of the bits corresponds to the mode of operation of the device.
PD1 (DB17) 0 -- 0 1 1 PD0 (DB16) 0 -- 1 0 1 OPERATING MODE Normal Operation Power-Down Modes Output 1k to GND Output 100k to GND High-Z
MICROPROCESSOR INTERFACING
DAC8531 TO 8051 INTERFACE
Figure 6 shows a serial interface between the DAC8531 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8531, while RXD drives the serial data line of the part. The SYNC signal is derived from a bit-programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the DAC8531, P3.3 is taken LOW. The 8051 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left LOW after the first eight bits are transmitted and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken HIGH following the completion of the third write cycle. The 8051 outputs the serial data in a format which has the LSB first. The DAC8531 requires its data with the MSB as the first bit received. The 8051 transmit routine must therefore take this into account, and "mirror" the data as needed.
TABLE I. Modes of Operation for the DAC8531. When both bits are set to 0, the part works normally with its typical current consumption of 250A at 5V. However, for the three power-down modes, the supply current falls to 200nA at 5V (50nA at 3V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different options. The output is connected internally to GND through a 1k resistor, a 100k resistor, or it is left opencircuited (High-Z). The output stage is illustrated in Figure 5.
80C51/80L51(1) P3.3 TXD RXD NOTE: (1) Additional pins omitted for clarity.
DAC8531(1) SYNC SCLK DIN
VFB
Resistor String DAC
Amplifier
VOUT
FIGURE 6. DAC8531 to 80C51/80L51 Interface. DAC8531 TO Microwire INTERFACE
Power-Down Circuitry
Resistor Network
Figure 7 shows an interface between the DAC8531 and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the DAC8531 on the rising edge of the SK signal.
FIGURE 5. Output Stage During Power-Down. All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 2.5s for VDD = 5V, and 5s for VDD = 3V. See the Typical Characteristics for more information.
MicrowireTM CS SK SO NOTE: (1) Additional pins omitted for clarity.
DAC8531(1) SYNC SCLK DIN
Microwire is a registered trademark of National Semiconductor.
FIGURE 7. DAC8531 to Microwire Interface.
DAC8531
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DAC8531 TO 68HC11 INTERFACE
Figure 8 shows a serial interface between the DAC8531 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8531, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to what was done for the 8051.
power supply is quite noisy or if the system supply voltages are at some value other than 5V. The REF02 will output a steady supply voltage for the DAC8531. If the REF02 is used, the typical current it needs to supply to the DAC8531 is 250A. This is with no load on the output of the DAC. When the DAC output is loaded, the REF02 also needs to supply the current to the load. The total current required (with a 5k load on the DAC output) is: 250A + (5V/ 5k) = 1.29mA The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 322V for the 1.29mA current drawn from it. This corresponds to a 4.2LSB error.
68HC11(1) PC7 SCK MOSI NOTE: (1) Additional pins omitted for clarity.
DAC8531(1) SYNC SCLK DIN
BIPOLAR OPERATION USING THE DAC8531
FIGURE 8. DAC8531 to 68HC11 Interface. The 68HC11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data is being transmitted to the DAC, the SYNC line is taken LOW (PC7). Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the DAC8531, PC7 is left LOW after the first eight bits are transferred, then a second and third serial write operation is performed to the DAC and PC7 is taken HIGH at the end of this procedure. The DAC8531 has been designed for single-supply operation but a bipolar output range is also possible using the circuit in Figure 10. The circuit shown will give an output voltage range of VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier. The output voltage for any input code can be calculated as follows: R D R1 + R 2 VO = VREF * - VREF * 2 * 65536 R1 R1 where D represents the input code in decimal (0-65535). With VREF = 5V, R1 = R2 = 10k:
10 * D VO = - 5V 65536
APPLICATIONS
USING REF02 AS A POWER SUPPLY FOR THE DAC8531
Due to the extremely low supply current required by the DAC8531, an alternative option is to use a REF02 +5V precision voltage reference to supply the required voltage to the part, as shown in Figure 9. This is especially useful if the
This is an output voltage range of 5V with 0000H corresponding to a -5V output and FFFFH corresponding to a +5V output. Similarly, using VREF = 2.5V, 2.5V output voltage raw can be achieved.
LAYOUT
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. As the DAC8531 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to keep digital noise from appearing at the output. Due to the single ground pin of the DAC8531, all return currents, including digital and analog return currents, must flow through the GND pin. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system.
+15
+5V REF02 285A
SYNC Three-Wire Serial Interface SCLK DIN DAC8531 VOUT = 0V to 5V
FIGURE 9. REF02 as a Power Supply to the DAC8531.
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DAC8531
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SBAS192B
The power applied to VDD should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output.
As with the GND connection, VDD should be connected to a +5V power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, the 1F to 10F and 0.1F bypass capacitors are strongly recommended. In some situations, additional bypassing may be required, such as a 100F electrolytic capacitor or even a "Pi" filter made up of inductors and capacitors--all designed to essentially lowpass filter the +5V supply, removing the high-frequency noise.
VREF
R2 10k +5V R1 10k OPA703 VFB VREF 10F 0.1F DAC8531 VOUT -5V
5V
Three-Wire Serial Interface
FIGURE 10. Bipolar Operation with the DAC8531.
DAC8531
SBAS192B
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PACKAGE DRAWINGS
DGK (R-PDSO-G8)
0,38 0,25 8 5
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,08 M
0,15 NOM 3,05 2,95 4,98 4,78
Gage Plane 0,25 1 3,05 2,95 4 0- 6 0,69 0,41
Seating Plane 1,07 MAX 0,15 0,05 0,10
4073329/C 08/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187
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DAC8531
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SBAS192B
PACKAGE DRAWINGS (Cont.)
DAC8531
SBAS192B
www.ti.com
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