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(R)
PCM1760P/U DF1760P/U
Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM
FEATURES
q DUAL 20-BIT MONOLITHIC MODULATOR (PCM1760) AND MONOLITHIC DECIMATING DIGITAL FILTER (DF1760) q HIGH PERFORMANCE: THD+N: -92dB typ, -90dB max Dynamic Range: 108dB typ SNR: 108dB min, 110dB typ Channel Separation: 98dB typ, 94dB min q 64X OVERSAMPLING q CO-PHASE CONVERSION q RUNS ON 256fs OR 384fs SYSTEM CLOCK q VERSATILE INTERFACE CAPABILITY: 16-, 20-Bit Output MSB First or LSB First Format q OPTIONAL FUNCTIONS: Offset Error Calibration Overflow Detection Power Down Mode (DF1760) q RUNS ON 5V SUPPLIES (PCM1760) AND 5V SUPPLY (DF1760) q COMPACT 28-PIN PACKAGES: 28-Pin DIP and SOIC
PCM1760
DESCRIPTION
The PCM1760 and DF1760 combine for a low-cost, high-performance dual 20-bit, 48kHz sampling analog-to-digital conversion system which is specifically designed for dynamic applications. The PCM1760/DF1760 pair form a 4-bit, 4th order, 64X oversampling analog-to-digital converter. The PCM1760 is a delta-sigma modulator that uses a 4-bit quantizer within the modulation loop to achieve very high dynamic range. The DF1760 is a high-performance decimating digital filter. The DF1760 accepts 4-bit 64fs data from the PCM1760 and decimates to 20-bit 1fs data. The FIR filter of the DF1760 has pass-band ripple of less than 0.001dB and greater than 100dB of the reject band attenuation.
DF1760
Analog Input (L)
4 Stage, 4-Bit Delta-Sigma Modulator 64fs
64fs Timing Control and Interface 256fs
1/16 Filter
4fs
FIR Filter
fs Timing Control and Interface
Data
Analog Input (R)
4 Stage, 4-Bit Delta-Sigma Modulator
System Clock 256/384fs
International Airport Industrial Park * Mailing Address: PO Box 11400 Tel: (520) 746-1111 * Twx: 910-952-1111 * Cable: BBRCORP *
(c)
* Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd. * Tucson, AZ 85706 Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132 PDS-1174C Printed in U.S.A. July, 1994
1993 Burr-Brown Corporation
SBAS025
SPECIFICATIONS
ELECTRICAL
At TA = +25C, VCC, Vdd = +5V, +VDD = +5V, fS = 48kHz and ext. components = 2% unless otherwise noted. PCM1760/DF1760 PARAMETER RESOLUTION ANALOG INPUT Input Range Input Impedance SAMPLING FREQUENCY Cover Range of fs ACCURACY Gain Error Gain Mismatch Bipolar Zero Error Gain Drift Bipolar Zero Drift DYNAMIC CHARACTERISTICS(4) P, U P-L, U-L THD+N/(-20dBFS) P, U P-L, U-L THD+N/(-60dBFS) P, U P-L, U-L Dynamic Range P, U P-L, U-L SNR P, U P-L, U-L Frequency Response Channel Separation DIGITAL FILTER Over Sample Rate Ripple in Band Stopband Attenuation -1 Stopband Attenuation -2 LOGIC INPUTS AND OUTPUTS Logic Family Input Frequency (System Clock 1) Frequency (System Clock 2) Duty Cycle (System Clock 1) Duty Cycle (System Clock 2) Data Clock Input Logic Family Output Data Clock Output Data Coding Data Bit Length Data Format Output Data Delay POWER SUPPLY REQUIREMENTS Supply Voltage VCC Vdd +VDD Supply Current +ICC -ICC +Idd -IDD +IDD -1 +IDD -2 Power Consumption PCM1760 PCM1760 DF1760 PCM1760 PCM1760 PCM1760 PCM1760 DF1760, Normal Mode DF1760, Power-Down Mode PCM1760 DF1760, Normal Mode DF1760, Power-Down Mode 4.75 4.75 4.75 5.0 5.0 5.0 24 -30 12 -8 40 4 370 200 20 5.25 5.25 5.25 36 -45 18 -12 55 6.6 500 275 33 V V V mA mA mA mA mA mA mW mW mW C C 256fs 384fs 256fs 384fs TTL Level Compatible CMOS 12.288 18.432 50 50 48 CMOS 64 Two's Complement 20 Selectable 1.5 MHz MHz % % fs fs Bits ms 64 0 - 0.04535fs 0.5465fs - 63.4535fs 0.5465fs - 3.4535fs 0.0001 -94 -100 fs dB dB dB THD+N/(0dBFS) fIN = 1kHz fIN = 1kHz fIN = 1kHz fIN = 1kHz, VIN = -60dBFS, A Filter VIN = 0, A Filter fIN = 20kHz fIN = 1kHz, A Filter 104 104 108 106 94 -92 -90 -76 -76 -44 -44 108 108 110 110 0.1 98 -90 -88 -70 -70 -42 -42 dB dB dB dB dB dB dB dB dB dB dB dB 0.5 VIN = 0 at 20s After Power-On 0C to +70C 0C to +70C 1.0 0.5 0.4 dB dB % FSR(2) ppmfs/C ppmfs/C Integrator Constants: Application(1) 30 48 50 kHz RIN1 = 2.2k RIN1 = 2.2k 2.5 RIN1 Vp-p CONDITIONS MIN 20 TYP MAX UNITS Bits
100 20
40 45 32
60 55 64
16 fs = 48kHz
TEMPERATURE RANGE Operating Storage PCM1760/DF1760 PCM1760/DF1760 0 -50 +25 +70 +125
NOTES: (1) Integrator Constants are determined by the external components shown in the block diagram. (2) FSR means Full Scale Range, digital output code is from 90000H to 70000H, FSR = 5.0V. (3) Use 20-bit DAC, 20kHz LPF, 400Hz HPF, average response. (4) Average response using a 20-bit reconstruction DAC with 20kHz low-pass filter and 400Hz high-pass filter.
(R)
PCM1760P/U DF1760P/U
2
ABSOLUTE MAXIMUM RATINGS--PCM1760
Supply Voltage ..................................................................................... 6V Voltage Mismatch ............................................................................... 0.1V Analog Input ........................................................................................ VCC Digital Input ............................................................................... +VDD +0.3V GND -0.3V Power Dissipation/P ....................................................................... 580mW Power Dissipation/U ....................................................................... 550mW Lead Temperature/P (soldering, 10s) .............................................. 260C Lead Temperature/U (soldering, 10s) .............................................. 235C Operating Temperature ......................................................... 0C to +70C Storage Temperature ...................................................... -50C to +125C
ABSOLUTE MAXIMUM RATINGS--DF1760
Supply Voltage .................................................................................... 7.0V Voltage Mismatch ............................................................................... 0.1V Digital Input ............................................................................... +VDD +0.5V VSS -0.5V Input Current 20mA Power Dissipation/P ....................................................................... 460mW Power Dissipation/U ....................................................................... 440mW Lead Temperature/P (soldering, 10s) .............................................. 260C Lead Temperature/U (soldering, 10s, reflow) ................................... 235C Operating Temperature .......................................................... 0C to +70c Storage Temperature ...................................................... -50C to +125C
ORDERING INFORMATION
MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE PDIP SOIC PDIP SOIC PDIP SOIC THD +N (fs) -90dB -90dB -88dB -88dB NA NA SNR 108dB 108dB 106dB 106dB NA NA
PACKAGE INFORMATION
MODEL PCM1760P PCM1760U PCM1760P-L PCM1760U-L DF1760P DF1760U PACKAGE 28-Pin PDIP 28-Pin SOIC 28-Pin PDIP 28-Pin SOIC 28-Pin PDIP 28-Pin SOIC PACKAGE DRAWING NUMBER(1) 800 804 800 804 801 805
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.
PIN ASSIGNMENTS PCM1760
Top View SOIC/DIP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O(1) O I O I - - - - - - I O I O - - O O I - - - O O O O - - NAME Out-2R In-2R Out-1R In-1R SERVO DC +VCC AGND -VCC BGDC NC In-1L Out-1L In-2L Out-2L NC BPODC-L L/RCK Strobe 256fs -VDD DGND +VDD D0 D1 D2 D3 BPODC-R NC DESCRIPTION Right Channel Second Integrator Output Right Channel Second Integrator Input Right Channel First Integrator Output Right Channel First Integrator Input Servo Amp Decoupling Capacitor +5V Analog Supply Voltage Analog Common -5V Analog Supply Voltage Band Gap Reference Decoupling Capacitor No Connection Left Channel First Integrator Input Left Channel First Integrator Output Left Channel Second Integrator Input Left Channel Second Integrator Output No Connection Left Channel Bipolar Offset Decoupling Capacitor LR Clock Output (64fs) Data Strobe Output (128fs) 256fs Clock Input -5V Digital Supply Voltage Digital Common +5V Digital Supply Voltage D0 Data Output (LSB) D1 Data Output D2 Data Output D3 Data Output (MSB) Right Channel Bipolar Offset Decoupling Capacitor No Connection
Out-2R In-2R Out-1R In-1R SERVO DC +VCC AGND -VCC BGDC
1 2 3 4 5 6 7 PCM1760 8 9
28 NC 27 BPODC-R 26 D3 25 D2 24 D1 23 D0 22 +VDD 21 DGND 20 -VDD 19 256fs 18 Strobe 17 L/RCK 16 BPODC-L 15 NC
NC 10 In-1L 11 Out-1L 12 In-2L 13 Out-2L 14
NOTE: (1) O = Output terminal; I = Input terminal.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
(R)
3
PCM1760P/U DF1760P/U
PIN ASSIGNMENTS DF1760
Top View OVL OVR D3 D2 D1 D0 TP1 VSS1 VDD1 1 2 3 4 5 6 7 DF1760 8 9 21 /PD 20 LRSC 19 FSYNC 18 SDATA 17 L/R 16 SCLK 15 SYSCLK 28 VSS2 27 VDD2 26 TP2 25 CLKSEL 24 S/M 23 Mode 1 22 Mode 2 SOIC/DIP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O(1) O O I I I I - - - O I I I O I I /O I /O O I /O I I I I I I - - - NAME OVL OVR D3 D2 D1 D0 TP1 VSS1 VDD1 256fs Strobe LRCK CALD CAL SYSCLK SCLK L/R SDATA FSYNC LRSC /PD Mode2 Mode1 S/M CLKSEL TP2 VDD2 VSS2 DESCRIPTION Left Channel Overflow Output (Active High) Right Channel Overflow Output (Active High) D3 Data Input (MSB) D2 Data Input D1 Data Input D0 Data Input (LSB) Test Pin (No Connection) Common Channel 1 +5V Channel 1 256fs Clock Output Data Strobe Clock Input (128fs) LR Clock Input Calibration Function Enable (Active Low) Calibration Output (High During Calibration) System Clock Input (256fs or 384fs) Data Clock LR Channel Phase Clock Serial Data Output (1fs) Frame Clock (2fs) Phase Control of LR Channel Phase Clock Power Down Mode Enable Input (Active Low) Output Format Selection Input 2 Output Format Selection Input 1 Slave/Master Mode Selection Input (High Makes Slave Mode System Clock Selection Input (High Makes 256fs) Test Pin (No Connection) +5V Channel 2 Common Channel 2
256fs 10 Strobe 11 LRCK 12 CALD 13 CAL 14
NOTE: (1) O = Output terminal; I = Input terminal.
BLOCK DIAGRAM OF DF1760
D3 D2 D1 D0 Strobe LRCK
Input LAT
1/16 Decimation Filter
Boost Filter
CALD CAL
VSS1 VDD1
Input RAM
Multiplier
ALU
Calibration
Output Control
P/S
Coefficient
Overflow DET
256fs
Main Timing Control
Temporary RAM
Test
SYSCLK CLKSEL /PD
VSS2 VDD2
S/M TP1 OVL SDATA TP2 OVR MODE 1 (16-, 20-Bit) MODE 2 LRSC FSYNC L/R SCLK
(R)
PCM1760P/U DF1760P/U
4
BLOCK DIAGRAM OF PCM1760
C1R
C2R
C3R
C4R
RT1R
RT2R RZ1R +
RIN1R
RIN2R NC
RCH, VIN
4 In-1R Out-1R
3
2 In-2R Out-2R
1
28
27 BPODC-R
S/HINR 1R SERVO DC 5 RCH BPO IOUTR IOUTR +5V + +VCC 6 AGND 7 + -5V 8 Sub + IOUTL IOUTL LCH DAC -VCC Band Gap Bias Servo Amp RCH DAC 2R
RCH S/H D3 26 D2 25 D e c o d e r D1 24 D0 23 +VDD 22 DGND T i m i n g LCH ADC C T L 21 -VDD 20 256fs 19 Strobe 18 L/R CK 17 + -5V + +5V
+
RCH ADC
BGDC 9 LCH BPO
1L NC 10
2L S/HINL
LCH S/H
In-1L 11
Out-1L 12 13
In-2L
Out-2L 14 15
NC 16 +
BPODC-L
RIN1L
RIN2L RZ1L
LCH, VIN C1L C2L C3L C4L
External Components Condition RIN 1R/L C1, C2 R/L 2.2k 2200pF C3, C4 R/L RT2 R/L 1800pF 560 RTIR/L 470 RZ1 R/L 1.2k RIN 2R/L 1.3k
RT1L
RT2L
(R)
5
PCM1760P/U DF1760P/U
TYPICAL PERFORMANCE CURVES
OVERALL PASS-BAND CHARACTERISTICS OF THE DF1760 1.0 50 OVERALL CHARACTERISTICS OF THE DF1760
0.5
0
(dB)
(dB)
0
-50
-0.5
-100
-1.0 0 fs / 4 fs / 2
-150 0 16 32 (fs) 46 64
PASS-BAND CHARACTERISTICS OF THE FIR PORTION OF THE DF1760 0.0010
TOTAL PASS-BAND FREQUENCY RESPONSE, COMBINATION OF PCM1760 AND DF1760 0.3 0.2
0.0005
Amplitude (dB)
fs / 4 fs / 2
0.1 0 -0.1 -0.2
(dB)
0
-0.0005
-0.0010 0
-0.3 0.1 1 Frequency (kHz) 10 100
TYPICAL FFT ANALYSIS OF THE 1kHz fs INPUT SIGNAL 0 -20 -40
Amplitude (dB)
-60 -80 -100 -120 -140 -160 -180 -200 0 6 fs = 48.000000kHz 12 Frequency (kHz) FC1 = 1.171876kHz 18 24
(R)
PCM1760P/U DF1760P/U
6
1800pF 1.2k
560
470 1.3k PCM1760 + DF1760 10F
1800pF
RIN 2.2k +
0.1F + 3.3F 28 VSS2 27 VDD2 +5V VDD
RCH In
2200pF
2200pF
+5V VCC + + 7 AGND DGND + 0.1F 3.3F 21 0.1F 3.3F + 3.3F 0.1F 0.1F + 0.1F 3.3F 3.3F
1 2 3 4 5 6 Out-2R In-2R Out-1R In-1R Servo DC +VCC BPO DCR D3 D2 D1 D0 +VDD 3 4 5 6 8 D3 D2 D1 D0 VSS1 27 26 25 24 23 22
10F
25 CLKSEL 24 S/M 23 Mode 1 22 Mode 2 21 PD
BASIC CONNECTION DIAGRAM OF PCM1760 AND DF1760
7
+ 10F 8 9 11 12 13 14 -VDD 256fs STB L/R CLK BPO DCL + 10F -VCC BG DC In-1L Out-1L In-2L Out-2L 20 19 18 17 16 1.3k -5V VDD +5V +5V VDD VDD 1.2k
-5V VCC
9 V 10 DD1 256fs 11 STB 12 LRCK
FSYNC SDATA L/R SCLK SYSCLK +5V VDD
19 18 17 16 15
Digital I/O 10k +
+5V VDD
RIN 2.2k
47F +
LCH In
3.3F
0.1F
2200pF
2200pF
Power on Reset
470
SYS CLK
1800pF
560
PCM1760P/U DF1760P/U
1800pF
(R)
FUNCTIONS OF THE DIGITAL FILTER
SYSTEM CLOCK The DF1760 can accept a system clock of either 256fs or 384fs. If a 384fs system clock is used, the DF1760 divides by 2/3 to create the 256fs system clock required for the PCM1760. The system clock is applied to pin 15 (SYSCLK input). The actual clock selection is done by setting pin 25 (CLKSEL input) "high" for 256fs clock and "LOW" for 384fs clock. The detailed timing requirements for the system clock are shown in Figure 3c.
CLKSEL H L SYSCLK 256fs 384fs
OFFSET CALIBRATION MODE The offset error is calibrated by storing the digital data when the input is zero in registers and subtracting it from the future data with actual signal input.
CALD H L CALIBRATION Disable Enable
MASTER/SLAVE MODE The DF1760 can be used in both the master mode and slave mode. In the master mode, the DF1760 outputs L/R (left/ right channel phase clock), SCLK (data clock) and FSYNC (frame clock 2fs) signals. In the slave mode, the DF1760 accepts L/R, SCLK and FSYNC signals. The mode selection is done by taking pin 24 (S/M INPUT) "HIGH" for slave mode and "LOW" for master mode.
S/M H L MODE Slave Master
To enable the calibration mode, set the CALD input (Pin 13) "LOW". The calibration mode is disabled by setting the CALD input (Pin 13) "HIGH". The calibration cycle is initiated by setting the /PD input (Pin 21) "LOW" for more than 2 system clock periods and then setting it "HIGH". During the calibration cycle, the CAL output (Pin 14) becomes "HIGH", all the serial data is forced to "LOW", and the L/R (Pin 17), SCLK (Pin 16) and FSYNC (Pin 19) pins become input terminals after the completion of the calibration cycle. The CAL output is "LOW". POWER DOWN MODE/RESET The /PD input (Pin 21) has two functions. First, it should be set at "HIGH" after application or restoration of power (VSS and/or VDD) to accomplish the power-on/mode reset function. The detail timing requirements for this function are shown in Figure 3f. Second, the DF1760 is placed in the power down mode by setting the /PD input (Pin 21) "LOW". Set the /PD input (Pin 21) "HIGH" for normal operation mode.
/PD H L OPERATION Normal Power Down
OUTPUT DATA FORMAT The serial output data has four possible formats. The selection of the formats can be done by the Mode 1 and Mode 2 inputs.
MODE 1 H L H L MODE 2 H H L L FORMATS MSB First, 16 Bits, Falling Edge MSB First, 20 Bits, Falling Edge MSB First, 20 Bits, Rising Edge LSB First, 20 Bits, Falling Edge
The power dissipation of the DF1760 in the power down mode is about 1/10 of the normal operation mode. During the power down mode, the L/R, SCLK, and FSYNC pins become input pins and all the serial data is forced "LOW". The 256fs output is enabled even in the power down mode. The detailed timing of the power down mode operation and the offset calibration is shown in Figure 3b.
LR CHANNEL PHASE CLOCK The status of the LR channel phase clock can be set by the LRSC input.
LRSC H L L/R CLOCK AND CHANNEL H = LCH, L = LCH, L = RCH H = RCH
+Detect Level
-Detect Level TOR TOF TOR TOF
OVERFLOW DETECTION When a near-to-clipping input condition is detected, OVL output (Pin 1), or OVR output (Pin 2), becomes "HIGH" for a duration of 4096/fs (about 85ms) depending upon on the channel detected. The OVL and OVR output return to "LOW" after 4096/fs duration automatically.
(R)
OVL (OVR)
DESCRIPTION Delay from Overflow Detection to OVL (OVR) Output OVL (OVR) Output Pulse Width
NAME TOR TOF
MIN - -
TYP - 4096
MAX 0 -
UNITS ns 1/fs
FIGURE 3a. DF1760 Overflow Detection. 8
PCM1760P/U DF1760P/U
TPDW /PD TPCR CAL TPSF SDATA TCSV
SDATA TSLR L/R
DESCRIPTION Pulse Width of /PD Input Delay from /PD Input to CAL Output Calibration Cycle Duration Delay from /PD Input to SDATA L Delay from Completion of Calibration to SDATA Valid NAME TPDW TPCR TPCF TPSF TCSV MIN 2 - - - - TYP - - 4096 - 1 MAX - 6 - 6 - UNITS 1/Fclk 1/Fclk 1/fs 1/Fclk 1/fs DESCRIPTION SCLK Frequency Low Duration of FSCLK High Duration of FSCLK Delay from SCLK to L/R Edge Delay from Falling Edge of SCLK to SDATA Valid Delay from SCLK to FSYNC Edge Delay from Rising Edge of SCLK to SDATA Valid Delay from SDATA Valid to Rising Edge of SCLK NAME TCLKL TCLKH MIN 31 31 TYP - - MAX - - UNITS ns ns NAME FSLK TSLKL TSLKH TSLR TDSS TSF TDSV TSDR MIN 32fs 100 100 -70 - -70 100 100
TSLKH TSLKL
TPCF
SCKL TDSS TDSV
TSDR
TSF FSYNC
TYP 48fs - - - - - - -
MAX 64fs - - 70 50 0 - -
UNITS - ns ns ns ns ns ns ns
FIGURE 3b. DF1760 Power Down and Offset Calibration.
TCLKH TCLKL 2.0V 1.4V 0.8V TLH
SYSTEM CLOCK: 256fs DESCRIPTION Low Level Duration High Level Duration SYSTEM CLOCK: 384fs DESCRIPTION Low Level Duration High Level Duration Rise Time Fall Time NAME TCLKL TCLKH TLH THL MIN 24 24 - - TYP - - - - MAX - - 6 6 UNITS ns ns ns ns
THL
FIGURE 3e. Timing of Slave Mode, DF1760.
FIGURE 3c. System Clock Timing Requirements of DF1760.
TDSV SCLK SDATA
T
SLR
TPDW
TPDW
TDSS
T
SDR
TDSV
TDSS
L/R TSP PD TSP
L/R FSYNC TSF TSF
TPDW
TPDW
APPLIES TO MODE Master/Slave Slave Slave
DESCRIPTION DESCRIPTION SCLK Frequency SCLK Frequency Duty Cycle FSYNC Frequency FSYNC Frequency Duty Cycle Delay from SCLK to L/R Edge Delay from Falling Edge of SCLK to SDATA Valid Delay from SCLK to FSYNC Edge Delay from Rising Edge of SCLK to SDATA Valid Delay from SDATA Valid to Rising Edge of SCLK TSLR TDSS TSF TSDR TDSV FSYNC NAME FSLK MIN - - - - -20 - -20 100 100 TYP 64fs 50 2fs 50 - - - - - MAX - - - - 50 50 50 - - % ns ns ns ns ns % UNITS Power on to PD PD to L/R (LRSC = "H") PD to L/R (LRSC = "L")
NAME TPDW TSP TSP
MIN 2 -1 -1
TYP
MAX
UNITS(1) 1/fs
+1 +1
1/Fclk 1/Fclk
NOTE: (1) fs: sampling rate. Fclk: system clock frequency.
FIGURE 3f. Power On and Mode Reset Timing.
FIGURE 3d. Output Timing of Master Mode, DF1760.
(R)
9
PCM1760P/U DF1760P/U
THEORY OF OPERATION
MULTI-BIT ENHANCED NOISE SHAPING A block diagram of a typical 1-bit delta-sigma modulator is shown in Figure 4. In Figure 4, the quantizer consists of a single bit which has two possible states, either "0" or "1". The input signal is sampled at a much higher sample rate than the nyquist sampling frequency. The quantizer output data stream is digitally filtered for higher resolution nyquist data. The theoretical SNR is determined by the number of the order of the integrator and the oversampling rate.
Integrator Input + Quantizer Output
The DF1760 accepts the four-bit 64fs noise shaped data stream from the PCM1760 and decimates to 1/16 with an initial filter, and then decimates to 1fs 20-bit data using a 4x oversampling filter. The PCM1760 and DF1760 combination achieves a dynamic range of 108dB and SNR of 110dB even with a single-ended input.
(2)
28
27 DF1760
z-1
8
(1)
9
FIGURE 4. Single Stage 1-Bit Delta-Sigma.
Integrator Input + nBit Output ADC
(1)
(1)
22
21
20 PCM1760
nBit DAC
6
(1)
7
(1)
8
FIGURE 5. Single Stage Multi-bit Delta-Sigma. There is a practical limit to increasing the numbers of order of the integrator due to an inherent oscillation in the modulator. There is also a limit to increasing the sample rate due to the increase in jitter sensitivity associated with high clock frequencies. The PCM1760 utilizes a four-bit quantizer instead of the conventional one-bit method. The quantizing noise of a fourbit quantizer is 1/16 of the one-bit version. Using the fourbit quantizer allows for a lesser order number of the integrator and a lower oversampling rate to achieve similar performance to that of a more complex one-bit system. A block diagram of the PCM1760 modulator is shown in Figure 6. The PCM1760 is a fourth-order integrator that samples at 64x oversampling, and samples left and right channel input signal simultaneously.
2nd Order Integrator Input + 2nd Order Integrator +
Digital Common +5V GND
Analog Common +5V GND Power Supply -5V
Power Supply
NOTE: (1) Tantalum 3.3F. (2) Ceramic 0.1F.
FIGURE 7. Recommended Power Supply Connection and Decoupling. LAYOUT PRECAUTIONS Analog common and digital common of the PCM1760 are not connected internally. These should be connected together with the common of the DF1760 as close to the unit as possible, preferably to a large ground plane under the PCM1760. The use of a separate +5V supply is recommended for the PCM1760 and DF1760, and to connect the common at one point as described above. Low impedance analog and digital commons returns are essential for better performance. The power supplies should be bypassed with tantalum capacitors as close as possible to the units. See Figure 7 for recommended common connections and power supplies bypassing.
4Bits Output ADC 4Bits DAC
FIGURE 6. Multi-bit Enhanced Noise Shaping.
(R)
PCM1760P/U DF1760P/U
10
OUTPUT TONE ELIMINATION When the sampling frequency (fs) is between 40kHz and 50 kHz and the L/R relative offset voltage (Vs) is less than or equal to 0.05% of full scale range, the PCM1760 may output a tone similar to an idle tone. This tone is very low and its frequency depends on the input L/R relative offset voltage, Vs. This tone never occurs when the sampling frequency (fs) is 32kHz. To avoid this tone, the offset voltage should be summed using an amplifier, buffer, active low pass filter, etc., to cause the input L/R relative offset voltage (Vs) to be greater than 0.05% of full scale range. It is recommended that: (A) Sum offset at both L/R channels Lch: VIL = -20mV 10% Rch: VIR = +10mV 10% (B) Sum offset at L channel Lch: VIL = -30mV 10% Rch: VIR = 1mV (by a precircuit) When FSR = 5V (2.5V). Figure 8 shows an application circuit for summing the offset at both L/R channels. Alternately, Figure 9 shows an application circuit for use when fs = 48kHz which changes the external integrator circuit of the PCM1760. MODULATOR COMPONENTS AND SAMPLING FREQUENCY The PCM1760/DF1760 are capable to 30kHz to 50kHz fs sampling frequency by condition with external components value which are shown in Basic Connection Diagram. The characteristics of the modulator's integrator can be set by external components. The values in the block diagram on page five are recommended for optimized performance. Low leakage, low voltage coefficient capacitors are recommended for integration capacitors. The tolerance of external components should be better than 2%.
C1
RIN1-L 2.2k VIL = -20mV 10%
11
PCM1760
RIN1-R 2.2k VIR = +10mV 10%
4
FIGURE 8. Application Example to Eliminate the Tone (offset voltage implementation for both channels). OFFSET ERROR CALIBRATION The offset voltage of the PCM1760 and the input stage of the system can be compensated by using the calibration mode of the DF1760. Offset calibration is shown in Figure 10. An optional analog switch is driven by a CAL output of the DF1760. The PD input of the DF1760 is used to initiate the calibration cycle. ANALOG INPUT AND DIGITAL OUTPUT Ideal output digital code range for 20-bit resolution is from 8000H (-Full Scale) to 7FFFFH (+Full Scale). The DF1760, combined with 70000H (FSR) of the PCM1760, produces a digital output code range at FSR input of 90000H (-FSR). The relationship between analog input and digital output is shown in Table I.
C2
C3
C4
RT1 RIN1 11 RIN1 = 2.2k RT2 = 2.2k C1, C2, C3, C4 = 1200pF RT1 = 470 RZ1 = 470 CZ1 = 220pF RIN2 = 1.3k RZ2 = 910
RZ1
CZ1 RIN2 12 13
RT2
RZ2
14
OP1
PCM1760
OP2
FIGURE 9. Application Example to Eliminate the Tone (alternative modulator's integrator circuit. Only for fs = 48kHz).
(R)
11
PCM1760P/U DF1760P/U
ANALOG INPUT +2.55V +2.50V to +2.55V +2.50V 0V -2.50V -2.83V to -2.85V -2.85V
CONDITION +Max Input Overflow +FSR BPZ (Ideal) -FSR Overflow -Max Input
DIGITAL OUTPUT 72000H 70000H to 72000H(2) 70000H 00000H (1) 90000H 82FFFH to 82000H(2) 82000H
NOTES: (1) Incase of BPZ Error = 0. (2) Overflow detection level is over 70000H or under 82FFFH of digital output code.
TABLE I. Output Codes. POWER SUPPLY SEQUENCING The PCM1760 requires VCC and VDD power supplies. To avoid any possibility of latch-up, the VCC and VDD power should all be applied simultaneously or the +VCC and +VDD applied first followed by -VCC and -VDD.
POWER-ON RESET AND MODE RESET The timing requirements for POWER-ON RESET and MODE RESET are shown in Figure 3f. The DF1760 requires POWER-ON RESET when power is applied or restored. MODE RESET is required when any of the following has been changed: system clock, master/slave mode, output data format, L/R clock, calibration after POWER-ON in slave mode. This reset should be done by holding the /PD input (pin 21) low for more than 2/fs. Suggested reset circuits are given in Figures 11, 12 and 13. CLOCK INPUT After power is applied to the DF1760, the system clock should be provided continuously. The DF1760 employs a dynamic logic architecture.
Analog Input VOS VOS PCM1760 DF1760 CAL PD
ANALOG INPUT +fs +fs VOS
ANALOG INPUT
Digital Output
BPZ
Digital Output
-fs 0V +fs
BPZ
-fs
-fs -fs 0V +fs
FIGURE 10. Illustration of Offset Calibration.
(R)
PCM1760P/U DF1760P/U
12
Power-On Reset Circuit VDD 10k /PDIN(1) /PDIN VDD 15 1588 + /PDOUT
DF1760P/U S/M /PD SDATA L/R SCLK SDATA L/R SCLK
10k
47F
NOTE: (1) External /PD input: Time "L" > 2/fs.
FIGURE 11. Master Mode Reset Circuit.
Power-On Reset Circuit DF1760P/U VDD 10k D CLK PR Q Q 74HC74 L/R VDD S/M /PDOUT /PD LRSC SDATA CL 15 1588 + 10k L/R SCLK VDD SDATA L/R SCLK VDD
/PDIN(1)
/PDIN VDD
47F
NOTE: (1) External /PD input: Time "L" > 2/fs.
FIGURE 12. Slave Mode Reset Circuit, (LRSC = H).
Power-On Reset Circuit DF1760P/U VDD 10k D CLK PR Q Q 74HC74 L/R VDD S/M /PD /PDOUT LRSC SDATA CL 15 1588 + 10k L/R SCLK SDATA L/R SCLK VDD
/PDIN(1)
/PDIN VDD
47F
NOTE: (1) External /PD input: Time "L" > 2/fs.
FIGURE 13. Slave Mode Reset Circuit, (LRSC = L).
(R)
13
PCM1760P/U DF1760P/U
TIMING CHARACTERISTICS
256fs
D3 D2 D1 D0 LRCK
Lch
Rch
Lch
Rch
Lch
Rch
Lch
Rch
STROBE
FIGURE 14. Input and Output Format of the DF1760 and PCM1760.
L/R (I)
SCLK (I)
FSYNC (I)
SDATA (O)
M
LM
L
FIGURE 15a. Slave Mode and SCLK = 32fs. (Output format of the DF1760).
L/R (I)
SCLK (I) FSYNC (I) * MSB First 20-Bit (1) SDATA (O) M L M L M
* MSB First 20-Bit (2) SDATA (O) * MSB First 16-Bit SDATA (O)
M
L
M
L
M
L
M
L
* LSB First 20-Bit SDATA (O)
L
M
L
M
FIGURE 15b. Slave Mode and SCLK = 48fs.
(R)
PCM1760P/U DF1760P/U
14
L/R (1) SCLK (1) FSYNC (1) * MSB First 20-Bit (1) SDATA (0)
* MSB First 20-Bit (2) SDATA (0)
* MSB First 16-Bit SDATA (0)
* LSB First 20-Bit SDATA (0)
FIGURE 15c. Slave Mode and SCLK = 64fs.
L/R (0) SCLK (0)
* MSB First 20 Bit (1) FSYNC (0) SDATA (0)
* MSB First 20 Bit (2) FSYNC (0) SDATA (0)
* MSB First 16 Bit FSYNC (0) SDATA (0)
* LSB First 20 Bit FSYNC (0) SDATA (0)
FIGURE 15d. Master Mode.
(R)
15
PCM1760P/U DF1760P/U
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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