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Preliminary Data Sheet
V340HPC A0 High Integration PCI System Controller
******
for 64-bit MIPS(R) Processors
1.1 About the V340HPC
* Highly scalable, 64-bit PCI system controller for high performance embedded systems * Glueless interface to MIPS R4000/R5000/R7000 family members with a 64-bit SysAD bus width, up to 100 MHz * Support for QED, NEC, IDT, Sandcraft, and other 64-bit MIPS-based processors * Local bus clock speeds: 100 MHz, 83 MHz, and 75 MHz--all with external cache support * Multiple outstanding reads with out-of-order return support for the RM7000TM processor * Flexible operation supports either a single 64-bit, 66 MHz PCI bus or dual 32-bit, 66 MHZ buses * Integrated non-transparent PCI-to-PCI bridge * 8 kB internal SRAM scratchpad for immediate access from the local processor * Support for 32-bit and 64-bit PCI, up to 66 MHz * Configurable for system host, bus master, and target operation * PCI-to-local and local-to-PCI address translation * Three PCI-to-local and three local-to-PCI data transfer apertures * 6 kByte FIFO storage * Integrated SDRAM controller * Support for up to 2 Gbyte of SDRAM with optional ECC protection * Support for discrete SDRAMs, standard DIMM(s), registered DIMM(s), and serial presence detect * Support for 16 Mbit-256 Mbit SDRAMs * 4-, 8-, 16-, or 32-bit devices * Integrated multi-channel prefetch buffers * Four independent DMA channels with chaining, multiprocessor support, and fly-by DMA support * Up to 2 kByte burst access on both local and PCI interfaces
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Preliminary Data Sheet
* * * * * * * * * * * * On-the-fly byte order (endian) conversion with automatic byte swapping Programmable chip select/peripheral device strobe generation I2O-ReadyTM ATU and messaging unit Interrupt controller with four configurable interrupt pins Four 32-bit general purpose timers 8-bit watchdog timer System heartbeat and bus watch timers UART serial interface 3.3 V operation with 5 V tolerant input 456-pin BGA (Ball Grid Array) package Tri-directional mailbox registers with doorbell interrupts Power-on configuration via serial EEPROM
A block diagram illustrating a sample application using the V340HPC is shown in Figure 1-1.
NOTE V3 Semiconductor retains the rights to change documentation, specifications, or
device functionality at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design.
Cache
MIPS Processor
SDRAM
PCI Network Device
Flash
PCI Network Device
PCIA V340HPC PCIB PCI Card Slot
Muti-Function I/O
Figure 1-1: Example Application
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(c) 2001 V3 Semiconductor Inc.
Preliminary Data Sheet
1.2 Product Codes
Table 1: Product Codes Order Number
V340HPC-100BPA0 V340HPC-83BPA0 V340HPC-75BPA0
Package
456-pin BGA (Ball Grid Array) 456-pin BGA (Ball Grid Array) 456-pin BGA (Ball Grid Array)
Local Bus Frequency
100 MHz 83 MHz 75 MHz
1.3 Revision History
Table 2: Revision History Revision Number
1.00
Date
Jan. 2001
Comments and Changes
Preliminary presilicon revision of data sheet.
Data Sheet DS-HC01-0100
V340HPC A0 High Integration PCI System Controller
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Preliminary Data Sheet
1.4 Signal Descriptions and Pinouts
Table 3 lists the pin types found on the V340HPC. Table 4 describes the function of all pins except for the PCI pins. Table 5 describes the function of the PCI pins when the V340HPC is configured in 64-bit mode (PCIMODE = 1). Table 6 describes the function of the PCI pins when the V340HPC is configured in 32-bit splitbus mode (PCIMODE = 0).
Table 3: Pin Types Pin Type
PCI I PCI O PCI I/O PCI I/OD I/O4 I/O8 I/O12 I O4 O8 O10 O12
Description
PCI input only PCI output only PCI tri-state I/O PCI input with open drain output I/O pin with 4 mA output drive I/O pin with 8 mA output drive I/O pin with 12 mA output drive input only output pin with 4 mA output drive output pin with 8 mA output drive output pin with 10 mA output drive output pin with 12 mA output drive
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(c) 2001 V3 Semiconductor Inc.
Preliminary Data Sheet
Table 4: Signal Descriptions: All except for PCI pins Signal Type Reset State Description
MIPS System Bus Interface Signals
SYSAD[63:0] SYSCMD[8:0] RELEASE WRRDY VALIDIN VALIDOUT PRQST PACK RSPSWAP TCDOE TCTCE TCWORD[1:0] TCMATCH LCLK LRST COLDRST WARMRST VCCOK O8 O8 I O8 O8 I I O8 O8 O8 O8 O8 O8 I I O12 O12 O8 Z Z Z Z Z Z Z Z Z Z System Address/Data Bus System Command/Data Identifier Bus Release to signal the processor is releasing the bus to slave Write Ready to signal HPC can accept a processor request Valid In indicates HPC is driving valid data on SYSAD and SYSCMD Valid Out indicates the processor is driving valid address/data on SYSAD and SYSCMD bus Processor Request for requesting control of system interface Processor Acknowledge indicates HPC returns control of system interface back to processor Response Swap HPC returns data to processor out of order Tertiary Cache Data RAM Output Enable Tertiary Cache Tag RAM Chip Enable Tertiary Cache Double Word Index Tertiary Cache Tag Match Local Clock Local Reset Cold Reset Warm Reset VCC is OK
Peripheral Bus Interface Signals
ALE IOW IOR IOC[13:0] O8 O8 O8 I/O8 Z Z Z Z Address Latch Enable IO Write IO Read IO Control
SDRAM Interface Signals
MDATA[63:0] MDQM[7:0] MDECC[7:0] RAS I/O8 O10 I/O8 O12 Z Z Z Z Data Data Mask Error Correcting Control Row Address Strobe
Data Sheet DS-HC01-0100
V340HPC A0 High Integration PCI System Controller
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Preliminary Data Sheet
Table 4: Signal Descriptions: All except for PCI pins Signal
CAS MWE MCS[3:0] MA[14:0]
Type
O12 O12 O12 O12
Reset State
Z Z Z Z Column Address Strobe Write Enable Chip Selects Address
Description
JTAG Interface Signals
TCK TRST TDI TMS TDO I I I I O4 Z JTAG Clock Input JTAG reset JTAG Data In JTAG Mode Select JTAG Data Out
Serial EEPROM Interface Signals
SCL SDA O4 I/O4 X X EEPROM Clock EEPROM Data
Configuration Signal
PCIMODE CFN RDIR I I I PCIMODE: tie high for 64-bit PCI bus, tie low for two 32-bit PCI buses
Central Function: indicates whether HPC is the PCIA arbiter and whether it drives REQ64 during reset in 64-bit mode Reset Direction: tie low to drive PRST out and LRST in; tie high to drive LRST out and PRST in.
Power and Ground Signals
VCC V25 GND -- -- -- Power leads for external connection to a 3.3 V power board plane. Power leads for external connection to a 2.5 V power board plane. Ground leads for external connection to a ground board plane.
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(c) 2001 V3 Semiconductor Inc.
Preliminary Data Sheet
Table 5: Signal Descriptions: PCI pins in 64-bit mode Signal Type Reset State Description PCI Bus Interface Signals
ADA[31:0] CBENA[3:0] PARA FRAMEA IRDYA TRDYA STOPA PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O Z Z Z Z Z Z Z Lower Address and Data multiplexed on the same pins. Lower Bus Command and Byte Enables multiplexed on the same pins. Lower Parity represents even parity across ADA[31:0] and CBENA[3:0]. Cycle Frame indicates the beginning and burst length of an access. Initiator Ready indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. Target Ready indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. Stop indicates that the current target is requesting the master to stop the current transaction (retry or disconnect). Device Select, when actively driven by a target, indicates the driving device has decoded its address as the target of the current access. As an input to the initiator, it indicates whether any device on the bus has been selected. Initialization Device Select is used as a chip select during configuration read and write transactions. It must be driven high in order to access the chip's internal configuration space. Z Request indicates to the arbiter that this agent requests use of the bus. Grant indicates to the agent that access to the bus has been granted. PCI Clock provides timing for all transactions on the PCI bus. Z/L PCI Reset acts as an input when RDIR is high, an output when RDIR is low. As an input it is asserted low to bring all internal HPC operation to a reset state. Parity Error is used to report data parity errors during all PCI transactions except a Special Cycle. System Error is used to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. Power Management Event signals request for change in PM state. Interrupt is used to receive or generate level-sensitive interrupt requests.
DEVSELA
PCI I/O
Z
IDSELA REQA GNTA PCLKA PRSTA
PCI I PCI I/O PCI I/O PCI I PCI I/O
PERRA
PCI I/O
Z
SERRA PMEA INT[A:D]
PCI I/OD PCI I/OD PCI I/OD
Z Z Z
PCI 64-bit Extension Signals
ADB[31:0] PCI I/O Z Upper 32-bit Data/Address
Data Sheet DS-HC01-0100
V340HPC A0 High Integration PCI System Controller
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Preliminary Data Sheet
Table 5: Signal Descriptions: PCI pins in 64-bit mode Signal
CBENB[3:0] PARB FRAMEB DEVSELB STOPB
Type
PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O
Reset State
Z Z Z Z Z Upper 4-bit Byte Enables
Description
Upper Parity represents even parity for ADB[31:0] and CBENB[3:0]. Request 64-bit Transfer Acknowledge 64-bit Transfer 64EN as defined in the CompactPCI Hot Swap Specification.
Table 6: Signal Descriptions: PCI Pins in 32-bit Split Bus Mode Signal Type Reset State Description PCIA Bus Interface Signals
ADA[31:0] CBENA[3:0] PARA FRAMEA IRDYA TRDYA STOPA PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O Z Z Z Z Z Z Z Address and Data multiplexed on the same pins. Bus Command and Byte Enables multiplexed on the same pins. Parity represents even parity across ADA[31:0] and CBENA[3:0]. Cycle Frame indicates the beginning and burst length of an access. Initiator Ready indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. Target Ready indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. Stop indicates that the current target is requesting the master to stop the current transaction (retry or disconnect). Device Select, when actively driven by a target, indicates the driving device has decoded its address as the target of the current access. As an input to the initiator, it indicates whether any device on the bus has been selected. Initialization Device Select is used as a chip select during configuration read and write transactions. It must be driven high in order to access the chip's internal configuration space. Z Z Request indicates to the arbiter that this agent requests use of the bus. Grant indicates to the agent that access to the bus has been granted. PCI Clock provides timing for all transactions on the PCI A bus. Z/L PCI Reset acts as an input when RDIR is high, an output when RDIR is low. As an input, it is asserted low to bring all internal HPC operations to a reset state.
DEVSELA
PCI I/O
Z
IDSELA REQA GNTA PCLKA PRSTA
PCI I PCI I/O PCI I/O PCI I PCI I/O
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(c) 2001 V3 Semiconductor Inc.
Preliminary Data Sheet
Table 6: Signal Descriptions: PCI Pins in 32-bit Split Bus Mode Signal
PERRA
Type
PCI I/O
Reset State
Z
Description
Parity Error is used to report data parity errors during all PCI transactions except a Special Cycle. System Error is used to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. Power Management Event signals a request for change in PM state. Interrupt is used to receive or generate level-sensitive interrupt requests.These pins are not dedicated and can be used on either PCI bus (A or B).
SERRA PMEA INT[A:D]
PCI I/OD PCI I/OD PCI I/OD
Z Z Z
PCIB Bus Interface Signals
ADB[31:0] CBENB[3:0] PARB FRAMEB IRDYB TRDYB STOPB PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O Z Z Z Z Z Z Z Address and Data multiplexed on the same pins. Bus Command and Byte Enables multiplexed on the same pins. Parity represents even parity across ADB[31:0] and CBENB[3:0]. Cycle Frame indicates the beginning and burst length of an access. Initiator Ready indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. Target Ready indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. Stop indicates that the current target is requesting the master to stop the current transaction (retry or disconnect). Device Select, when actively driven by a target, indicates the driving device has decoded its address as the target of the current access. As an input to the initiator, it indicates whether any device on the bus has been selected. Request indicates to the arbiter that this agent requests the use of the bus. Grant indicates to the agent that access to the bus has been granted. PCI Clock provides timing for all transactions on the PCI B bus. Z/L PCI Reset acts as an input when RDIR is high, an output when RDIR is low. As an input, it is asserted low to bring all internal HPC operations to a reset state. Parity Error is used to report data parity errors during all PCI transactions except a Special Cycle. System Error is used to report address parity errors, data parity errors on the Special Cycle command, or any other system error that would have catastrophic results.
DEVSELB
PCI I/O
Z
REQB GNTB PCLKB PRSTB
PCI I/O PCI I/O PCI I PCI I/O
Z
PERRB
PCI I/O
Z
SERRB
PCI I/OD
Z
Data Sheet DS-HC01-0100
V340HPC A0 High Integration PCI System Controller
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Preliminary Data Sheet
1.5 Pin Assignments
Figure 1-2 and Table 7 describe the pin assignments for the V340HPC, revision A0.
1 A
SYSAD[16] SYSAD[50] SYSAD[24] SYSAD[59] SYSAD[58] SYSAD[27] SYSAD[21] SYSAD[5] SYSAD[49] SYSAD[56] SYSAD[23] VCCOK IOW IOC[5] IOC[8] IOC[12] LCLK VDDAP MDATA[62] MDATA[31] MDATA[58] MDQM[3] MDATA[57] MA[11] MDATA[24] MDQM[6]
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 A B
B
SYSAD[28] SYSAD[3] SYSAD[54] SYSAD[62] SYSAD[61] SYSAD[48] SYSAD[20] SYSAD[18] SYSAD[22] SYSAD[55] SYSAD[57] IOR IOC[2] ALE IOC[9] IOC[13] CFNB VSSAP MDATA[30] MDATA[61] MDATA[27] MDQM[25] MDATA[56] MDQM[7] MA[10] MA[14]
C
SYSAD[30] TCDOE SYSAD[0] SYSAD[1] SYSAD[31] SYSAD[29] SYSAD[51] SYSAD[52] SYSAD[19] SCL LRST SDA IOC[1] IOC[0] IOC[4] IOC[7] PCIMODE VBBP VDDDP MDATA[63] MDATA[60] MDATA[28] MDATA[26] GROUND MDQM[2] MCS[3]
C D
SYSAD[63] SYSCMD[4] SYSAD[2] SYSAD[33] SYSCMD[6] SYSAD[60] SYSAD[17] SYSAD[53] SYSAD[25] SYSAD[26] GROUND WARMRST COLDRST IOC[6] IOC[3] IOC[11] IOC[10] N/C VSSDP GROUND MDATA[29] MDATA[59] GROUND MA[9] MA[8] MA[7]
D E
SYSAD[32] SYSCMD[1] TCTCE SYSCMD[7] VCC VCC V25 (2.5 V) GROUND VCC VCC GROUND V25 (2.5 V) VCC VCC V25 (2.5 V) GROUND VCC VCC V25 (2.5 V) GROUND VCC GROUND MA[6] MDATA[55] MDATA[23] MDATA[54]
E F
SYSAD[34] TCWORD[1] SYSCMD[8] SYSCMD[2] VCC VCC MDECC[7] MDATA[22] MDATA[53] MDATA[21]
F G
SYSAD[35] SYSCMD[5] SYSCMD[3] TCWORD[0] V25 (2.5 V) V25 (2.5 V) MDATA[18] MDATA[52] MDATA[20] MDECC[3]
G H
SYSCMD[0] SYSAD[43] VALIDOUT RELEASE GROUND GROUND MDECC[6] MCS[2] MDATA[50] MDATA[51]
H J
SYSAD[14] VALIDIN TCMATCH SYSAD[6] VCC VCC MCAS MDATA[19] MDATA[49] MDECC[2]
J K
SYSAD[12] SYSAD[38] PACK WRRDY VCC
K 11 L
SYSAD[10] SYSAD[47] SYSAD[36] SYSAD[4] V25 (2.5 V) GROUND GROUND GROUND GROUND GROUND GROUND V25 (2.5 V) MDATA[16] MRAS MDATA[47] MWE
12
13
14
15
16
VCC
MCS[0]
MCS[1]
MDATA[48]
MDATA[17]
L M
SYSAD[46] SYSAD[15] PRQST SYSAD[41] GROUND
L M
GROUND GROUND GROUND GROUND GROUND GROUND GROUND MDATA[14] MDATA[45] MA[13] MA[12]
M N
RSPSWAP SYSAD[45] SYSAD[11] SYSAD[13] VCC GROUND GROUND GROUND GROUND GROUND GROUND VCC MDATA[46] MDATA[12] MDATA[43] MDATA[13]
N P
RDIR SYSAD[39] SYSAD[40] SYSAD[7] VCC
N P
GROUND GROUND GROUND GROUND GROUND GROUND VCC MDATA[10] MDATA[15] MDATA[11] MDATA[44]
P R
SYSAD[8] INTB SYSAD[44] SYSAD[42] V25 (2.5 V) GROUND GROUND GROUND GROUND GROUND GROUND V25 (2.5 V) MDATA[9] MDATA[42] MDATA[40] MDATA[8]
R T
SYSAD[37] INTD SYSAD[9] INTC GROUND
R T
GROUND GROUND GROUND GROUND GROUND GROUND GROUND MA[1] MDATA[41] MA[2] MA[4]
T
U
REQA PMEA GNTA INTA VCC VCC MA[5] MA[3] MA[0] MDQM[5]
U V
ADA[30] ADA[29] ADA[28] PRSTA VCC VCC MDQM[4] MDQM[0] MDATA[39] MDQM[1]
V W
ADA[25] VIOA[0] ADA[24] ADA[31] V25 (2.5 V) V25 (2.5 V) MDATA[38] MDATA[6] MDATA[37] MDATA[7]
W Y
IDSELA ADA[23] ADA[27] ADA[26] GROUND GROUND MDECC[0] MDATA[5] MDATA[36] MDECC[1]
Y AA
CBENA[3] ADA[22] ADA[21] ADA[20] VCC VCC MDATA[4] MDATA[35] MDATA[3] MDECC[4]
AA AB
FRAMEA ADA[19] ADA[18] ADA[17] GROUND VCC GROUND V25 (2.5 V) VCC VCC GROUND V25 (2.5 V) VCC VCC V25 (2.5 V) GROUND VCC VCC V25 (2.5 V) GROUND VCC VCC MDATA[2] MDATA[33] MDATA[32] MDATA[0]
AB AC
STOPA DEVSELA CBENA[2] GROUND GROUND VIOA[2] GROUND ADA[5] ADA[3] GROUND GROUND REQB ADB[30] GROUND TRDYB GROUND ADB[23] GROUND ADB[18] ADB[14] GROUND ADB[7] TDI MDATA[34] MDATA[1] MDECC[5]
AC AD
IRDYA VIOA[1] GROUND ADA[11] ADA[14] ADA[10] VSSAO ADA[4] ADA[2] GNTB CBENB[2] ADB[29] IRDYB DEVSELB STOPB ADB[26] PARB ADB[21] ADB[17] ADB[13] ADB[10] VIOB[2] ADB[4] GROUND TDO TMS
AD AE
ADA[16] PARA CBENA[0] TRDYA ADA[13] ADA[9] VBBO ADA[7] ADA[1] PCLKB CBENB[3] ADB[31] FRAMEB PERRB ADB[28] ADB[25] ADB[22] ADB[20] ADB[16] ADB[12] ADB[9] ADB[6] ADB[3] ADB[1] GROUND TCK
AE AF
CBENA[1] ADA[15] PERRA SERRA ADA[12] ADA[8] VDDAO ADA[6] ADA[0] PCLKA CBENB[1] CBENB[0] VIOB[0] SERRB ADB[27] ADB[24] VIOB[1] ADB[19] ADB[15] ADB[11] ADB[8] ADB[5] ADB[2] ADB[0] PRSTB TRSTB
AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 1-2: V340HPC Pinouts
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(c) 2001 V3 Semiconductor Inc.
Preliminary Data Sheet
Table 7: V340HPC Pin Assignments
PIN #
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2
Signal
SYSAD[16] SYSAD[50] SYSAD[24] SYSAD[59] SYSAD[58] SYSAD[27] SYSAD[21] SYSAD[5] SYSAD[49] SYSAD[56] SYSAD[23] VCCOK IOW IOC[5] IOC[8] IOC[12] LCLK VDDAP MDATA[62] MDATA[31] MDATA[58] MDQM[3] MDATA[57] MA[11] MDATA[24] MDQM[6] SYSAD[28] SYSAD[3] SYSAD[54] SYSAD[62] SYSAD[61] SYSAD[48] SYSAD[20] SYSAD[18] SYSAD[22] SYSAD[55] SYSAD[57] IOR IOC[2] ALE IOC[9] IOC[13] CFNB VSSAP MDATA[30] MDATA[61] MDATA[27] MDATA[25] MDATA[56] MDQM[7] MA[10] MA[14] SYSAD[30] TCDOE
PIN #
C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4
Signal
SYSAD[0] SYSAD[1] SYSAD[31] SYSAD[29] SYSAD[51] SYSAD[52] SYSAD[19] SCL LRST SDA IOC[1] IOC[0] IOC[4] IOC[7] PCIMODE VBBP VDDDP MDATA[63] MDATA[60] MDATA[28] MDATA[26] GROUND MDQM[2] MCS[3] SYSAD[63] SYSCMD[4] SYSAD[2] SYSAD[33] SYSCMD[6] SYSAD[60] SYSAD[17] SYSAD[53] SYSAD[25] SYSAD[26] GROUND WARMRST COLDRST IOC[6] IOC[3] IOC[11] IOC[10] N/C VSSDP GROUND MDATA[29] MDATA[59] GROUND MA[9] MA[8] MA[7] SYSAD[32] SYSCMD[1] TCTCE SYSCMD[7]
PIN #
E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 J1 J2
Signal
VCC VCC V25 (2.5 V) GROUND VCC
VCC
PIN #
J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M11 M12 M13 M14 M15 M16 M22 M23 M24 M25 M26 N1 N2 N3 N4
Signal
TCMATCH SYSAD[6] VCC VCC MCAS MDATA[19] MDATA[49] MDECC[2] SYSAD[12] SYSAD[38] PACK WRRDY VCC VCC MCS[0] MCS[1] MDATA[48] MDATA[17] SYSAD[10] SYSAD[47] SYSAD[36] SYSAD[4] V25 (2.5 V) GROUND GROUND GROUND GROUND GROUND GROUND V25 (2.5 V) MDATA[16] MRAS MDATA[47] MWE SYSAD[46] SYSAD[15] PRQST SYSAD[41] GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND MDATA[14] MDATA[45] MA[13] MA[12] RSPSWAP SYSAD[45] SYSAD[11] SYSAD[13]
PIN #
N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 P12 P13 P14 P15 P16 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15
Signal
VCC GROUND GROUND GROUND GROUND GROUND GROUND VCC MDATA[46] MDATA[12] MDATA[43] MDATA[13] RDIR SYSAD[39] SYSAD[40] SYSAD[7] VCC GROUND GROUND GROUND GROUND GROUND GROUND VCC MDATA[10] MDATA[15] MDATA[11] MDATA[44] SYSAD[8] INTB SYSAD[44] SYSAD[42] V25 (2.5 V) GROUND GROUND GROUND GROUND GROUND GROUND V25 (2.5 V) MDATA[9] MDATA[42] MDATA[40] MDATA[8] SYSAD[37] INTD SYSAD[9] INTC GROUND GROUND GROUND GROUND GROUND GROUND
PIN #
T16 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24
Signal
GROUND GROUND MA[1] MDATA[41] MA[2] MA[4] REQA PMEA GNTA INTA VCC VCC MA[5] MA[3] MA[0] MDQM[5] ADA[30] ADA[29] ADA[28] PRSTA VCC VCC MDQM[4] MDQM[0] MDATA[39] MDQM[1] ADA[25] VIOA[0] ADA[24] ADA[31] V25 (2.5 V) V25 (2.5 V) MDATA[38] MDATA[6] MDATA[37] MDATA[7] IDSELA ADA[23] ADA[27] ADA[26] GROUND GROUND MDECC[0] MDATA[5] MDATA[36] MDECC[1] CBENA[3] ADA[22] ADA[21] ADA[20] VCC VCC MDATA[4] MDATA[35]
GROUND V25 (2.5 V) VCC VCC V25 (2.5 V) GROUND VCC VCC V25 (2.5 V) GROUND VCC GROUND MA[6] MDATA[55] MDATA[23] MDATA[54] SYSAD[34] TCWORD[1] SYSCMD[8] SYSCMD[2] VCC VCC MDECC[7] MDATA[22] MDATA[53] MDATA[21] SYSAD[35] SYSCMD[5] SYSCMD[3] TCWORD[0] V25 (2.5 V) V25 (2.5 V) MDATA[18] MDATA[52] MDATA[20] MDECC[3] SYSCMD[0] SYSAD[43] VALIDOUT RELEASE GROUND GROUND MDECC[6] MCS[2] MDATA[50] MDATA[51] SYSAD[14] VALIDIN
Data Sheet DS-HC01-0100
V340HPC A0 High Integration PCI System Controller
* * * 11 * * *
Preliminary Data Sheet
Table 7: V340HPC Pin Assignments
PIN #
AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20
Signal
MDATA[3] MDECC[4] FRAMEA ADA[19] ADA[18] ADA[17] GROUND VCC GROUND V25 (2.5 V) VCC VCC GROUND V25 (2.5 V) VCC VCC V25 (2.5 V) GROUND VCC VCC V25 (2.5 V) GROUND
PIN #
AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16
Signal
VCC VCC MDATA[2] MDATA[33] MDATA[32] MDATA[0] STOPA DEVSELA CBENA[2] GROUND GROUND VIOA[2] GROUND ADA[5] ADA[3] GROUND GROUND REQB ADB[30] GROUND TRDYB GROUND
PIN #
AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12
Signal
ADB[23] GROUND ADB[18] ADB[14] GROUND ADB[7] TDI MDATA[34] MDATA[1] MDECC[5] IRDYA VIOA[1] GROUND ADA[11] ADA[14] ADA[10] VSSAO ADA[4] ADA[2] GNTB CBENB[2] ADB[29]
PIN #
AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8
Signal
IRDYB DEVSELB STOPB ADB[26] PARB ADB[21] ADB[17] ADB[13] ADB[10] VIOB[2] ADB[4] GROUND TDO TMS ADA[16] PARA CBENA[0] TRDYA ADA[13] ADA[9] VBBO ADA[7]
PIN #
AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4
Signal
ADA[1] PCLKB CBENB[3] ADB[31] FRAMEB PERRB ADB[28] ADB[25] ADB[22] ADB[20] ADB[16] ADB[12] ADB[9] ADB[6] ADB[3] ADB[1] GROUND TCK CBENA[1] ADA[15] PERRA SERRA
PIN #
AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26
Signal
ADA[12] ADA[8] VDDAO ADA[6] ADA[0] PCLKA CBENB[1] CBENB[0] VIOB[0] SERRB ADB[27] ADB[24] VIOB[1] ADB[19] ADB[15] ADB[11] ADB[8] ADB[5] ADB[2] ADB[0] PRSTB TRSTB
* * * 12 * * *
(c) 2001 V3 Semiconductor Inc.
Preliminary Data Sheet
1.6 DC Specifications
The DC specifications for the PCI bus signals reference those given in the PCI Local Bus Specification, Revision 2.2, Section 4.2. For more information on the PCI DC specifications, see the PCI Local Bus Specification.
Table 8: Absolute Maximum Ratings Symbol
VCC VIN TSTG
Parameter
Supply voltage DC input voltage Storage temperature range
Value
3.6
Units
V V C
-0.3 to 5.75 -65 to 150
Table 9: Guaranteed Operating Conditions Symbol
VCC V25 Jmax
Parameter
Supply voltage 3.3 volt
Value
3.0 to 3.6 V340HPC-75BPA0 V340HPC-83BPA0 V340HPC-100BPA0 2.3 to 2.7
Units
V
Supply voltage 2.5 volt
V 2.4 to 2.6 C C/w C/w C
Maximum Junction temperature Junction-to-ambient thermal resistance Junction-to-case thermal resistance Ambient temperature range
125 17.2 11 0 to 70
JA JC
TA
1.6.1 Local Bus DC Specifications
Table 10: Local Bus Signals DC Operating Specifications Symbol
VIL VIH IIL IIH VOL VOH IOZ IOS CIO
Description
Low level input voltage High level input voltage Low level input current High level input current Low level output voltage High level output voltage Tristate output leakage current Output short circuit current Input and output capacitance
Conditions
Min Max Units
1.0 2.1 V V A 10 0.4 2.4 A V V 10 55 4 A mA pF
VIN = GND VIN = VCC
-10
VIN = GND VCC = 3.6 V
-10 -55
Data Sheet DS-HC01-0100
V340HPC A0 High Integration PCI System Controller
* * * 13 * * *
Preliminary Data Sheet
1.6.2 PCI Bus DC Specifications
Table 11: PCI Bus Signals DC Operating Specifications 3.3 V Signaling Symbol
VCC VIH VIL IIL VOH VOL CIN CCLK CIDSEL
5 V Signaling Max
3.6 4.1 0.33 VCC 10 0 < VIN < VCC IOUT = -2 mA 0.1 VCC 10 IOUT = 6 mA
Parameter
Supply Voltage Input high voltagea
Condition
Min
3.0 0.5 VCC
Condition
Min
3.0 1.9 -0.5 -70 2.4
Max
3.6 5.75 0.9 70
Units
V V V A V
Input low voltage Input leakage currentb 0 < VIN < VCC IOUT = -500 A IOUT = 1500 A
-0.5 -10
0.9 VCC
Output high voltage Output low voltage Input pin capacitancec
0.55 10 5 12 8
V pF pF pF
PCLK pin capacitance IDSEL pin capacitanced
5
12 8
a. Custom 5 V tolerant PCI buffers are used in the design. b. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs. c. Absolute maximum pin capacitance for a PCI unit is 10 pF (except for CLK). d. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
* * * 14 * * *
(c) 2001 V3 Semiconductor Inc.
Preliminary Data Sheet
1.7 AC Specifications
The AC specifications for the PCI bus signals match those given in the PCI Local Bus Specification, Revision 2.2, Section 4.2. For more information on the PCI AC specifications, including the V/I curves for 3.3 V signalling, see the PCI Local Bus Specification.
1.7.1 PCI Bus Timings
Table 12: PCI Bus Signals AC Operating Specifications (33 MHz) Symbol Parameter Condition
0 < VOUT 0.3 VCC Switching current high IOH(AC) (Test point) 0.3 VCC < VOUT < 0.9 VCC 0.7 VCC < VOUT < VCC VOUT = 0.7 VCC VCC > VOUT 0.6 VCC Switching current low IOL(AC) (Test point) ICL ICH tR tF Low clamp current High clamp current Unloaded output rise time Unloaded output fall time 0.6 VCC > VOUT > 0.1 VCC 0.18 VCC > VOUT > 0 VOUT = 0.18 VCC 16 VCC 26.7 VOUT Equation D 38 VCC mA mA mA 4 4 V/ns V/ns
Min
Max
Units
mA mA
-12 VCC -17.1 (VCC - VOUT)
Equation C
-32 VCC
mA mA mA
-3 < VIN -1
VCC + 4 > VIN VCC + 1 0.2 VCC - 0.6 VCC load 0.6 VCC - 0.2 VCC load
-25 + (VIN + 1) / 0.015
25 + (VIN - VCC - 1) / 0.015 1 1
Table 13: PCI Bus Signals, AC Operating Specifications (66 MHz) Symbol
IOH(AC,min) IOH(AC,max) IOL(AC, min) IOL(AC, max) ICL ICH tR tF
Parameter
Switching current high, minimum Switching current high, maximum Switching current low, minimum Switching current low, maximum Low clamp current High clamp current Output rise slew rate Output fall slew rate
Condition
VOUT = 0.3 VCC VOUT = 0.7 VCC VOUT = 0.6 VCC VOUT = 0.18 VCC
Min
Max
Units
mA
-12 VCC -32 VCC
16 VCC 38 VCC
mA mA mA mA mA
-3 < VIN -1
VCC + 4 > VIN VCC + 1 0.3 VCC to 0.6 VCC 0.6 VCC to 0.3 VCC
-25 + (VIN + 1) / 0.015
25 + (VIN - VCC - 1) / 0.015 1 1 4 4
V/ns V/ns
Data Sheet DS-HC01-0100
V340HPC A0 High Integration PCI System Controller
* * * 15 * * *
Preliminary Data Sheet
1.7.2 Local Bus Timings
Table 14: Local Bus AC Test Conditions Symbol
VCC V25 VIN COUT
Parameter
Supply voltage, 3.3 volt operation
Limits
3.0 to 3.6 V340HPC-75BPA0 V340HPC-83BPA0 V340HPC-100BPA0 2.3 to 2.7
Units
V
Supply voltage 2.5 volt
V 2.4 to 2.6 V pF
Input low and high voltages Capacitive load on output and I/O pins
0.4 and 2.0 50
Table 15: Capacitive Derating for Output and I/O Pins Output Drive Limit
4 mA 8 mA 10 mA 12 mA
Supply voltage
3.3 volt 3.3 volt 3.3 volt 3.3 volt
Derating
+0.30 ns/pF for loads > 50pF +0.15 ns/pF for loads > 50pF +0.12 ns/pF for loads > 50pF +0.10 ns/pF for loads > 50pF
TC TCH TSU TH TCL
CLOCK INPUT SETUP/HOLD OUTPUT VALID
Tczo VALID TCOV VALID
OUTPUT DRIVE
TCOZ
VALID
OUTPUT FLOAT
Figure 1-3: Clock and Synchronous Signals
* * * 16 * * *
(c) 2001 V3 Semiconductor Inc.
Preliminary Data Sheet
Table 16: Local Bus Timing Parameters for VCC = 3.3 Volts 10%
V340HPC100BPA0 V340HPC83BPA0 V340HPC75BPA0
# Symbol
1 2 3 4 5 6 7 8 9 TC TCH TCL TSU TH TCZO TCOV TCOZ TRST
Description
LCLK period LCLK high time (measured at 1.5 V) LCLK low time (measured at 1.5 V) Synchronous input setup Synchronous input hold LCLK to output drive delay LCLK to output valid delay LCLK to output float delay Reset period when LRST used as input
Units
ns ns ns ns ns ns ns ns ns
Min
10 4 4 2 2
Max
Min
12 5 5 2 2
Max
Min
13.3 6 6 2 2
Max
4 4 0 16 TC 2 0 16 TC
6 5 2 0 16 TC
7 6 2
Table 17: PCI Bus Timing Parameters for VCC = 3.3 Volts 10%
V340HPC100BPA0 V340HPC83BPA0 V340HPC75BPA0
# Symbol
1 2 3 4 5 6 7 8 9 TC TCH TCL TSU TH TCZO TCOV TCOZ TRST
Description
PCLK period PCLK high time (measured at 1.5 V) PCLK low time (measured at 1.5 V) Synchronous input setup to PCLK Synchronous input hold from PCLK PCLK to output to drive delay PCLK to output valid delay PCLK to output float delay Reset period when PRSTA used as input
Units
ns ns ns ns ns ns ns ns ns
Min
15 6 6 3 0
Max
Min
16 6 6 3 0
Max
Min
17 6 6 4 0
Max
7 7 9 16 TC 16 TC
8 8 11 16 TC
9 9 12
Data Sheet DS-HC01-0100
V340HPC A0 High Integration PCI System Controller
* * * 17 * * *
Preliminary Data Sheet
1.7.3 Serial EEPROM Port Timings
The clock for the serial EEPROM interface is derived by dividing the local bus clock. The waveforms generated are shown in Figure 1-4.
tP
START CONDITION
STOP CONDITION
SCL SDA
tS
tH
Figure 1-4: Serial EEPROM Waveforms and Timings
Table 18: Serial EEPROM Waveform and Timing Information Symbol
tP tS tH
Description
Clock Period Setup Time Hold Time
Min
192 + 4 local clocks 48 + 1 local clocks 48 + 1 local clocks
Max
4064 + 4 local clocks 1016 + 1 local clocks 1016 + 1 local clocks
* * * 18 * * *
(c) 2001 V3 Semiconductor Inc.
Preliminary Data Sheet
1.8 Getting Help from V3 Semiconductor
If you need assistance with a technical question, please contact us. E-mail is the quickest and most efficient way to get technical support from V3. The V3 Web site also contains a wealth of technical support information, as well as the most up-to-date technical documents. Visit us on the Web at: http://www.vcubed.com. Corporate Office 250 Consumers Road, Suite 901 Toronto, Ontario, Canada M2J 4V6 Telephone: 1-877-283-7364 (416) 497-8884 Fax: (416) 497-1160 E-mail: V3help@vcubed.com Sales Office 2348G Walsh Avenue Santa Clara, California 95051 USA Telephone: 1-800-488-8410 (408) 988-1050 Fax: (408) 988-2601
(c) 2001 V3 Semiconductor Inc. All rights reserved. The Embedded Intelligence Company(R) is a registered trademark of V3 Semiconductor. All other trademarks are the property of their respective owners. V3 Semiconductor reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. V3 does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a V3 product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights, or other rights, of V3 Semiconductor.
Data Sheet DS-HC01-0100
V340HPC A0 High Integration PCI System Controller
* * * 19 * * *

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