 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MOTOROLA SEMICONDUCTOR PRODUCT INFORMATION Product Brief Order this document by DSP56002P/D DSP56002 DSP56L002 24-bit Digital Signal Processor The DSP56002 and the DSP56L002 are MPU-style general purpose Digital Signal Processors (DSPs), composed of an efficient 24-bit digital signal processor core, program and data memories, various peripherals, and support circuitry. The 56000-Family-compatible DSP core is fed by onchip program RAM, two independent data RAMs, and two data ROMs with sine and A-law and -law tables. The DSP56002/L002 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI), parallel Host Interface (HI), Timer/Event Counter, Phase-Locked Loop (PLL), and On-chip Emulation (OnCETM) port. This combination of features, illustrated in Figure 1, makes the DSP56002/L002 a cost-effective, high-performance solution for high-precision generalpurpose digital signal processing. 1 24-bit Timer / Event Counter 6 Sync. Serial (SSI) or I/O 3 Serial Comm. (SCI) or I/O 15 Host Interface (HI) or I/O Program Memory 512 x 24 RAM 64 x 24 ROM (boot) 16-bit Bus 24-bit Bus X Data Memory 256 x 24 RAM 256 x 24 ROM (A-law / -law) Y Data Memory 256 x 24 RAM 256 x 24 ROM (sine) 24-bit 56000 DSP Core Internal Data Bus Switch OnCETM Port PLL Clock Gen. 7 4 IRQ Address Generation Unit PAB XAB YAB GDB PDB XDB YDB External Address Bus Switch External Data Bus Switch Address 16 Data 24 Interrupt Control Program Decode Controller Program Address Generator Program Control Unit 3 Data ALU 24 x 24 + 56 56-bit MAC Two 56-bit Accumulators Bus Control Control 10 Figure 1 DSP56002/L002 Block Diagram Motorola reserves the right to change or discontinue this product without notice. (c) MOTOROLA INC., 1994 DSP56002/L002 Features Digital Signal Processing Core * Efficient, object code compatible, 24-bit 56000-Family DSP engine -- -- -- -- -- -- -- -- -- -- -- -- -- Up to 33 Million Instructions Per Second (MIPS) - 30.3 ns instruction cycle at 66 MHz Up to 198 Million Operations Per Second (MOPS) at 66 MHz Performs a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks Highly parallel instruction set with unique DSP addressing modes Two 56-bit accumulators including extension byte Parallel 24 x 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) Double precision 48 x 48-bit multiply with 96-bit result in 6 instruction cycles 56-bit Addition/Subtraction in 1 instruction cycle Fractional and integer arithmetic with support for multiprecision arithmetic Hardware support for block-floating point FFT Hardware nested DO loops Zero-overhead fast interrupts (2 instruction cycles) Four 24-bit internal data buses and three 16-bit internal address buses for maximum information transfer on-chip Memory * On-chip Harvard architecture permitting simultaneous accesses to program and two data memories * 512 x 24-bit on-chip program RAM and 64 x 24-bit bootstrap ROM * Two 256 x 24-bit on-chip data RAMs * Two 256 x 24-bit on-chip data ROMs containing sine, A-law and -law tables * External memory expansion with 16-bit address and 24-bit data buses * Bootstrap loading from external data bus, Host Interface, or Serial Communications Interface Peripheral and Support Circuits * Byte-wide Host Interface (HI) with direct memory access support * Synchronous Serial Interface (SSI) to communicate with codecs and synchronous serial devices -- Up to 32 software-selectable time slots in network mode * Serial Communication Interface (SCI) for full-duplex asynchronous communications * 24-bit Timer/Event Counter also generates and measures digital waveforms * On-chip peripheral registers memory mapped in data memory space * Double buffered peripherals MOTOROLA DSP56002/L002 Product Information 1 * Up to 25 general purpose I/O (GPIO) pins * Three external interrupt request pins; one non-maskable * On-Chip Emulation (OnCE) port for unobtrusive, processor speed-independent debugging * Software-programmable, Phase-Locked Loop-based (PLL) frequency synthesizer for the core clock * Power-saving Wait and Stop modes * Fully static, HCMOS design for operating frequencies from 66 MHz or 40 MHz down to DC * 132-pin Ceramic Pin Grid Array (PGA) package; 13 x 13 array * 132-pin Plastic Quad Flat Pack (PQFP) surface-mount package; 24 x 24 x 4 mm * 144-pin Thin Quad Flat Pack (TQFP) surface-mount package; 20 x 20 x 1.4 mm * 3.3 V (DSP56L002) and 5 V (DSP56002) Power supply options The DSP56002 and DSP56L002 are identical except that the DSP56002 operates at 5 volts, while the DSP56L002 operates at 3.3 volts with a resultant reduction in power consumption and the need for fewer batteries in a portable application. Documentation The three documents listed in Table 1 are required for a complete description of the DSP56002/L002 and are necessary to properly design with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, or a Motorola Literature Distribution Center listed on the back page. Table 1 DSP56002/L002 Documentation Topic DSP56000 Family Manual Description Detailed description of the 56000family architecture and the 16-bit core processor and instruction set Detailed description of memory, peripherals, and interfaces Electrical and timing specifications, and pin and package descriptions Order Number DSP56KFAMUM/AD DSP56002 User's Manual DSP56002/L002 Data Sheet DSP56002UM/AD DSP56002/D 2 DSP56002/L002 Product Information MOTOROLA |
Price & Availability of DSP56L002
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |