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| Under development CMOS 8-Bit Microcontroller TMP86CP24 TMP86CP24F The TMP86CP24 is the high-speed, high-performance and low power consumption 8-bit microcomputer, including ROM, RAM, LCD driver, multi-function timer/counter, serial interface (UART, HSIO), a 10-bit AD converter and two clock generators on chip. Product No. TMP86CP24F ROM 48 K 8 bits RAM 2K 8 bits Package P-LQFP80-1212-0.50A EEPROM MCU Emulation Chip TMP86FP24F TMP86C948XB Feautures 8-bit single chip microcomputer TLCS-870/C series Instruction execution time: 0.25 s (at 16 MHz) 122 s (at 32.768 kHz) 132 types and 731 basic instructions 19 interrupt sources (External: 5, Internal: 14) Input/output ports (54 pins) (Out of which 16 pins are also used as SEG pins) 16-bit timer counter: 2 ch Timer, Event counter, Pulse width measurement, External trigger timer, Window, PPG output modes 8-bit timer counter: 2 ch Timer, Event counter, PWM output, Programmable divider output, Capture modes Time base timer Divider output function Watchdog timer Interrupt source/internal reset generate (programmable) TMP86CP24 P-LQFP80-1212-0.50A 000707EBP1 For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. 86CP24-1 2003-04-15 Under development Serial interface UART: 1ch (The function port for UART is also used as SIO function.) SIO: 2ch TMP86CP24 ROM corrective function Four register bank 1 or 2 bytes replace mode Address replace mode 10-bit successive approximation type AD converter Analog input: 8 ch Five key-on wake-up pins LCD driver/controller Built-in voltage booster for LCD driver With display memory (12 bytes) LCD direct drive capability (max 24 seg 4 com) 1/4, 1/3, 1/2duties or static drive are programmably selectable Dual clock operation Single/dual-clock mode Nine power saving operating modes STOP mode: Oscillation stops. Battery/capacitor back-up. Port output hold/High-impedance. CPU stops, and peripherals operate using high-frequency clock of Time-Base-Timer. Release by falling edge of TBTCR TBTCK setting. CPU stops, and peripherals operate using high-frequency clock. Release by interruputs. CPU stops, and peripherals operate using high and low frequency clock. Release by interruputs. CPU stops, and peripherals operate using low-frequency clock of Time-Base-Timer. Release by falling edge of TBTCR TBTCK setting. CPU stops, and peripherals operate using low-frequency clock. Release by interrupts. CPU stops, and peripherals operate using high and low frequency clock. Release by interrupts. SLOW 1, 2 mode: Low power consumption operation using low-frequency clock (32.768 kHz) IDLE 0 mode: IDLE 1 mode: IDLE 2 mode: SLEEP 0 mode: SLEEP 1 mode: SLEEP 2 mode: Wide operating voltage: 1.8 to 3.6V at 8 MHz/32.768 kHz 2.7 to 3.6V at 16 MHz/32.768 kHz 86CP24-2 2003-04-15 Under development Pin Assignments (Top View) P-LQFP80-1212-0.50A TMP86CP24 V3 V2 V1 C1 C0 WAKE VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 (STOP/INT5) P20 (BOOT) P23 (INT0) P00 (INT1) P01 (INT2) P02 (TC2) P03 P04 (RXD/SI1) P05 (TXD/SO1) P06 (SCK1) P07 AVDD VAREF RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (SO2) P10 (SI2) P11 ( SCK2 ) P12 ( PWM5 / PDO5 /TC5) P13 (INT3/TC3) P14 (TC1) P15 P30 P31 P32 P33 P34 P35 P36 P37 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 P97 (SEG8) P96 (SEG9) P95 (SEG10) P94 (SEG11) P93 (SEG12) P92 (SEG13) P91 (SEG14) P90 (SEG15) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P47 (SEG16) P46 (SEG17) P45 (SEG18) P44 (SEG19) P43 (SEG20) P42 (SEG21) P41 (SEG22) P40 (SEG23/STOP4) P53 P52 P51 ( DVO ) P50 ( PPG ) P67 (AIN7/STOP3) P66 (AIN6/STOP2) P65 (AIN5/STOP1) P64 (AIN4/STOP0) P63 (AIN3) P62 (AIN2) P61 (AIN1) P60 (AIN0) Note: BOOT function of P23 is included in only TMP86FP24F. 86CP24-3 2003-04-15 Under development Block Diagram I/O port (segment output) Common outputs COM3 to COM0 Segment outputs SEG7 to SEG0 P97 (SEG8) P47 (SEG16) to to P90 (SEG15) P40 (SEG23) TMP86CP24 I/O port P37 to P30 Power supply VDD VSS LCD driver circuit C0 C1 V1 V2 V3 RESET TEST P9 P4 P3 LCD power supply Address/data bus LCD voltage booster circuit TLCS-870/C CPU System control circuit Standby control circuit (Key-on wake-up) Timing generator Data memory (RAM) Program memory (ROM) Reset input test pin Interrupt Controller Resonator connecting pins Time base timer XIN XOUT High frequency Clock generator Low frequency 16-bit timer/counter TC1 TC2 8-bit timer/counter TC3 TC5 HSIO UART SIO2 SIO1 Watchdog timer Address/data bus P2 P6 P1 P0 P5 10-bit AD converter P23 to P20 AVDD VAREF Analog reference pins P67 (AIN7) P15 to P10 to P60 (AIN0) I/O ports P07 to P00 P53 to P50 I/O Ports 86CP24-4 2003-04-15 Under development Pin Functions Pin Name P07 ( SCK1 ) P06 (TXD, SO1) P05 (RXD, SI1) P04 P03 (TC2) P02 (INT2) P01 (INT1) P00 ( INT0 ) P15 (TC1) P14 (TC3,INT3) P13 ( PWM5 , PDO5 , TC5) P12 ( SCK2 ) P11 (SI2) P10 (SO2) P23 P22 (XTOUT) P21 (XTIN) P20 ( INT5 , STOP ) TMP86CP24 Input/Output I/O (I/O) I/O (Output) I/O (Input) I/O I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (I/O) I/O (I/O) I/O (Input) I/O (Output) I/O I/O (Output) I/O (Input) I/O (Input) Functions 8-bit input/output port with latch. When used as a serial interface output or UART output, respective output latch (P0DR) should be set to "1". When used as an input port, an serial interface input, UART input, timer counter input or an external interrupt input, respective output control (P0OUTCR) should be cleared to "0" after setting P0DR to "1". 6-bit input/output port with latch. When used as a timer/counter output or serial interface output, respective output latch (P1DR) should be set to "1". When used as an input port, a timer counter input, an external interrupt input or serial interface input, respective output control (P1OUTCR) should be cleared to "0" after setting P1DR to "1". Serial clock input/output 1 UART data output, Serial data output 1 UART data input, Serial data input 1 Timer counter 2 input External interrupt 2 input External interrupt 1 input External interrupt 0 input Timer counter 1 input Timer counter 3 input, External interrupt 3 input PWM5 output, PDO5 output, Timer/counter 5 input Serial clock input/output 2 Serial data input 2 Serial data output 2 4-bit input/output port with latch. When used as an input port or an external interrupt input, respective output control (P2OUTCR) should be cleared to "0" after setting output latch (P2DR) to "1". 8-bit input/output port with latch (Nch high current output). When used as an input port, respective output control (P3OUTCR) should be cleared to "0" after setting output latch (P3DR) to "1". 7-bit input/output port with latch. When used as an input port, respective output latch (P4DR) should be set to "1" after LCD output control (P4LCR) is cleared to "0". 1-bit input/output port with latch. When used as an input port, the output latch (P4DR) should be set to "1" after the LCD output control (P4LCR) is cleared to "0". When used as a LCD output, the P4LCR should be set to "1" after the STOPCR Resonator connecting pins (32.768 kHz) For inputting external clock, XTIN is used and XTOUT is opened. External interrupt input 5 or STOP mode release signal input P37 to P30 I/O P47 (SEG16) to P41 (SEG22) I/O (Output) LCD segment output P40 (SEG23, STOP4) I/O (I/O) LCD segment output STOP mode release input P53 P52 P51 ( DVO ) I/O I/O (Output) Divider output P50 ( PPG ) I/O (Output) PPG output 86CP24-5 2003-04-15 Under development TMP86CP24 P67 (AIN7, STOP3) P66 (AIN6, STOP2) P65 (AIN5, STOP1) P64 (AIN4, STOP0) P63 (AIN3) P62 (AIN2) P61 (AIN1) P60 (AIN0) SEG7 to SEG0 COM3 to COM0 V3 to V1 C1 to C0 WAKE I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) 8-bit programmable input/output port (tri-state). Each bit of this port can be individually configured as an input or an output under software control. When used as an input port, respective input/output control (P6CR1) should be cleared to "0" after setting input control (P6CR2) to "1". When used as an analog input or key on wake up input, respective P6CR1 should be cleared to "0" after clearing P6CR2 to "0". When used as a key on wake up input, STOPCR STOP 3 input STOP 2 input STOP 1 input STOP 0 input AD converter analog inputs Output LCD voltage booster pin Output LCD voltage booster pin. Capacitors are required between C0 and C1 pin and V1/V2/V3 pin and GND. STOP mode monitor output. During reset and CPU operation (including IDLE0/1/2, SLEEP0/1/2, warming-up period), it becomes "L" level state. In STOP mode, it becomes the high impedance state. Resonator connecting pins for high-frequency clock. For inputting external clock, XIN is used and XOUT is opened. Reset signal input Test pin for out-going test. Be fixed to low. Power supply for operation XIN, XOUT RESET Input output Input Input TEST VDD, VSS VAREF AVDD Power supply Analog reference voltage for AD conversion AD circuit power supply 86CP24-6 2003-04-15 Under development TMP86CP24 Operational Description 1. CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, the external memory interface, and the reset circuit. 1.1 Memory Address Map The TMP86CP24 memory consists of 4 blocks: ROM, RAM, DBR (Data Buffer Register) and SFR (Special Function Register). They are all mapped in 64-Kbyte address space. Figure 1.1.1 shows the TMP86CP24 memory address map. The general-purpose registers are not assigned to the RAM address space. 0000H SFR 003FH 0040H 64 bytes ROM: Read Only Memory includes: Program memory Vector table RAM: Random Access Memory includes: Data memory Stack SFR: Special Function Register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Interrupt control registers Program Status Word DBR: Data Buffer Register includes: Peripheral control registers Peripheral Status registers LCD display memory RAM 083FH 2048 bytes 1F80H DBR 1FFFH 4000H 128 bytes 49072 bytes ROM FFB0H FFBFH FFC0H FFDFH FFE0H FFFFH 16 bytes 32 bytes 32 bytes TMP86CP24 Vector table for interrupts/reset (8 vectors) Vector table for vector call instructions (16 vectors) Vector table for interrupts/reset (16 vectors) Figure 1.1.1 Memory Address Maps 1.2 Program Memory (ROM) The TMP86CP24 has a 48 K programmed ROM). 8 bits (address 4000H to FFFFH) of program memory (mask 86CP24-7 2003-04-15 Under development Electrical Characteristics Absolute Maximum Ratings Parameter Supply voltage Input voltage Output voltage TMP86CP24 (VSS 0 V) Pins Rating 0.3 to 4.0 0.3 to VDD Except V3 pin V3 pin P0, P1, P20, P23, P3, P5, P6 Ports P0, P1, P2, P4, P6, P9, WAKE Ports P3, P5 Ports P0, P1, P20, P23, P3, P5, P6 Ports P0, P1, P2, P4, P6, P9, WAKE Ports P3, P5 Ports 0.3 to VDD -0.3 to 4.0 2 2 10 80 80 30 350 260 (10 s) 55 to 125 40 to 85 C mW mA 0.3 0.3 V Symbol VDD VIN VOUT1 VOUT2 IOUT1 IOUT2 IOUT3 IOUT1 Unit Output current (Per 1 pin) Output current (Total) Power dissipation [Topr Storage temperature Operating temperature 85C] IOUT2 IOUT3 PD Tsld Tstg Topr Soldering temperature (time) Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. 86CP24-162 2003-04-15 Under development TMP86CP24 Recommended Operating Condition Parameter Symbol (VSS 0 V, Topr 40 to 85C) Condition Min 2.7 1.8 Pins fc fc Max Unit 16 MHz 8 MHz NORMAL1, 2 mode IDLE0, 1, 2 mode NORMAL1, 2 mode IDLE0, 1, 2 mode SLOW1, 2 mode SLEEP0, 1, 2 mode STOP mode Supply voltage VDD 3.6 fs 32.768 kHz VIH1 Input high level VIH2 VIH3 VIL1 Input low level VIL2 VIL3 Clock frequency LCD reference voltage Capacity for LCD booster circuit fc fs V1 V2 CLCD XIN, XOUT XTIN, XTOUT Except Hysteresis input Hysteresis input Except Hysteresis input Hysteresis input 1.8 V VDD VDD VDD 0 0.70 0.75 0.80 VDD VDD VDD 1.0 30.0 0.8 1.6 0.1 0.30 0.25 0.20 MHz kHz V F VDD VDD VDD VDD VDD VDD VDD VDD (V3 (V3 2.7 V 2.7 V 2.7 V 2.7 V 1.8 to 3.6 V 2.7 to 3.6 V 1.8 to 3.6 V VDD) VDD) 8.0 16.0 34.0 1.2 2.4 0.47 Booster circuit is enable LCD booster circuit is enable Note 1: The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. 86CP24-163 2003-04-15 Under development DC Characteristics Parameter Hysteresis voltage TMP86CP24 (VSS 0 V, Topr Pins Hysteresis input TEST 40 to 85C) Condition VDD VDD 3.3 V 3.6 V, VIN 3.6 V, VIN 3.6 V, VIN 3.6 V, VIN 3.6 V, VIN 0V 3.6 V/0 V 3.6 V 3.6 V 0V 100 70 220 T.B.D. VDD VDD VDD VOUT VDD 3.6 V 3.6 V 3.6 V 3.4V / 0.2 V 3.6 V, lOH 3.6 V, IOL 0.6 mA 0.9 mA 6 V1 2 V1 3 V2 1/2 V2 3/2 00 01 10 11 00 01 10 11 Symbol VHS IIN1 Min Typ. 0.4 Max 5 5 +5 Unit V Input current IIN2 IIN4 RIN1 Sink Open Drain, Tri-state VDD RESET A VDD VDD VDD TEST Pull-down RESET Pull-Up Input resistance RIN2 RIN3 P21,P22 Ports Programmable Pull-down (P4, P9 Ports) XOUT XTOUT Sink Open Drain, Tri-state C-MOS, Tri-state 450 k High frequency feedback resister Low frequency feedback resister Output leakage current Output high voltage Output low voltage Output low current LCD output voltage (LCD booster is enable) RFB RFBT ILO VOH VOL IOL V2-3OUT V1-3OUT 1.2 M 14 10 3.2 0.4 V mA A Except XOUT,P3 and P5 VDD Ports P3, P5 Ports V2 pin V3 pin V1 pin V3 pin VDD 3.6 V, VOL 1.0 V V3 VDD Reference supply pin: V1 SEG/COM pin: No-load V3 VDD Reference supply pin: V2 SEG/COM pin: No-load VDD fc 3.6 V 16 MHz V T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. mA T.B.D. T.B.D. T.B.D. A T.B.D. T.B.D. T.B.D. mV/ A LCD output current capacity (LCD booster is enable) CLCD 0.1 F Reference supply pin: ILCDV3 V3 pin V1 VDD fc 1V 3.6 V 16 MHz CLCD 0.1 F Reference supply pin: V2 2V Supply current in NORMAL 1, 2 mode Supply current in IDLE 0, 1, 2 mode Supply current in SLOW 1 mode Supply current in SLEEP 1 mode Supply current in SLEEP 0 mode Supply current in STOP mode IDD VDD VIN fc fs 3.6 V 3.4 V/0.2 V 16 MHz 32.768 kHz VDD VIN fs 3.6 V 3.4 V/0.2 V T.B.D. 32.768 kHz VDD VIN 3.6 V 3.4 V/0.2 V T.B.D. Note 1: Typical values show those at Topr Note 3: IDD does not include IREF current. 25C, VDD 3.3 V Note 2: Input current (IIN1, IIN2); The current through pull-up or pull-down resistor is not included. Note 4: The supply currents of SLOW 2 and SLEEP 2 modes are equivalent to IDLE 0, 1, 2. Note 5: Current capacity indicates the drop in pin V3 output voltage per 1 A. Select an appropriate booster frequency setting in LCDCR 86CP24-164 2003-04-15 Under development AD Conversion Characteristics Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage Non linearity error Zero point error Full scale error Total error TMP86CP24 40 to 85C) Typ. 1.0 VDD V 2.5 VSS VAREF T.B.D. T.B.D. 2 2 2 2 mA (VSS 0.0 V, 2.7 V VDD 3.6 V, Topr Min AVDD Symbol VAREF AVDD VAREF VAIN IREF VDD VSS VDD VSS VAREF Condition Max AVDD Unit AVDD 0.0 V AVDD 0.0 V 2.7 V VAREF 3.6 V 2.7 V LSB (VSS Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage Non linearity error Zero point error Full scale error Total error 0.0 V, 2.0 V VDD 2.7 V, Topr Min AVDD 0.6 40 to 85C) Typ. Max AVDD VDD V Symbol VAREF AVDD VAREF VAIN IREF VDD VSS VDD VSS VAREF Condition Unit 2.0 VSS AVDD 0.0 V AVDD 0.0 V 2.0 V 2.0 V VAREF 2.0V T.B.D. VAREF T.B.D. 4 4 4 4 mA LSB (VSS Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage Non linearity error Zero point error Full scale error Total error 0.0 V, 1.8 V Condition VDD 2.0 V, Topr Min AVDD 0.1 10 to 85C) (Note 5) Typ. Max AVDD VDD V Symbol VAREF AVDD VAREF VAIN IREF VDD VSS VDD VSS VAREF Unit 1.8 VSS AVDD 0.0 V AVDD 0.0 V 1.8 V 1.8 V VAREF 1.8V T.B.D. VAREF T.B.D. 4 4 4 4 mA LSB Note 1: The total error includes all errors except a quantization error, and is defined as a maximum deviation from the ideal conversion line. Note 2: Conversion time is different in recommended value by power supply voltage. About conversion time, please refer to "2.12.2 Register configuration". Note 3: Please use input voltage to AIN input Pin in limit of VAREF VSS. When voltage of range outside is input, conversion value becomes unsettled and gives affect to other channel conversion value. Note 4: Analog Reference Voltage Range: VAREF VAREF VSS Note 5: When AD is used with VDD < 2.0 V, the guaranteed temperature range varies with the operating voltage. Note 6: When AD converter is not used, fix the AVDD pin on the VDD level. 86CP24-165 2003-04-15 Under development AC Characteristics Parameter (VSS 0 V, VDD 2.7 to 3.6 V, Topr Condition NORMAL1, 2 mode Machine cycle time tcy IDLE1, 2 mode SLOW1, 2 mode SLEEP1, 2 mode High level clock pulse width Low level clock pulse width High level clock pulse width Low level clock pulse width twcH twcL twcH twcL For external clock operation (XIN input) fc 16 MHz For external clock operation (XTIN input) fs 32.768 kHz TMP86CP24 40 to 85C) Min 0.25 117.6 Symbol Typ. Max 4 Unit s 133.3 31.25 ns 15.26 s (VSS Parameter 0 V, VDD 1.8 to 3.6 V, Topr Condition 40 to 85C) Min 0.5 117.6 Symbol Typ. Max 4 Unit NORMAL1, 2 mode Machine cycle time tcy IDLE1, 2 mode SLOW1, 2 mode SLEEP1, 2 mode High level clock pulse width Low level clock pulse width High level clock pulse width Low level clock pulse width twcH twcL twcH twcL For external clock operation (XIN input) fc 8 MHz For external clock operation (XTIN input) fs 32.768 kHz s 133.3 62.5 ns 15.26 s Recommended Oscillating Conditions Note 1: An electrical shield by metal shield plate on the surface of IC package is recommended in order to protect the device from the high electric field stress applied from CRT (Cathodic Ray Tube) for continuous reliable operation. Note 2: The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following http://www.murata.co.jp/search/index.html 86CP24-166 2003-04-15 |
Price & Availability of E03041586CP24SUMMARY
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