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TC90A67F
Preliminary
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC90A67F
Single Chip Picture-in-Picture IC (PAL/NTSC)
TC90A67F is a Picture-in-Picture (PIP) IC including a PIP controller and a PAL/NTSC decoder function on a chip. TC90A67F has an ADC, a video decoder, a vertical filter, a field memory, DACs and so on, so that it is easy to design a PIP application with the least external components.
Features
Video Decoder for the Sub-Picture
* * * * * * * * * * * * * * * * * * * NTSC, PAL (Europe), M-PAL and N-PAL systems Automatic color system identification 8-bit ADC for a composite video input Y/C separation by built-in digital filters ACC, Color killer circuits Contrast, Brightness, Tint and Color level controls Accessible V-chip signal data via. IIC bus External PLL circuit for main-picture system clock (A recommended IC TI: TLC2933) 525-60 Hz, 626-50 Hz and mixed are available Vertical filter Field memory (181 kbit) PIP mode: Single PIP with 1/9 or 1/16 size, 6 PIPs with 1/36 size Flexible PIP position 3ch 8-bit DACs for YUV or RGB outputs YUV to RGB converter 42 MHz crystal oscillator I2C bus control Package: QFP80 Power supply: 3.3 V Weight: 1.6 g (typ.)
Main-Picture System Clock PIP Controller
Others
980910EBA1
* TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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Block Diagram
Line Memory
Field Memory
Compsite signal
CVI ADC LPF
Y signal Processing
Vertical Filtering
PIP Control
YUV/RGB
UP SAMPLING
DAC
Yout
Clamp CLMP
BPF
ACC
Chroma Demo
Chroma LPF DAC Rout
fsc PLL
Sync Sepa
fH PLL
DAC
Bout
V.Sync Sepa CCD Slice 42 MHz Oscillator
subtiming Gen maintiming Gen
Ys
IIC BUS
CKP XI XO VCO
PHREF
PHD
PVD
PD HD main VD main
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Terminal Connection Diagram
QFP80-P-1420-0.80B
TESTM2
TESTM1
TESTM0
CKPSEL
RESET
PHREF
VCHIP
PIPEN
VDD
CKILL
PHD
PVD
CKP
SDA
VSS
SCL
VDD
VSS
NC
NC
NC
NC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 TEST2 65 VDD 66 VSS 67 NC 68 NC 69 VREFD 70 BIAS2 71 NC 72 BIAS1 73 NC 74 AVDD 75 BOUT 76 AVSS 77 ROUT 78 AVDD 79 YOUT 80 1 AVSS 2 BIASA 3 VREFH 4 AVSS 5 CVI 6 AVDD 7 VREFL 8 AVSS 9 NC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VREF CKIN BIASD FILTER CKC NC NC NC CKCSEL CKOUT AVDD AVDD CLMP AVSS VSS TC90A67F (QFP80) 40 CHREF 39 CVREF 38 CFIELD 37 PFIELD 36 VDD 35 VSS 34 CSTD 33 NC 32 NC 31 VDD 30 NC 29 XO 28 XI 27 VSS 26 TEST 25 VDD
NC
YS
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Terminal Function
QFP80-P-1420-0.80B
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Name AVSS BIASA VREFH AVSS CVI AVDD VREFL AVSS NC CKOUT AVDD BIASD VREF NC NC AVSS FILTER AVDD CKIN NC VSS CKC CKCSEL CLMP VDD TEST VSS XI XO NC VDD NC NC CSTD VSS VDD PFIELD CFIELD CVREF CHREF NC I/O I O O O I I I O I I O O O O O O Internal signal output Ground for DRAM Power supply for DRAM Field odd/even output (main picture) Field odd/even output (sub picture) Vertical sync. output (sub picture) Horizontal sync. output (sub picture) H: even, L: odd H: even, L: odd Power supply for crystal oscillator Ground for digital circuit Clock input (sub-picture) Internal/external 384fH VCO select Clamp level output Power supply for digital circuit Test pin Ground for crystal oscillator 42 MHz crystal oscillator input 42 MHz crystal oscillator output normal: H L: internal, H: external Ground for VCO VCO filter terminal Power supply for DAC 384fH-clock input 384fH-clock output Power supply for VCO DAC bias voltage Lower limit reference voltage of DAC normal: 1.8 V Ground for DAC ADC bias voltage Upper limit reference voltage of ADC Ground for ADC Composite video signal input Power supply for ADC Lower limit reference voltage of ADC Ground for ADC normal: 1.0 V normal: 2.3 V Function Condition
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PIN 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name CKILL VCHIP RESET VDD SDA SCL NC PIPEN YS NC VSS PVD VDD NC PHREF CKPSEL CKP VSS PHD NC TESTM0 TESTM1 TESTM2 TEST2 VDD VSS NC NC VREFD BIAS2 NC BIAS1 NC AVDD BOUT AVSS ROUT AVDD YOUT I/O O I I I/O I I O O I O O I I I I I I I I O O O Power supply for DAC Analog signal output (B-Y or B) Ground for DAC Analog signal output (R-Y or R) Power supply for DAC Analog signal output (Y or G) DAC bias reference voltage Lower limit reference voltage of DAC DAC bias reference voltage normal: 1.8 V Test pin Test pin Test pin Test pin Power supply for digital circuit Ground for digital circuit normal: H normal: H normal: H normal: H Horizontal sync. output (main picture) CKP frequency selection Clock input (main-picture) Ground for digital circuit Horizontal sync. input (main picture) normal: positive L: 24 MHz, H: 48 MHz Ground for digital circuit Vertical sync. input (main picture) Power supply for digital component normal: negative PIP enable Main, sub-picture switching pulse normal: H sub-picture: high Function Color killer detection output (sub picture) 23rd-line detect signal output Reset input Power supply for digital circuit I2C BUS data input, data and acknowledge output I2C BUS clock input Condition H: color killer ON, L: OFF 23rd-line: H L: reset
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System Block Diagram
Main V/C/J Chroma Demo Main Video Sync Processor YUV Processor RGB Text Processor
H/V
YUV
YUV
PIP Controller
Ys Sub Video Sub V/C/J
TC90A67F
PIP Mode
1 PIP MODE Size: 1/3, 1/4, 1/6
6 PIP MODE 1 Size: 1/6 x 6
6 PIP MODE 2 Size: 1/6 x 6
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Function
TC90A67F has horizontal and vertical sync separation circuit for sub picture, color demodulation circuit for sub picture, horizontal and vertical timing generation circuit for main picture, PIP control circuit. Color demodulation circuit consists of digital circuit, and corresponds to M-NTSC, PAL, M-PAL, N-PAL system. It is possible to process the sub picture easily, according to adopting system clock of 24 MHz by digital PLL circuit locked fH. Horizontal and vertical timing generation circuit uses system clock (24 MHz) generated by analog PLL circuit locked main picture's fH. PIP control circuit consists of filter for horizontal and vertical reduction, line memory, field memory and according to changing horizontal and vertical reduction factors, it is possible to carry out various pip sizes.
1. ADC, Clamping Circuit
Dynamic range of ADC is 1.32 Vp-p whose voltage is fixed in IC. (top voltage is 2.31 V, bottom voltage is 0.99 V) ADC has pedestal clamp function, base voltage is output from CLMP terminal. The pedestal level becomes about 1.32 V. (64LSB)
2. Horizontal and Vertical Sync for Main Picture
It is necessary to input main picture's H-sync and V-sync at PHD and PVD terminal in order to make system clock for readout stored data into the internal field memory. PHD and PVD are fitted to 5 V. It can be inverted the polarity using IICBUS registers WHINV and WNINV at sub address 29hex. At terminals of IC, polarity of H-sync is positive and V-sync is negative. The clocks from external VCO are selectable in 24 MHz and 48 MHz, it can be switched by given voltage to CKPSEL (SDIP: 52 pin, QFP: 57 pin) terminal. (CKPSEL = L: 24 MHz, CKPSEL = H: 48 MHz)
3. The System Clock Locked to the Sub Picture's Horizontal Sync.
The signal converted into the digital environment passes through horizontal sync separation circuit, horizontal locked circuit, which construct PLL circuit, it makes the system clock locked to the sub picture's horizontal sync. This clock is put in internal VCO and generated the system clock of 24 MHz.
4. Horizontal Reduction
It is necessary to limit to frequency bandwidth for Y signal and color difference signal concerning PIP mode. Horizontal reduction is selectable using HWS. (HWS: sub address 10hex)
HWS [1:0] 00 01 10 11
Horizontal Reduction 1/3 1/4 1/6 1/8
Sampling Rate for Y 4 MHz 3 MHz 2 MHz 1.5 MHz
Sampling Rate for Color Difference 1 MHz 0.75 MHz 0.5 MHz 0.375 MHz
In order to horizontal reduction, LPFs are used for Y signal and color difference signal. It is selectable in two kinds of LPF for Y signal and six kinds of LPF for color difference signal.
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5. Vertical Reduction
It is necessary to reduce vertical direction concerning PIP mode, and vertical reduction is carried out from multiplication of coefficient as below. Vertical reduction is selectable using VWS. (VWS: sub address 10hex)
1H Coefficient 1/4 1/8 1/16 1/16 2H Coefficient 1/2 3/8 1/4 3/16 3H Coefficient 1/4 3/8 3/8 1/4 4H Coefficient 1/8 1/4 1/4 5H Coefficient 1/16 3/16 6H Coefficient 1/16
Vertical Reduction 1/3 (VWS [1:0] = 00) 1/4 (VWS [1:0] = 01) 1/5 (VWS [1:0] = 10) 1/6 (VWS [1:0] = 11)
6. The Sub Picture's Area of Writing in the Field Memory and Reading from the Field Memory
Writing start position is defined horizontal start point to write (sub address 16hex: CHS) and vertical start point to write. (sub address 16hex: CVSN or sub address 17hex: CVSP) CVSN: Vertical frequency of sub picture is 60 Hz CVSP: Vertical frequency of sub picture is 50 Hz Horizontal width of the sub picture is defined by sampling number of horizontal direction. (sub address 1Ahex: HSPL) The number of writing vertical lines is determined internally according to vertical frequency of the main picture and VWS. Reading start position is defined horizontal start point to read (sub address 14hex: PHS) and vertical start point to read. (sub address 14hex: PVSN or 15hex: PVSP) PVSN: Vertical frequency of sub picture is 60 Hz PVSP: Vertical frequency of sub picture is 50 Hz Horizontal display size of the sub picture is defined by PHW (sub address 12hex) and the readout number of vertical lines is defined by PVWN (sub address 12hex) or PVWP (sub address 13hex). PVWN: Vertical frequency of sub picture is 60 Hz PVWP: Vertical frequency of sub picture is 50 Hz
7. DACs for Y Signal and Color Difference Signal
TC90A67F is built-in three 8 bit-DAC in motion on 24 MHz. Output dynamic range is determined by the difference between VDD and VREFD terminal voltage. Standard level is 1.5 Vp-p.
8. ACC Control
ACC control is carried out comparing demodulation result of color burst signal with set reference level by ACCPAL or ACCNTSC register. (ACCPAL, ACCNTSC: sub address 21hex) When compared value is less than the reference level, controller puts on gain, and more than reference level, controller cuts down one.
9. Peaking Circuit for Y Signal
It is possible to carry out a clear picture according to putting up some frequency bandwidth when sub picture becomes indistinct picture for reducing high frequency bandwidth using LPF for Y signal. There are two kinds of characteristics for LPF, and it is selectable about gain of four stages respectively using YPKGS and YPKGG. YPKGS: select for LPF characteristics (sub address 10hex) YPKGG: select for gain (sub address 10hex)
10. PGB Matrix Circuit
For a built-in RGB matrix circuit, and when RGBON = 1, it can be changed R-Y, Y, B-Y into RGB signal. How to find the value of coefficient (a, b, c) is as below. < < 1Chex: MTXCR: a, MTXCG2: b, MTXCG1: c (on condition 0 < a < 1, 0 = b < 1, 0 = c < 1) = R = a (R - Y) + Y G = b {-(R - Y)} + c {-(B - Y)} + Y B = (B - Y) + Y
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11. Blue Back Function
It is possible to control blue back function using BBACK resister. (BBACK: sub address 13hex, BBACK = 1: blue back mode) It is available for only sub picture set to live mode. BBACK is useful when detected V chip or no signal. it can be selected in four kinds of colors using BLEVEL. (BLEVEL: sub address 13hex)
12. Addition of Frame
It is possible to add the frame to the sub picture. It is selectable frame width by FRAMEW and adjustable frame color for RGB or R-Y, Y, B-Y respectively by FRAMEYG, FRAMER, FRAMEB. (FRAMEW, FRAMEYG, FRAMER, FRAMEB: sub address 1Ehex)
13. CCD Slice Circuit
This IC has a CCD slice circuit, picks up CCD data, the CCD data and CCD slice conditions can be checked on using IIC BUS read mode.
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Bus Map (the value in parentheses indicate preseted data. the parts of mesh is fixed, input the indicated value.)
Sub Address 00 (READ) 01 (READ) 02 (READ) 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F YSDLYS [1:0] TYDLY [1:0] (0) (0) 0 0 MTXCB [5:0] YGOS [5:0] FRAMEW [1:0] 0 (0) PMDFIX (0) CHLOADN [7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ACCPAL [6:0] KILON [6:0] NTSOFF [6:0] 0 1 0 1 PMDS [1:0] DRAMCLRN (0) 0 1 0 BRTRGB [5:0] 0 0 HSPL [5:0] (32) HUEBIAS [5:0] (31) (00) FRAMEYG [3:0] (0) (0) OFF2527 (0) (FE) SELREV (0) 0 (00) MTXCG [24:20] ROS [4:0] (0C) (00) FRAMER [3:0] 0 (0) 0 CHLOADP [7:0] (3A) (0C) (14) 0 1 0 0 0 FSSTM [1:0] (1) ACCNTSC [6:0] KILOFF [6:0] NTSON [6:0] PIDREF [6:0] FSSEL [1:0] (0) 0 0 CLVL [4:0] HUE [7:0] MTXCG [14:10] BOS [4:0] FRAMEB [3:0] PFLDREV (0) BBACK (0) BLEVEL [1:0] NOSIG 0 0 15 CR13DET CCDATA [15:0] CVMD525 TRAPFIX (0) 0 CNOVPN TRAP358 (0) MF (0) CVDET60 YDLY1 [1:0] BCF [1:0] (1) STRO [3:0] YPKGS (0) PVMD525 YLPFS (0) (0) (31) SELGAIN (0) PHS [7:0] PHC [6:0] CHS [7:0] (00) PHW 0 [2:0] (0) (2B) (00) (19) 1 WADOS [12:0] RADOS [12:0] CTRT [4:0] PNOVPN YPKGG [1:0] TATEON (0) PIPNUM [2:0] PVDET60 CKIL PD UNLOCK CLPF [2:0] (0) RON (0) PALDET VWS [1:0] (0) MSNUM [2:0] HWS [1:0] (0) (04A) (05C) (99) (83) (0A) (112) (0000) (0000) (00) (00) (0A) (00) (0) CFLDREV (0) (F9) RGBON (0) (0) MSON (0) 14 13 CRIN [3:0] 12 11 10 CFIELD 9 SBDET 8 AEDGE 7 BEDGE 6 SLV [6:0] 5 4 3 2 1 0
PHW [6:0] (0)
PVWN [8:0] PVWP [8:0] PVSN [7:0] PVSP [8:0] CVSN [7:0] CVSP [8:0]
20
21 22 23 24 25
(51) (14) (0C) (76) FSMO [1:0] (1)
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Sub Address 26 27 28 29 1 1 1 1 0 0 15 14 13 SSLV [5:0] 0 1 0 0 0 WS262 (0) WVINV (0) 12 11 (20) 0 0 CCDL [3:0] WHINV (0) F60 (0) 0 10 9 8 CCDSBH [4:0] 0 (8) F50 (0) 0 F60 (0) 0 7 6 (0C) 0 F50 (0) 0 0 0 0 0 0 0 5 4 3 CCDSBL [4:0] 0 0 0 FLDSEL (1) 0 0 2 1 (4) SELFLOOP (0) 0 0 SLVFIX (1) WS262 (0) 0 0
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Description of I C Bus Registers
Write Command
Sub Address 10H Bit D15 D14 D13 D12, D11 D10 Name TRAPFIX TRAP358 YDLY1 [1:0] YPKGS Preset 0 0 0 01 0 0: hi-band, 1: low-band Select Y-horizontal decimation filter characteristic. D9 YLPFS YPKGG [1:0] CLPF [2:0] VWS [1:0] HWS [1:0] 0 0: hi-band, 1: low-band D8, D7 D6 to D4 D3, D2 D1, D0 00 000 00 00 Select Y-peaking gain level. 00: 0, 01: 1/4, 10: 1/2, 11: 1 Fix to `0' Change fsc-trap mode. 0: auto, 1: fix Comment
2
Select fsc-trap characteristic. (active at TRAPFIX = 1 only) 0: 4.43 MHz, 1: 3.58 MHz Y-output signal delay against U and V output signal (rough). Select Y-peaking filter characteristic.
Select R-Y/B-Y horizontal decimation filter characteristic. Select vertical decimation. Select horizontal decimation. 00: 1/3, 01: 1/4, 10: 1/5, 11: 1/6 00: 1/3, 01: 1/4, 10: 1/6, 11: 1/8
11H
D15, D14 D13
MF
00 0
Fix to `0' Set single-field display mode. 0: normal, 1: Fixed to single-field display
Select off-and-on cycle of field memory writing. (4 field step) 0000: normal D12 to D9 STRO [3:0] 0000 0001: strobe (once 6 fields) 0010: strobe (once 10 fields) D8 D7 to D5 D4 TATEON PIPNUM [2:0] RON MSNUM [2:0] MSON 0 000 0 1110: strobe (once 58 fields) 1111: still
Sub-pictures' set at multi-pictures 0: horizontal, 1: vertical Set multi-picture numbers of the animation picture. Sub-picture display ON/OFF. 0: OFF, 1: ON
Select multi-strobe pictures number. D3 to D1 000 000: 1-picture, 001: 2-pictures, 010: 3-pictures, 011: 4-pictures, 100: 5-pictures, 101: 6-pictures Select multi-strobe mode. (0: normal strobe mode, 1: multi-strobe mode)
D0
0
12H
D15 to D9
PHW [6:0]
011000 Sub-pictures range in the main-picture. (horizontal width, rough) 1 001001 Sub-pictures range in the main-picture (vertical height) 010 , when main-picture is 60 Hz system.
D8 to D0
PVWN [8:0]
13H D15 BBACK BLEVEL [1:0] SELGAIN PHE0 [2:0] PVWP [8:0] 0
Replace sub-picture by blue-back at write-memory. 0: normal, 1: blue-back D14, D13 D12 D11 to D9 D8 to D0 00 00 000 Select blue-back level. (DRAMCLRN = 1 or BBACK = 1 only) 00: black, 01: blue1, 10: blue2, 11: blue3 Control internal Y-level. 0: 1.5 times, 1: Twice
Sub-pictures range in the main-picture. (horizontal width, fine)
001011 Sub-pictures range in the main-picture (vertical height) 100 , when main-picture is 50 Hz system.
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Sub Address 14H Bit D15 to D8 Name PHS [7:0] Preset Comment
001010 Horizontal starting point of the sub-pictures in the main-picture. 11 1001100 Vertical starting point of the sub-pictures in the main-picture 01 , when main-picture is 60 Hz system.
D7 to D0
PVSN [7:0]
15H
D15 to D9
PHC [6:0]
000000 Set clock frequency of main-picture processing. 0 (set the dividing number of fH PLL.) 010000 Vertical starting point of the sub-pictures in the main-picture 011 , when main-picture is 50 Hz system.
D8 to D0
PVSP [8:0]
16H
D15 to D8
CHS [7:0]
000110 Horizontal starting point to write into the memory in the sub-picture. 01 000010 Vertical starting point to write into the memory in the sub-picture 10 at 60 Hz system.
D7 to D0
CVSN [7:0]
17H
D15 to D10 D9 D8 to D0
BRTRGB [5:0] CVSP [8:0]
000000 1
Control bright at RGB mode. 100000: -32 LSB, 000000: 0 LSB, 011111: +31 LSB Fix to `1'
100010 Vertical starting point to write into the memory in the sub-picture 010 at 50 Hz system.
18H
D15 D14 D13 D12 to D0
DRAMCLRN WADOS [12:0]
0 1 0
Field-memory reset Fix to `1' Fix to `0'
0: normal, 1: reset
000000 Set start-address to write the memory. 000000 (for the memory partition to memorize several sub-pictures at the same time.) 0
19H
D15 to D13 D12 to D0
RADOS [12:0]
000
Fix to `0'
000000 Set start-address to read from the memory. 000000 (for the select of sub-pictures in the memory) 0
1AH
D15 to D10 D9 to D5
HSPL [5:0] CLVL [4:0]
110010 Set number of horizontal sampling on the input sub-picture. Set color-level. 00000 10000: -6 dB, 00000: 0 dB, 01111: +6 dB Set contrast level.
D4 to D0
CTRT [4:0]
00000
00000: +1 dB, 11111: +3.5 dB
1BH
D15, D14 D13 to D8
HUEBIAS [5:0] HUE [7:0]
00 000000
Fix to `0' Adjustment the demodulation phases for R-Y signal. (NTSC only) 000000: 0, 111111: +45
D7 to D0
000000 Adjustment the demodulation phase for R-Y and B-Y signals. (NTSC only) 00 10000000: -45, 00000000: 0, 01111111: +45
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Sub Address 1CH Bit D15 to D10 D9 to D5 D4 to D0 Name MTXCB [5:0] MTXCG [24:20] MTXCG [14:10] Preset 110001 Set RGB matrix coefficient 1. 01100 01010 Set RGB matrix coefficient 2. Set RGB matrix coefficient 3. Comment
1DH D15, D10 YGOS [5:0] 000000
Set DC offset of sub-picture. (Y or G signal) 100000: -32 LSB, 000000: 0 LSB, 011111: +31 LSB Set DC offset of sub-picture. (R-Y or R signal) 10000: -16 LSB, 00000: 0 LSB, 01111: +15 LSB Set DC offset of sub-picture. (B-Y or B signal) D4 to D0 BOS [4:0] 00000 10000: -16 LSB, 00000: 0 LSB, 01111: +15 LSB
D9 to D5
ROS [4:0]
00000
1EH
D15, D14 D13, D12
YSDLY [1:0] FRAMEW [1:0] FRAMEYG [3:0] FRAMER [3:0] FRAMEB [3:0]
01 00
Timing offset of Ys pulse. 00: -1 ck, 01: center, 10: +1 ck, 11: +2 ck (24 MHz) Select the side frame width of sub-picture. 00: OFF (no-frame), 01: narrow, 10: center, 11: wide
D11 to D8 D7 to D4 D3 to D0
0000 0000 0000
Select frame signal level of PIP. (Y or G signal) Select frame signal level of PIP. (R-Y or R signal) Select frame signal level of PIP. (B-Y or B signal)
1FH
D15, D14 D13 D12
TYDLY [1:0] PMDFIX
00 0 0
Y-output signal delay for U and V output signal. (fine). Fix to `0' Clock frequency to read from the memory. 0: auto, 1: fix
D11, D10
PMDS [1:0]
00
Select Clock frequency to read from the memory. (active at PMDFIX = 1 only) 00: 12 MHz, 01: 9 MHz, 10: 18 MHz, 11: 16 MHz Set 50 Hz/ 60 Hz-conversion mode. (VWS = 1/3 mode only) 0: ON, 1: OFF
D9 D8 D7 to D3 D2 D1 D0
OFF2527 SELREV PFLDREV CFLDREV RGBON
0 0 00000 1 0 1
Set reverse mode. Fix to `0'
0: normal, 1: reverse
Reverse PFIELD at internal circuit. 0: reverse, 1: normal Reverse CFIELD at internal circuit. 0: normal, 1: reverse Select output signal format. 0: YUV, 1: RGB
20H
D15 to D8
CHLOADN [7:0] CHLOADP [7:0]
111111 Set clock frequency of sub-picture processing at 60 Hz system. 10 (set the dividing number of H-PLL) 111110 Set clock frequency of main-picture processing at 50 Hz system. 01 (set the dividing number of H-PLL)
D7 to D0
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Sub Address 21H Bit D15, D14 D13 to D7 Name ACCPAL [6:0] ACCNTSC [6:0] Preset 00 Fix to `0' Comment
011101 Set ACC reference level (for PAL). 0 0: Minimum level 127: Maximum level 101000 Set ACC reference level (for NTSC). 1 0: Minimum level 127: Maximum level
D6 to D0
22H
D15, D14 D13 to D7
KILON [6:0] KILOFF [6:0]
00
Fix to `0'
0: Minimum level 63: maximum level 000110 Set color killer ON level. 0 It must be set "KILON" < "KILOFF" 0: Minimum level 63: maximum level 001010 Set color killer OFF level. 0 It must be set "KILON" < "KILOFF"
D6 to D0
23H
D15, D14
NTSOFF [6:0]
00
Fix to `0'
D13 to D7
Set level to turn over from NTSC to PAL in NTSC/PAL detector. 001010 0: Minimum level 63: maximum level 0 It must be set "NTSON" < "NTSOFF" Set level to turn over from PAL to NTSC in NTSC/PAL detector. 000110 0: Minimum level 63: maximum level 0 It must be set "NTSON" < "NTSOFF"
D6 to D0
NTSON [6:0]
24H
D15 to D7
PIDREF [6:0]
000000 Fix to `0' 000 111011 Sensitivity of PAL-IDENT detection. 0 0: Minimum Sensitivity 63: Maximum Sensitivity
D6 to D0
25H
D15 to D12 D11 to D8 D7, D6 D5, D4
FSSTM [1:0]
0000 1111 00 10
Fix to `0' Fix to `1' Fix to `0' Set cycle of color system detection in color sub-carrier frequency detector. (1field step) 0: 1 field 3: 4 fields
D3, D2
FSSEL [1:0]
00
Set color system of sub-picture processing. (at FSMO = 11 only) 00: N-PAL, 01: M-PAL, 10: M-NTSC, 11: BG-PAL/4.43NTSC Mode for color sub-carrier frequency search
D1, D0
FSMO [1:0]
01
00: M-NTSC only, 01: BG-PAL/4.43NTSCM-NTSC, 10: N-PALM-PALM-NTSC, 11: FSSEL [1:0]
26H D15 to D10 SSLV [5:0] CCDSBH [4:0] CCDSBL [4:0] 100000
Set slice level for CCD. (this data is initial value of peak detector circuit at auto-slice mode.) D9 to D5 D4 to D0 01100 00100 Set minimum-width of high-period in start-bit for CCD. Set minimum-width of low-period in start-bit for CCD.
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TC90A67F
Sub Address 27H Bit D15, D14 D13 to D3 D2 D1 D0 Name FLDSEL SELPLOOP SLVFIX Preset 11 Fix to `1' Comment
000000 Fix to `0' 00000 1 0 0 Control CCD slice 1. Control CCD slice 2. Fix CCD slice level. 0: fix, 1: auto-slice
28H
D15 D14 D13 D12 D11 to D8 D7 D6 D5 to D1 D0
CCDL [3:0] F60 F50 WS262
1 0 1 0 1000 0 0 00000 0
Fix to `1' Fix to `0' Fix to `1' Fix to `0' Set line No. of data slicing for CCD. 1000: 21 H (NTSC) Force 60 Hz mode (sub-picture). Force 50 Hz mode (sub-picture). Fix to `0' Reverse CFIELD polarity. 0: even high, 1: odd high 0: normal, 1: force 0: normal, 1: force
29H
D15 D14, D13 D12 D11
WS262 WVINV
0 11 0 0
Fix to `0' Fix to `1' Reverse PFIELD polarity. 0: even high, 1: odd high
Set polarity of vertical sync pulse input at pin "PVD" . (main-picture) 0: Negative, 1: Positive D10 D9 D8 D7 to D0 WHINV F60 F50 0 0 0 Set polarity of horizontal sync pulse input at pin "PHD". (main-picture) 0: Positive, 1: Negative Force 60 Hz mode (main-picture) Force 50 Hz mode (main-picture) 0: OFF, 1: ON 0: OFF, 1: ON
000000 Fix to `0' 00
2000-03-23
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TC90A67F
Read Command
Sub Address 00H Bit D15 D14 to D11 D10 D9 D8 Name CRI3DET CRIN [3:0] CFIELD SBDET AEDGE 0: OK, 1: too near Caution of too near sampling point for front-edge of data. D7 D6 to D0 01H 02H D15 to D0 D15 D14 D13 D12 D11, D10 BEDGE 0: OK, 1: too near SLV [6:0] CCDDATA [15:0] NOSIG CVMD525 0: Non-standard, 1: Standard CNOVPN CVDET60 BCF [1:0] Vertical sync detection. (sub-picture) Vertical frequency detection. (sub-picture) System mode detection. (sub-picture) 0: exist, 1: No vertical sync 0: 50 Hz, 1: 60 Hz 00: N-PAL, 01: M-PAL, 10: M-NTSC, 11: BG-PAL/4.43NTSC Slice level data. CCD data including parity bits. Result of no-signal detection (sub-picture) 0: exist, 1: not-signal CRI detection. CRI number detection. Field-detection. (sub-picture) Start-bit (001) detection. 1: 1st field, 0: 2nd field 0: not start-bit detected, 1: start-bit detected Comment
Caution of too near sampling point for back-edge of data.
Vertical sync frequency standard/non-standard detection. (sub-picture)
Vertical sync frequency standard/non-standard detection. (main-picture) D9 D8 D7 D6 D5 D4 PVMD525 0: Non-standard, 1: Standard PNOVPN PVDET60 CKIL Vertical sync detection. (main-picture) Vertical frequency detection. (main-picture) Color Killer detection. (sub-picture) 0: exist, 1: No vertical sync 0: 50 Hz, 1: 60 Hz 0: Killer-off, 1: Killer-on 0: Lock, 1: Un-lock 0: NTSC or No-color, 1: PAL
PDUNLOCK H-PLL condition. (sub-picture) PALDET PAL signal detection.
CCD Data Slicer Supplementary Explanation
SLVFIX 1 SELFLOOP 0 FLDSEL Slice Level Control Circuit ON Detected Slice Level Feedback ON Motion Field at Auto Slice 1st and 2nd field
Auto slice function works both field. (CCD details sliced at suitable level) ON OFF 1st and 2nd field
1
1
Slice level is detecting from value of SSLV resistor, and sliced the most suitable value. (Detected slice level is not feedback at the next field) ON OFF Slice level is fixed value of SSLV resistor. ON ON 2nd field (CFIELD = 0)
0
1
0 0 0 ON 1 ON
Renewed slice level reading value of SLV resistor only 2nd field. 1st field (CFIELD = 1)
Renewed slice level reading value of SLV resistor only 1st field.
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TC90A67F
Outline of I C BUS Control Format
Sub-pictures range in the main-picture. (horizontal width)
2
Slave Address
A6 0 A5 0 A4 1 A3 0 A2 1 A1 1 A0 1 R/W 1/0
Write Format
SCL SDA SUB ADDRESS DATA (MSB) DATA (LSB)
START
SLAVE ADDRESS (0010111)
R/WACK
ACK
ACK
ACK END
Read Format
SCL SDA SUB ADDRESS DATA (MSB) DATA (LSB)
START
SLAVE ADDRESS (0010111)
R/W ACK
ACK END START
SLAVE ADDRESS (0010111)
R/W ACK
ACK
ACK END
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
2000-03-23
18/23
TC90A67F
Maximum Ratings (VSS = 0 V, Ta = 25C)
Characteristics Supply voltage Applied voltage Applied current Power dissipation Storage temperature Symbol VDD VIN IIN PD TSTG Rating VSS to VSS + 4.5 -0.3 to VDD + 0.3 10 1538 -55 to 125 Unit V V mA mW C
TD-PD (on board mounting)
Power dissipation PD
(mW)
1538 1500
1000 846
500
0
25
50
70
100
125
Ambient temperature (C)
Recommended Operating Conditions
Characteristics Supply voltage Input voltage Output voltage Ambient temperature Symbol VDD VIN VOUT TOPR Rating 3.0 to 3.6 0 to VDD 0 to VDD -10 to 70 Unit V V V C
2000-03-23
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TC90A67F
Electrical Characteristics DC Characteristics
Digital Part Operating Condition: VDD = 3.3 V, Ta = 25C
Characteristics Consumption current High input voltage Low level input voltage CMOS input Schmitt trigger input CMOS input Schmitt trigger input High level Input current Low level Output voltage High level Low level Symbol IDD VIH1 VIH2 VIL1 VIL2 IIH IIL VOH VOL Test Circuit Test Condition Min VDD x 0.8 VDD x 0.8 -10 -10 2.4 Typ. 160 Max 230 VDD VDD 0.8 0.8 +10 +10 0.4 Unit mA V V V V A A V V Applicable Terminals (Note1) (Note2) (Note1) (Note2) (Note1) (Note2) (Note1) (Note2) (Note3) (Note3)
Note1: CKC, CKCSEL, TEST, SDA, PIPEN, CKPSEL, CKP, TESTM0, TESTM1, TESTM2, TEST2 Note2: RESET, SCL, PVD, PHD Note3: CLMP, CSTD, PFIELD, CFIELD, CVREF, CHREF, CKILL, VCHIP, Ys, PHREF
ADC Characteristics Operating Condition: VDD = 3.3 V, Ta = 25C
Characteristics Resolution Input level Symbol RS1 ADIN BIASA Pin voltage A/D converter Non-linear error Differential non-linear error DG DP VREFH VREFL ILE1 DLE1 DG DP Test Circuit Test Condition AVDD = 3.3 V (8 bit precision) (8 bit precision) 0 0 Min Typ. 1.32 0.9 2.3 1.0 3 2 6.5 4.0 Max 8 Unit bit Vp-p V V V LSB LSB % deg Applicable Terminals CVI BIASA VREFH VREFL
2000-03-23
20/23
TC90A67F
DAC, VCO Characteristics Operating Condition: VDD = 3.3 V, Ta = 25C
Characteristics Resolution Symbol RS2 YOUT Output level ROUT BOUT Non-linear error D/A converter (VIDEO) Differential non-linear error Pin voltage BIAS2 Reference voltage level Output impedance Resolution Output level Non-linear error D/A converter (CLOCK) Differential non-linear error Pin voltage Reference voltage level Output impedance Pull-in frequency Input amplitude VCO Pull-in oscillation frequency FILTER terminal voltage VREFD ILE2 DLE2 BIAS1 Test Circuit Test Condition (VDD - VREFD) (VDD - VREFD) (VDD - VREFD) (8 bit precision) (8 bit precision) (VDD - VREF) (6 bit precision) (6 bit precision) Min 0.8 1.8 1.8 0.8 1.3 5.4 1.0 21.6 0.8 Typ. 1.0 2.0 Max 8 1.5 1.5 1.5 1 1 1.4 2.2 6 2.0 3 2 1.4 6.6 26.4 2.7 Unit bit Vp-p Vp-p Vp-p LSB LSB V V V bit Vp-p LSB LSB V V MHz V MHz V Applicable Terminals YOUT ROUT BOUT BIAS1 BIAS2 VREFD YOUT, ROUT, BOUT CKOUT BIASD VREF CKOUT CKIN FILTER
ZOUT1 RSD2 CKOUT ILE3 DLE3 BIASD VREF ZOUT2 FCK1 VCK FCK2 FILTER
200 1.0 200 6.0 2.0 24.0
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TC90A67F
Application Circuit
SDA SCL Ys PVD
PHD HD Q 1 F
PHREF
SW3
R14 30 k R15 30 k 0.1 F C22
SW2
C41
0.1 F
C23
14 13 12 11 10 74HC14AP 1 2 3 4 5
9
8
LQ13 VCHIP CKILL CKILL NC CHREF 40 CVREF 39 CFIELD 38 PFIELD 37 VDD 36 VSS 35 CSTD 34
6
7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PHREF PHD NC PVD PIPEN NC NC TESTM1 TESTM2 TESTM0 CKPSEL NC SCL RESET VDD VDD R20 2 k 8 9 TLC2933 10 11 C31 0.1 F C32 R19 10 F 560 R18 3 k 12 13 14 7 65 TEST2 6 5 4 LQ14 LQ15 3 2 1 TLC2933 LQ17 LQ16 C25 0.1 F R17 C26 10 k 0.1 F R16 8.2 k C27 0.1 F C28 Q3 2SC1815 C34 6 pF R21 4.7 k BOUT 0.1 F 73 BIAS1 74 NC 75 AVDD 76 BOUT 77 AVSS 78 ROUT CKOUT VREFH BIASD BIASA YOUT FILTER CKCSEL R22 4.7 k C29 0.1 F 79 AVDD VREFL AVDD AVSS AVSS AVSS CVI NC 80 YOUT 70 VREFD 71 BIAS2 72 NC TC90A67F (QFP80) C21 CSTD C20 0.1 F 69 NC C24 0.1 F 66 VDD 67 VSS 68 NC VCHIP SDA CKP VSS VSS Ys CHREF CVREF CFIELD PFIELD 0.1 F
C33 0.1 F
C30 0.1 F
NC 33 NC 32 VDD 31 NC 30 XO 29 XI 28 VSS 27 TEST 26 CLMP VDD 25 C16 0.1 F C18 1000 pF R13 100 C17 12 pF 270 k
B-Y (B) OUT
R24 470
ROUT
AVDD
VREF
AVSS
AVDD
CKIN
NC
R25 470
R-Y (R) OUT
C35 6 pF
TC90A67F 1 R23 4.7 k
2 C4 0.1 F
3 C5 0.1 F
4
5
6 C6 0.1 F
7 C7 0.1 F
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C14 0.1 F C15 0.1 F
R26 470
Q5 2SC1815 C36 6 pF
R8 R7 8.2 k 10 k C10 0.1 F Q2
820 0.01 F
C12
180 pF
Y (G) OUT
C8 0.1 F C9 0.1 F
NC
CKC
VSS
NC
Q4 2SC1815
C13
VIDEO INPUT R1 510 C1
33 k Q1
R3
C2 10 F
2SC1815 VIDEO C3 R6 10 k 1 F
LQ7
R9 1.5 k C11
2SC1B15 360 CKIN
68 pF R2 1 k R4 47 k R5 1 k
4 pF
LQ10 LQ5
LQ1
LQ2
LQ3
+3.3 V VSS LQ18 LQ19
LQ4
LQ6
C39
100 F
C40
0.1 F
LQ8
C37
100 F
C38
0.1 F
R10
LQ9
R11
CKC
SW1
L1 CY1 42 MHz 1.5 H C19
R12
LQ11
LQ12
18 pF
2000-03-23
22/23
TC90A67F
Package Dimensions
Weight: 1.6 g (typ.)
2000-03-23
23/23

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