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| 10/7/97 Errata: CS5394 Revision B CS5394 : 117 dB, 48 kHz Audio A/D Converter (DS258PP3 NOV '96) This information is provided to document the performance of the CS5394 revision B silicon. These items will be fixed in revision C silicon. s When in slave mode, the part must be calibrated with the LRCK low as in the following diagram: CAL LRCK t > 4400 / Fs s The rising edge of the CAL pin must lag the rising edge MCLK by at least 15 ns as in the diagram below: CAL MCLK t > 15 ns Datasheet Changes/Additions s s s Power consumption is 740 mW typical. MCLK max fall time is 8 ns. Pin 15 is connected to DGND. If there are any questions concerning this information please call: Steve Green - Applications Engineer (512) 442-7555 x3321 Tom Stein - Product Marketing Engineer (512) 442-7555 x3113 Cirrus Logic: Crystal Semiconductor Products Division PO Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com ER258B3 OCT `97 1 |
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