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Errata: CS4392 Data Sheet revision DS459PP1 dated OCT `00
The following is a correction to the CS4392 Datasheet revision DS459PP1, OCT'00. These changes will occur in the next revision of the datasheet. * * The chip ID register (07 h) is a reserved register. There is an internal 100 Ohm source impedance for the four analog output pins AOUTA+, AOUTA-, AOUTB+, and AOUTB-. This source impedance must be taken under consideration when designing the output filter such that the full-scale output level is not attenuated below the desired level. By design, the DSD frequency response is +0, -0.1 dB from 20Hz to 20kHz and the -3dB corner frequency is 120kHz (for Fs = 64x 44.1kHz). The group delay specifications are as follows (note: filter response is not tested but guaranteed by design): Fast Roll - Off Typical Max Single speed mode Group Delay Passband Group Delay Deviation 0 to 20 kHz Double Speed Mode Group Delay Passband Group Delay Deviation 0 to 20 kHz Quad Speed Mode Group Delay Passband Group Delay Deviation 0 to 20 kHz Contacting Cirrus Logic Support:
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm or email: proaudio@crystal.com
* *
Slow Roll -Off Typical Max 6.5/Fs 0.14/Fs
Unit
12/Fs -
0.41/Fs
s s
4.6/Fs -
0.03/Fs
3.9/Fs -
0.01/Fs
s s
4.7/Fs -
0.01/Fs
4.2/Fs -
0.01/Fs
s s
Cirrus Logic, Inc. P.O. Box 17847, Austin, Texas 78760 (512) 445-7222 FAX: (512) 445-7581 http://www.cirrus.com
ER459B2 MAR '01 1

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