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| Application Notes SH 100 G GCDR3300A The GCDR3300A is a macro to be used within the SH100G Gate Array-environment. This macro is designed for 2.5 - 3.3 GHz applications. It contains a 1:2 demultiplexer and a phase detector (PD) [1] with bit error detection and VCO (fig. 1). The block named 'UP' and 'DOWN' represents a mixer circuit for the UP and DOWN signals of the PD and the FD. The VCO has its own GND (I9) and negative supply N2V5 (I10), and is controlled by pin I7 (VF0). With a frequency window detector (FD), an operational amplifier and a voltage reference diode, a complete PLL can be built. The external configuration is shown in figure 3. CDR3300 I8 I1, I2 I5, I6 I3, I4 Stand: 10.12.96 Data Test tclk Alex clock O5,O6 Data Reset Clock D1 D2 O9, O10 O11, O12 DEMUX CLK/4 O7,O8 O3, O4 O1, O2 VCO I7 control I11, I12 I13, I14 I15, I16 I17, I18 I9 I10 DOWN FD PD UP FD PD O13 DON O14 UPN fig. 1: Block diagram GCDR3300A Table 1 shows the signal class and the function of the input and the output pins. The correct pin pad combination is given in table2. Semiconductor Group 1 Vers.: 1.3 Application Notes SH 100 G Table 1: Pin list Pinname I1,I2 data I3,I4 tclk I5,I6 test I7 control I8 I9, I19 I10 I11, I12 I13, I14 I15, I16 I17, I18 O1,O2 down O3,O4 up O5,O6 ber O7,O8 c/4 O9,O10 d1 O11,O12 d2 O13 DON O14 UPN Signal class Analog CML2 ECL2 Analog CML Analog Analog CML2 CML2 CML2 CML2 CML2 CML2 CML2 ECL2 CML2 CML2 Analog Analog Notes Differential data, 10 mV- 500 mVpp. 50 Ohm on chip resistors Differential clock used for testing. Select test mode. High = Test mode on Input integral path from PD, FD Reset toggle ff's demux GND for internal VCO N2V5 for internal VCO nom. -2.5V Down signal frequency detector Down signal phase detector Up signal frequency detector Up signal phase detector Down signal phase detector Up signal phase detector Bit error detection Clock/4 Data 1 Data 2 DON signal phase detector + 1/10 frequency detector UPN signal phase detector + 1/10 frequency detector Semiconductor Group 2 Vers.: 1.3 Application Notes SH 100 G Table 2: Pad macros Pin name I1, I2 I7 I9 I10 O13 O14 Pad macro PA50I PIWIRE2A PASUP1 PASUP1 PAWIRE PAWIRE Description Block Diagram In figure 1, the internal structure of the macro is shown. The block ALEX represents the combined phase detector and decision circuit [1]. In this block, the data signal is recovered and the UP and DOWN signals are generated. Also a Bit error detection signal (BER) is available. This BER signal can be used to build a 'Loss Of Signal' detection (LOS). The VCO is a ring oscillator structure with a K vco of about 2 GHz/V (fig. 3). The 1:2 demultiplexer circuit gets the data and clock signal from the ALEX. CDR3300 VCOsimulation VEE=2.5V 4,00 3,80 3,60 3,40 F/GHz 3,20 3,00 2,80 2,60 2,40 2,20 2,00 1,40 1,50 1,60 1,70 1,80 1,90 2,00 FD/V 2,10 2,20 2,30 2,40 F-10 F25 F80 F125 fig. 2: VCO frequency as function of the voltage at I7. Semiconductor Group 3 Vers.: 1.3 Application Notes SH 100 G VCC VCC a) 8 10uF T LM386-2.5 4 + 20mA 80 N2V5 5 15mA -4.5V VCC VCC b) 1 10uF T TL431(D) 2,3,6,7 + 20mA 80 N2V5 5 15mA -4.5V c) 844 VCC VCC VCC 844 100p 100p 100n 100 100n DON + 1k 1k 100n 100 100 5 UPN VF0 6mA fig. 3: External Parts of the PLL circuit a) negative VCO Supply from external reference (LM385-2.5). b) negative VCO Supply from external reference(TL431(SO8)). c) Integrator (part of Loop filter) e.g. TS3V912. Remark: The values given in this application note result in a supply range from 4 to 5.5V and a lower frequency limit of 2.4GHz. OPAMP requirements I(-1V): 0 mA I(-2.8V): 4.8 mA < 5 mV Uos: Semiconductor Group 4 Vers.: 1.3 Application Notes SH 100 G Pinout Table 3 shows the pad numbers for the G1 and G2 master with the two possible placements of the macro. Table 4 shows the placement of the connections from the core side. Table 3: Pad list of pad numbers Pin I1 I2 I7 I9 I10 I19 O13 O14 G1 Top PP317 PP318 PP321 PP316 PP315 PP319 PP321 PP320 G1 Bottom PP124 PP123 PP119 PP125 PP126 PP122 PP117 PP118 G2 Top PP309 PP311 PP315 PP310 PP306 PP312 PP317 PP316 G2 Bottom PP118 PP116 PP112 PP117 PP121 PP115 PP110 PP111 Table 4: Core ports Pin I3, I4 I5, I6 I8 I11, I12 I13, I14 I15, I16 I17, I18 O1, O2 O3, O4 O5,O6 O7, O8 O9, O10 O11, O12 G1 Top C1625 C1627 C1643 C1651 C1642 C1649 C1641 C1628 C1629 C1626 C1647 C1650 C1648 G1 Bottom C0152 C0150 C0132 C0126 C0134 C0128 C0135 C0149 C0148 C0151 C0130 C0127 C0129 G2 Top C1007 C1009 C1028 C1038 C1027 C1036 C1026 C1010 C1011 C1008 C1033 C1037 C1034 G2 Bottom C0137 C0135 C0116 C0107 C0117 C0109 C0118 C0134 C0133 C0136 C0111 C0108 C0110 Semiconductor Group 5 Vers.: 1.3 Application Notes SH 100 G Test Description A static test can be done by switching into the test mode (I5 = High, I6 = Low). Then the macro can be tested with an external clock (pin I3, I4) and data (pin I1, I2). At the beginning of a test sequence a reset (pin8) is done. The internal VCO can be stopped by leaving the pins N2V5 and VF0 open. Hints for Simulation In the simulation model, the VCO is inoperable. For simulations, the testmode is switched on. When the test mode is off, all outputs of the macro show the X-state. To simulate the demultiplexer part of the macro, a reset (pin8) has to be done. Data recovery Circuit in the SH100G Environment To build a complete PLL with LOS and demultiplexer, some additional circuits in the periphery and in the core area are needed. PLL The PLL consists of a phase detector(PD), a frequency detector (FD), and a loopfilter. The PD is realized in the macro GCDR3300A.The outputs O1-O4 of this macro are the UP and DOWN signals of the PD. These UP and DOWN signals are mixed with the UP and DOWN signals of the FD. This can be done with the inputs I11-I18 of the GCDR3300A. The signals of the PD are weighted 9 times stronger than the signals of the FD. So it is important to use the right input for each signal (see figure 1 and table 1)! Pin O13 and O14 of the GCDR3300A are fed to the loop filter. The external circuits can be implemented as shown in figure 3. The FD compares the divided VCO signal with a reference clock. The value of a counter, after a certain time, gives the information wether the VCO is too fast or too slow. When the FD gives the value 'too slow' or 'too fast' the PD signals have to be turned off at pin I13, I14 and I17, I18. This can be done by a multiplexer (fig. 4). Semiconductor Group 6 Vers.: 1.3 Application Notes SH 100 G I1,I2 I3,I4 I5,I6 I7 I8 I9 I10 I11,I12 I13,I14 I15,I16 I17,I18 GCDR3300A O1,O2 O3,O4 O5,O6 O7,O8 O9,O10 O11,O12 O13 O14 DON UPN LOW MUX 0 1 0 1 1 FD Up DOWN VST VST BER LOS LOS LOS fig. 4: Internal PLL circuit Frequency Detector For the frequency window detector (FWD) a reference clock (REF) is needed. This reference clock is divided by n, and this divided clock is the main parameter for designing the other parts of the FWD. A certain frequency window (FW) is given when the FWD is turned off. The counter is clocked by the VCO signal divided by x. After a certain time, given by REF, the value of the counter is compared with a reference value window. This comparison gives an UP or DOWN or OK (UP=DOWN= LOW) signal that is passed on a pulse former and then to the loop filter. For the design of the PLL, there are two constrains that have to be considered: the size of the loop filter and the size of the counter. A large counter range will determine the accuracy of the frequency but the FD will give less information in a certain time. Therefore a large loop filter is needed.This invokes a long transient time for the PLL. Semiconductor Group 7 Vers.: 1.3 Application Notes SH 100 G EARLY 1/N REF LATE 1 ERR UP VST VST Compare DOWN START VCO 1/X out Counter fig. 5: Frequency window detector block diagram EARLY LATE VST OUT VCO Counter DOWN OK UP fig. 6: Waveform frequency detector Semiconductor Group 8 Vers.: 1.3 Application Notes SH 100 G LOS A LOS can be generated with the help of the BER signal, pin O5 O6 of the GCDR3300A. This can be done with a counter that is reset after a certain time generated by the reference clock. When this counter reaches a specified value a LOS will be set immediately. The LOS will be reset when the value of the counter drops below another specified value that is below the first value. This time is specified by VST and SHIFT (fig. 8). BER Counter RESET Bit 1 2 3 4 5 6 7 8 9 .... REFCL LOS R VST SHIFT OK NOLOS R S LOS S fig. 7: LOS detection Example: The LOS has to be HIGH when the pulse rate of BER is higher then 10E-3. f VST = ( Fbit ) 2 16 ( 2 ) 16 = 65536Bit. 10E-3 = 65Bit LOS is LOW if less then 128 BER pulses are generated in a certain time. Semiconductor Group 9 Vers.: 1.3 Application Notes SH 100 G LOS R OK D R D R D REFCL & NOLOS fig. 8: SHIFT The Flip-flops in SHIFT are positive edge triggered Semiconductor Group 10 Vers.: 1.3 Application Notes SH 100 G 10-3 10-4 Bit Error Ratio 10-5 -3dB -6dB -9dB 10-6 10-7 10-8 10-9 10-10 -11 -2410 -28 -27 -26 -25 Optical Power /dBm Semiconductor Group 11 Vers.: 1.3 Application Notes SH 100 G DOWN UP Jitter distribution 40% UP 40% DOWN 20% 0 UP DOWN DOWN DOWN UP UP DOWN DOWN UP UP UP DOWN References [1] J. J. D. H. Alexander: "Clock Recovery from Random Binary Signals", Electronics Letters 11, pp. 541-542, Oct. 1975. Semiconductor Group 12 Vers.: 1.3 |
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