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MOTOROLA
MC9S12H-FamilyPP Rev 5.5, 11-Mar-03
SEMICONDUCTOR
TECHNICAL DATA
MC9S12H-Family
Product Proposal
16-Bit Microcontroller
All MC9S12H-Family member microcontroller units (MCU) are 16-bit devices composed of standard onchip peripherals including a 16-bit central processing unit (CPU12), up to 256K bytes of Flash EEPROM, 12K bytes of RAM, 4K bytes of EEPROM, one or two asynchronous serial communications interfaces (SCI), a serial peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 16-channel, 10-bit analog-to-digital converter (ADC), up to six-channel pulse width modulator (PWM), and up to two CAN 2.0 A, B software compatible modules (MSCAN12). In addition, they feature a 28x4 or 32x4 liquid crystal display (LCD) controller/driver and a motor pulse width modulator (PWM) consisting of 24 high current outputs suited to drive up to 6 stepper motors. System resource mapping, clock generation, interrupt control, and bus interfacing are managed by the system integration module. The MC9S12H-Family has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 14 I/O ports are available with Key-Wake-Up capability from STOP or WAIT mode.
Features
NOTE: Not all features listed here are available in all configurations! * 16-bit CPU12 -- Upward compatible with M68HC11 instruction set -- Interrupt stacking and programmer's model identical to M68HC11 -- Instruction queue -- Enhanced indexed addressing * 8-bit and 4-bit ports with Key Wake-Up Interrupt -- Digital filtering -- Programmable rising or falling edge trigger * Memory options -- 128K, 256K Flash EEPROM -- 2K, 4K byte EEPROM -- 6K, 12K byte RAM * Analog-to-Digital Converter -- 8 or 16 channels, 10-bit resolution -- External conversion trigger capability * One or two 1M bit per second, CAN 2.0 A, B software compatible modules -- Five receive and three transmit buffers -- Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit -- Four separate interrupt channels for Rx, Tx, error and wake-up -- Low-pass filter wake-up function -- Loop-back for self test operation
This document contains information on a new product. Specifications and information herein are subject to change without notice.
(c) MOTOROLA 2003
* Timer -- 16-bit main counter with 7-bit prescaler -- 8 programmable input capture or output compare channels -- Two 8-bit or one 16-bit pulse accumulators * 2 or 6 PWM channels depending on the package option -- Programmable period and duty cycle -- 8-bit 6-channel or 16-bit 3-channel -- 8-bit 2 channel or 16-bit 1 channel -- Separate control for each pulse width and duty cycle -- Center-aligned or left-aligned outputs -- Programmable clock select logic with a wide range of frequencies * Serial interfaces -- One or two asynchronous Serial Communications Interfaces (SCI) -- Synchronous Serial Peripheral Interface (SPI) -- Inter-Integrated Circuit interface (IIC) 144LQFP * Liquid Crystal Display driver with variable input voltage -- Configurable for up to 32 frontplanes and 4 backplanes or general purpose input or output -- 5 modes of operation allow for different display sizes to meet application requirements -- Unused frontplane and backplane pins can be used as general purpose I/O * 24 high current drivers suited for PWM motor control -- 12 PWM channels with common frequency timebase -- Each PWM channel switchable between two drivers in an H-bridge configuration -- left, right and center aligned outputs -- Support for sin and cos drive -- Dithering -- Output slew rate limitation * SIM (System Integration Module) -- CRG (windowed COP watchdog, real time interrupt, clock monitor, clock generation and reset) -- MEBI (multiplexed external bus interface) -- MMC (memory map and interface) -- INT (interrupt control) -- BKP (breakpoints) -- BDM (background debug mode) * Clock generation -- Phase-locked loop clock frequency multiplier -- self clock mode in absence of external clock -- Low power 0.5 to 16MHz crystal oscillator reference clock * 144-Pin or 112-Pin QFP package -- I/O lines with 5V input and drive capability -- 5V A/D converter inputs -- Operation at 32MHz equivalent to 16MHz Bus Speed -- Development support -- Single-wire background debugTM mode (BDM) -- On-chip hardware breakpoints
MOTOROLA 2
MC9S12H-Family PRODUCT PROPOSAL, Rev 5.5, 11-Mar-03
Table 1 List of MC9S12H-Family members
Flash 256K 128K RAM 12K 6K EEPROM Package 4K 2K Device CAN 2 2 2 SCI 2 1 1 SPI 1 1 1 IIC 1 0 0 A/D 16 8 8 PWM 6 2 2 LCD 32x4 28x4 28x4 Motor 24/6 24/6 24/6 I/O 93 61 61 144LQFP H256 112LQFP H256 112LQFP H128
* Pin out explanations: -- A/D is the number of A/D channels. -- Motor denotes the number of high current drive pins/number of stepper motors which can be driven -- I/O is the sum of ports capable to act as digital input or output. 144 Pin Packages: Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 5, L=8, M = 6, P = 6, S = 8, T = 8, PAD = 16 input only. 14 inputs provide Interrupt capability (H = 8, J = 4, IRQ, XIRQ) 112 Pin Packages: Port A = 8, B = 8, E = 6 + 2 input only, K=5, L=4, M = 4, P = 2, S = 6, T = 8, PAD = 8 input only. 2 inputs provide Interrupt capability (IRQ, XIRQ)
MC9S12H-Family PRODUCT PROPOSAL, Rev 5.5, 11-Mar-03
MOTOROLA 3
VDDR VDD1 VSS1,2
Voltage Regulator 128K, 256K Bytes Flash EEPROM 2K, 4K Bytes EEPROM
4K, 6K, 12K Bytes RAM
VDDA VSSA VRH VRL AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 PW0 PW1 PW2 PW3 PW4 PW5 RxD TxD
VDDA VSSA VRH VRL PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07 PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PP0 PP1 PP2 PP3 PP4 PP5 PS0 PS1
CPU12 Periodic Interrupt COP Watchdog Clock Monitor
XFC VDDPLL VSSPLL EXTAL XTAL RESET TEST PE0 PE1 PE4 PE5 PE6 VLCD XADDR14 XADDR15 XADDR16 XADDR17 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 PK0 PK1 PK2 PK3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PE2 PE3 PE7 PK7
PLL
Clock and Reset Generation Module
Breakpoints
XIRQ IRQ ECLK MODA MODB VLCD BP0 BP1 BP2 BP3 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 FP28 FP29 FP30 FP31 FP20 FP21 FP22 FP23
DDRP
DDRE
PTE
LCD Driver
Multiplexed Address/Data Bus
DDRM
CAN0 CAN1
RxCAN TxCAN RxCAN TxCAN
PTM
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15
SPI
DDRB
PTB
SDI/MISO SDO/MOSI SCK SS SCL SDA
DDRS PTS
PIX0 PIX1 PIX2 PIX3
PPAGE
DDRK
SCI0 SCI1
PTK
RxD TxD
PTP
System Integration Module
Pulse Width Modulator
PTAD
BKGD
Single-Wire Background Debug Module
Analog to Digital Converter
PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 VDDM1 VSSM1 PU0 PU1
IIC
DDRA
PTA
MOTOR0 and MOTOR1 Supply
PWM0 MOTOR0 PWM1 PWM2 MOTOR1 PWM3 M0C0M M0C0P
DDRL
Multiplexed Multiplexed Narrow Wide Bus Bus
DDRU
PTL
M1C0M M1C0P M1C1M M1C1P
PTU
M0C1M M0C1P
PU2 PU3 PU4 PU5 PU6 PU7 VDDM2 VSSM2 PV0 PV1
MOTOR2 and MOTOR3 Supply
R/W LSTRB/TAGLO NOACC/XCLKS ECS/ROMONE MOTOR3 PWM4 MOTOR2 PWM5 M2C0M M2C0P
DDRE
Pins shown in BOLD are not available in the 112 QFP package
PTE
DDRV
DDRK
PTK
PWM6 PWM7
M3C0M M3C0P M3C1M M3C1P
PTV
M2C1M M0C1P
PV2 PV3 PV4 PV5 PV6 PV7 VDDM3 VSSM2 PW0 PW1
PTW
PWM9 PWM10 MOTOR5 PWM11 Supply pins A/D Converter 5V & Voltage Regulator Reference VDDA VSSA
DDRW
NOTE: Not all functionality shown in this block diagram is available in all versions!
DDRT
PTT
PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PJ0 PJ1 PJ2 PJ3
FP24 FP25 FP26 FP27 IOC4 IOC5 IOC6 IOC7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 KWJ0 KWJ1 KWJ2 KWJ3
IOC0 IOC1 IOC2 IOC3
MOTOR4 and MOTOR5 Supply
PWM8 M4C0M M4C0P M4C1M M4C1P M5C0M M5C0P M5C1M M5C1P
Input Capture and Output Compare Timer
MOTOR4
PW2 PW3 PW4 PW5 PW6 PW7
DDRH
PTH
Pin Interrupt Logic
I/O Driver 5V Internal Logic 2.5V VDD1 VDDX1,2 VSS1,2 VSSX1,2 PLL 2.5V VDDPLL VSSPLL
DDRJ
PTJ
Vreg Input 5V VDDR
Figure 1. MC9S12H-Family Block Diagram
MOTOROLA 4
MC9S12H-Family PRODUCT PROPOSAL, Rev 5.5, 11-Mar-03
M0C0M/PU0 M0C0P/PU1 M0C1M/PU2 M0C1P/PU3 VDDM1 VSSM1 M1C0M/PU4 M1C0P/PU5 M1C1M/PU6 M1C1P/PU7 M2C0M/PV0 M2C0P/PV1 M2C1M/PV2 M2C1P/PV3 VDDM2 VSSM2 M3C0M/PV4 M3C0P/PV5 M3C1M/PV6 M3C1P/PV7 M4C0M/PW0 M4C0P/PW1 M4C1M/PW2 M4C1P/PW3 VDDM3 VSSM3 M5C0M/PW4 M5C0P/PW5
M5C1M/PW6 M5C1P/PW7 PWM0/PP0 PWM1/PP1 RxD0/PS0 TxD0/PS1 VSS2 VDDR VDDX2 VSSX2 BKGD RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST RxCAN0/PM2 TxCAN0/PM3
RxCAN1/PM4 TxCAN1/PM5
Figure 2. MC9S12H-Family Pin Assignments, 112 pin QFP package
MC9S12H-Family PRODUCT PROPOSAL, Rev 5.5, 11-Mar-03
MODA/PE5 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 IRQ/PE1
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PT7/IOC7 PT6/IOC6 PT5/IOC5 PT4/IOC4 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 VSSX1 VDDX1 PK7/ECS/ROMONE/FP23 PE7/NOACC/XCLKS/FP22 PE3/LSTRB/TAGLO/FP21 PE2/R/W/FP20 PL3/FP19 PL2/FP18 PL1/FP17 PL0/FP16 PA7/ADDR15/DATA15/FP15 PA6/ADDR14/DATA14/FP14 PA5/ADDR13/DATA13/FP13 PA4/ADDR12/DATA12/FP12 PA3/ADDR11/DATA11/FP11 PA2/ADDR10/DATA10/FP10 PA1/ADDR9/DATA9/FP9 PA0/ADDR8/DATA8/FP8 PB7/ADDR7/DATA7/FP7 PB6/ADDR6/DATA6/FP6
MC9S12H-Family 112 QFP
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 CAN1 is not available on the MC9S12H64 Version! 59 58 PM5:4 will be general purpose I/O 57
PB5/ADDR5/DATA5/FP5 PB4/ADDR4/DATA4/FP4 PB3/ADDR3/DATA3/FP3 PB2/ADDR2/DATA2/FP2 PB1/ADDR1/DATA1/FP1 PB0/ADDR0/DATA0/FP0 PK0/XADDR14/BP0 PK1/XADDR15/BP1 PK2/XADDR16/BP2 PK3/XADDR17/BP3 VLCD VSS1 VDD1 PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VDDA VRH VRL VSSA PE0/XIRQ PE4/ECLK PE6/MODB
MOTOROLA 5
M0C0M/PU0 M0C0P/PU1 M0C1M/PU2 M0C1P/PU3 VDDM1 VSSM1 M1C0M/PU4 M1C0P/PU5 M1C1M/PU6 M1C1P/PU7 KWH0/PH0 KWH1/PH1 KWH2/PH2 KWH3/PH3 M2C0M/PV0 M2C0P/PV1 M2C1M/PV2 M2C1P/PV3 VDDM2 VSSM2 M3C0M/PV4 M3C0P/PV5 M3C1M/PV6 M3C1P/PV7 KWH4/PH4 KWH5/PH5 KWH6/PH6 KWH7/PH7 M4C0M/PW0 M4C0P/PW1 M4C1M/PW2 M4C1P/PW3 VDDM3 VSSM3 M5C0M/PW4 M5C0P/PW5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
PT7/IOC7 PT6/IOC6 PT5/IOC5 PT4/IOC4 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 PJ3/KWJ3 PJ2/KWJ2 PJ1/KWJ1 PJ0/KWJ0 VSSX1 VDDX1 PK7/ECS/ROMONE/FP23 PE7/NOACC/XCLKS/FP22 PE3/LSTRB/TAGLO/FP21 PE2/R/W/FP20 PL7/FP31 PL6/FP30 PL5/FP29 PL4/FP28 PL3/FP19 PL2/FP18 PL1/FP17 PL0/FP16 PA7/ADDR15/DATA15/FP15 PA6/ADDR14/DATA14/FP14 PA5/ADDR13/DATA13/FP13 PA4/ADDR12/DATA12/FP12 PA3/ADDR11/DATA11/FP11 PA2/ADDR10/DATA10/FP10 PA1/ADDR9/DATA9/FP9 PA0/ADDR8/DATA8/FP8 PB7/ADDR7/DATA7/FP7 PB6/ADDR6/DATA6/FP6
MC9S12H-Family 144 QFP
Pins shown in BOLD are not available in the 112 QFP package
PB5/ADDR5/DATA5/FP5 PB4/ADDR4/DATA4/FP4 PB3/ADDR3/DATA3/FP3 PB2/ADDR2/DATA2/FP2 PB1/ADDR1/DATA1/FP1 PB0/ADDR0/DATA0/FP0 PK0/XADDR14/BP0 PK1/XADDR15/BP1 PK2/XADDR16/BP2 PK3/XADDR17/BP3 VLCD VSS1 VDD1 PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VDDA VRH VRL VSSA PE0/XIRQ PE4/ECLK PE6/IPIPE1/MODB
MOTOROLA 6
M5C1M/PW6 M5C1P/PW7 PWM0/PP0 PWM1/PP1 PWM2/PP2 PWM3/PP3 PWM4/PP4 PWM5/PP5 RxD0/PS0 TxD0/PS1 RxD1/PS2 TxD1/PS3 VSS2 VDDR VDDX2 VSSX2 MODC/TAGHI/BKGD RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SDA/PM0 SCL/PM1 RxCAN0/PM2 TxCAN0/PM3 RxCAN1PM4 TxCAN1/PM5 MODA/IPIPE0/PE5 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 IRQ/PE1
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Figure 3. MC9S12H-Family Pin Assignments, 144 Pin QFP package
MC9S12H-Family PRODUCT PROPOSAL, Rev 5.5, 11-Mar-03
Table 1. Pin Descriptions Note: Features shown in bold are not available in the 112 pin QFP package.
Pin Name Function 1 Pin Name Function 2 M0C0M, M0C0P, M0C1M, M0C1P Pin Name Function 3 Description Function 1: General purpose input/output pins. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 0. PWM output on M0C0M results in a positive current flow through coil 0 when M0C0P is driven to a logic high state. PWM output on M0C1M results in a positive current flow through coil 1 when M0C1P is driven to a logic high state. Supply input pins for motor 0 and motor 1 output drivers. Tolerance = 5 V 10%. Function 1: General purpose input or output pin. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 1. PWM output on M1C0M results in a positive current flow through coil 0 when M1C0P is driven to a logic high state. PWM output on M1C1M results in a positive current flow through coil 1 when M1C1P is driven to a logic high state. Function 1: General purpose input or output pin. Function 2: Key wake-up interrupt pin. When configured as an input, can generate an interrupt causing the MCU to exit STOP or WAIT mode. Function 1: General purpose input or output pin. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 2. PWM output on M2C0M results in a positive current flow through coil 0 when M2C0P is driven to a logic high state. PWM output on M2C1M results in a positive current flow through coil 1 when M2C1P is driven to a logic high state. Supply input pins for motor 2 and motor 3 output drivers. Tolerance = 5 V 10%. Function 1: General purpose input or output pin. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 3. PWM output on M3C0M results in a positive current flow through coil 0 when M3C0P is driven to a logic high state. PWM output on M3C1M results in a positive current flow through coil 1 when M3C1P is driven to a logic high state. Function 1: General purpose input or output pin. Function 2: Key wake-up interrupt pin. When configured as an input, can generate an interrupt causing the MCU to exit STOP or WAIT mode. Function 1: General purpose input or output pin. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 4. PWM output on M4C0M results in a positive current flow through coil 0 when M4C0P is driven to a logic high state. PWM output on M4C1M results in a positive current flow through coil 1 when M4C1P is driven to a logic high state. Supply input pins for motor 4 and motor 5 output drivers. Tolerance = 5 V 10% Function 1: General purpose input or output pin. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 5. PWM output on M5C0M results in a positive current flow through coil 0 when M5C0P is driven to a logic high state. PWM output on M5C1M results in a positive current flow through coil 1 when M5C1P is driven to a logic high state.
PU[3:0]
VDDM1, VSSM1
M1C0M, M1C0P, M1C1M, M1C1P
PU[7:4]
PH[3:0]
KWH[3:0]
PV[3:0]
M2C0M, M2C0P, M2C1M, M2C1P
VDDM2, VSSM2
M3C0M, M3C0P, M3C1M, M3C1P
PV[7:4]
PH[7:4]
KWH[7:4]
PW[3:0]
M4C0M, M4C0P, M4C1M, M4C1P
VDDM3, VSSM3
M5C0M, M5C0P, M5C1M, M5C1P
PW[7:4]
MC9S12H-Family PRODUCT PROPOSAL, Rev 5.5, 11-Mar-03
MOTOROLA 7
Table 1. Pin Descriptions Note: Features shown in bold are not available in the 112 pin QFP package.
Pin Name Function 1 PP[1:0] PP[5:2] Pin Name Function 2 PWM[1:0] PWM[5:2] Pin Name Function 3 Description Function 1: General purpose input or output pin. Function 2: Pulse Width Modulator (PWM) channel output pin. Function 1: General purpose input or output pin. Function 2: Pulse Width Modulator (PWM) channel output pin. Function 1: General purpose input or output pin. Function 2: RxD0 is the receive pin and TxD0 is the transmit pin of Serial Communication Interface 0 (SCI0). Function 1: General purpose input or output pin. Function 2: RxD1 is the receive pin and TxD1 is the transmit pin of Serial Communication Interface 1(SCI1). Core ground. Power supply input pin for voltage regulator. Nominal 5V Function 1: Pseudo-open-drain communication pin for the background debug function. Function 2: In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. Function 3: At the rising edge during reset, the state of this pin is latched to the MODC bit to set the MCU operating mode. An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. PLL supply output pins. No load allowed except for bypass capacitors. Dedicated pin used to create the PLL loop filter. Crystal driver and external clock input pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. Pin reserved for test. Function 1: General purpose input or output pin. Function 2: SDA is the serial data pin and SCL is the serial clock pin for the Inter-IC Bus Interface (IIC). Function 1: General purpose input or output pin. Function 2: RxCAN0 is the receive pin and TxCAN0 is the transmit pin for the Motorola Scalable Controller Area Network controller 0 (msCAN0). Function 1: General purpose input or output pin. Function 2: RxCAN1 is the receive pin and TxCAN1 is the transmit pin for the Motorola Scalable Controller Area Network controller 1 (msCAN1). CAN1 is not available for the MC9S12H64 Version!

PS[1:0]
TxD0, RxD0
PS[3:2] VSS2 VDDR
TxD1, RxD1

BKGD
TAGHI
MODC
RESET VDDPLL, VSSPLL XFC EXTAL, XTAL TEST PM[1:0]

SCL, SDA

PM[3:2]
TxCAN0, RxCAN0
PM[5:4]
TxCAN1, RxCAN1
PE[6:5]
MODB, MODA
Function 1: General purpose input or output pin. IPIPE1, IPIPE0 Function 2: The state of the MODA and MODB pins during reset determine the initial operating mode of the MCU. Function 3: Instruction queue tracking signals.
PS4
MISO
Function 1: General purpose input or output pin. Function 2: Master input (during master mode) or slave output (during slave mode) pin for the Serial Peripheral Interface (SPI).
MOTOROLA 8
MC9S12H-Family PRODUCT PROPOSAL, Rev 5.5, 11-Mar-03
Table 1. Pin Descriptions Note: Features shown in bold are not available in the 112 pin QFP package.
Pin Name Function 1 PS5 PS6 Pin Name Function 2 MOSI SCK Pin Name Function 3 Description Function 1: General purpose input or output pin. Function 2: Master output (during master mode) or slave input (during slave mode) pin for the Serial Peripheral Interface (SPI). Function 1: General purpose input or output pin. Function 2: Serial clock pin for the Serial Peripheral Interface (SPI). Function 1: General purpose input or output pin. Function 2: Slave select pin for the Serial Peripheral Interface (SPI). Function 1: General purpose input pin. Function 2: Maskable interrupt request input provides a means of applying asynchronous interrupt requests. Will wake up the MCU from STOP or WAIT mode. Function 1: General purpose input or output pin. Function 2: ECLK is the internal bus clock output. ECLK can be used as a timing reference. Function 1: General purpose input pin. Function 2: Nonmaskable interrupt request input provides a means of applying asynchronous interrupt requests. Will wake up the MCU from STOP or WAIT mode. Reference voltage input pins for the analog to digital converter. Supply input pins for the voltage regulator and the analog to digital converter. Tolerance = 5V 5%. Function 1: General purpose input pin. Function 2: Analog inputs for the analog to digital converter. Function 1: General purpose input pin. Function 2: Analog inputs for the analog to digital converter. Core supply output pins. No load allowed except for bypass capacitors. Supply input pin for the LCD driver. Adjusting the voltage on this pin will change the display contrast.

PS7 PE1
SS IRQ
PE4
ECLK

PE0
XIRQ
VRH, VRL VDDA, VSSA PAD[07:00] PAD[15:08] VDD1, VSS1 VLCD

AN[07:00] AN[15:08]

BP[3:0]
PK[3:0]
Function 1: General purpose input or output pin. XADDR[17:14] Function 2: LCD backplane segment driver output pin. Function 3: In MCU expanded modes of operation, expanded address pins for the external bus. ADDR[7:0]/ DATA[7:0] Function 1: General purpose input or output pin. Function 2: LCD frontplane segment driver output pin. Function 3: In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. Function 1: General purpose input or output pin. Function 2: LCD frontplane segment driver output pin. Function 3: In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. Function 1: General purpose input or output pin. Function 2: LCD frontplane segment driver output pin. Function 1: General purpose input or output pin. Function 2: LCD frontplane segment driver output pin. Function 1: General purpose input or output pin. Function 2: LCD frontplane segment driver output pin. Function 3: In MCU expanded modes of operations, performs the read/ write output signal for the external bus. This pin indicates direction of data on the external bus.
PB[7:0]
FP[7:0]
PA[7:0]
FP[15:8]
ADDR[15:8]/ DATA[15:8]
PL[3:0] PL[7:4]
FP[19:16] FP[31:28]

PE2
FP20
R/W
MC9S12H-Family PRODUCT PROPOSAL, Rev 5.5, 11-Mar-03
MOTOROLA 9
Table 1. Pin Descriptions Note: Features shown in bold are not available in the 112 pin QFP package.
Pin Name Function 1 Pin Name Function 2 Pin Name Function 3 Description Function 1: General purpose input or output pin. Function 2: LCD frontplane segment driver output pin. Function 3: In MCU expanded modes of operation, LSTRB is used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the low half of the instruction word being read into the instruction queue. Function 1: General purpose input or output pin. Function 2: LCD frontplane segment driver output pin. Function 3: The XCLKS signal selects between an external clock or oscillator configuration during reset. This pin should be at a logic high during reset if an external clock is used on the EXTAL input pin. This pin should be at a logic low during reset if an oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-down device during reset, if the pin is left floating, the default configuration is an oscillator circuit on EXTAL and XTAL. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or "free" cycle. This signal will assert when the CPU is not using the bus. Function 1: General purpose input or output pin. Function 2: LCD frontplane segment driver output pin. Function 3: During MCU expanded modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMONE). Also during MCU expanded modes of operation, this pin is used as the emulation chip select signal (ECS). Supply input pins for input/output drivers. Tolerance = 5V 5%. Function 1: General purpose input or output pin. Function 2: Key wake-up interrupt pin. When configured as an input, can generate an interrupt causing the MCU to exit STOP or WAIT mode. Function 1: General purpose input or output pin. Function 2: Timer system input capture or output compare pin. Function 3: LCD frontplane segment driver output pin. Function 1: General purpose input or output pin. Function 2: Timer system input capture or output compare pin.
PE3
FP21
LSTRB/ TAGLO
PE7
FP22
NOACC/ XCLKS
PK7
FP23
ECS/ ROMONE
VDDX1,2, VSSX1,2 PJ[3:0]
KWJ[3:0]

PT[3:0] PT[7:4]
IOC[3:0] IOC[7:4]
FP[27:24]
MOTOROLA 10
MC9S12H-Family PRODUCT PROPOSAL, Rev 5.5, 11-Mar-03
$0000 $0000 $0400 $1000 $03FF $0000 $0FFF $1000
1K Register Space Mappable to any 2K Boundary 4K Bytes EEPROM Initially overlapped by register space Mappable to any 4K Boundary 12K Bytes RAM Alignable to top ($1000 - $3FFF) or bottom ($0000 - $2FFF)
$4000
$3FFF $4000
Mappable to any 16K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$7FFF $8000 $8000 EXT $BFFF $C000 $C000
16K Fixed Flash EEPROM
16K Page Window Sixteen * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
Figure 4. MC9S12H256 User Configurable Memory Map
MC9S12H-Family PRODUCT PROPOSAL, Rev 5.5, 11-Mar-03
MOTOROLA 11
$0000 $0000 $0400 $0800 $1000 $2800 $03FF $0800 $0FFF $2800 $3FFF $4000 $4000
1K Register Space Mappable to any 2K Boundary 2K Bytes EEPROM Mappable to any 2K Boundary 6K Bytes RAM Alignable to top ($2800 - $3FFF) or bottom ($2000 - $37FF) of 8K Boundary Mappable to any 8K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$7FFF $8000 $8000 EXT $BFFF $C000 $C000
16K Fixed Flash EEPROM
16K Page Window Eight * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0800 - $1FFF: 6K RAM $0000 - $07FF: 2K EEPROM (1K not visible) Figure 5. MC9S12H128 User Configurable Memory Map
MOTOROLA 12
MC9S12H-Family PRODUCT PROPOSAL, Rev 5.5, 11-Mar-03
$0000 $0000 $0400 $0800 $2000 $3000 $4000 $03FF $0800 $0FFF
1K Register Space Mappable to any 2K Boundary 1K Bytes EEPROM repeated twice in 2K space Mappable to any 2K Boundary
$3000 $3FFF $4000
4K Bytes RAM Mappable to any 4K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$8000
$7FFF $8000 EXT
16K Fixed Flash EEPROM 16K Page Window Four * 16K Flash EEPROM Pages
$BFFF $C000 $C000 16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (1K not visible) $0000 - $07FF: 1K EEPROM (repeated twice in 2K address space, not visible) $1000 - $3FFF: 12K Flash Figure 6. MC9S12H64 User Configurable Memory Map
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USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver Colorado 80217. 1-800-441-2447, (303) 675-2140 INTERNET: http://mcu.motsps.com JAPAN: Motorola Japan Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298

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