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Datasheet File OCR Text: |
ICS513 LOCOTM PLL CLOCK GENERATOR Description The ICS513 LOCOTM is the most cost effective way to generate a high quality, high frequency clock output from a 14.31818 MHz crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed to replace crystal oscillators in most electronic systems. Using Phase-Locked-Loop (PLL) techniques, the device uses a standard, inexpensive crystal to produce output clocks up to 100 MHz. Stored in the chip's ROM is the ability to generate five different output frequencies, allowing one chip to work in different speed processor systems. The device also has a power-down mode that turns off the clock outputs when both select pins are low. In this mode, the internal PLL is not running. Features * * * * * * * * * * * * * * Packaged as 8-pin SOIC or die Available in Pb (lead) free package ICS' lowest cost PLL clock plus reference Produces common computer frequencies Input crystal frequency typically 14.3182 MHz Output clock frequencies up to 100 MHz from a 14.3182 MHz crystal or input clock Low jitter of 40 ps (one sigma) Compatible with all popular CPUs Duty cycle of 45/55 up to 200 MHz Custom frequencies available Operating voltage of 3.3 V to 5.5 V Power-down mode turns off chip 25 mA drive capability at TTL levels Advanced, low-power CMOS process Block Diagram VDD S1:0 2 PLL Clock Synthesis and Control Circuitry Crystal Oscillator CLK X1/ICLK 14.31818 MHz crystal or clock input X2 REF Optional crystal capacitors GND MDS 513 D I n t e gra te d C i r c u i t S y s t e m s 1 5 25 Race Stre et, San Jo se, CA 9 5126 Revision 070704 te l (40 8) 2 97-12 01 w w w. i c st . c o m ICS513 LOCOTM PLL Clock Generator Pin Assignment X1/ I CLK VDD GND REF 1 2 3 4 8 7 6 5 X2 S1 S0 CLK Clock Decoding Table (MHz) with 14.31818 MHz Crystal or Clock Input S1 0 0 M M 1 1 S0 0 1 0 1 0 1 CLK Power-down CLK 100 24 14.31818 48 3.6864 Multiplier -- 6.984 1.676 1 3.353 0.2576 Accuracy -- 1 ppm 1 ppm 0 ppm 0.017% 0.044% 8 - p i n ( 1 5 0 mi l ) S OI C 0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (floating) CLK and REF stop low in power-down state Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 Pin Name XI/ICLK VDD GND REF CLK S0 S1 X2 Pin Type Input Power Power Output Output Tri-level Input Tri-level Input Output Pin Description Crystal connection to a 14.31818 MHz crystal or clock input. Connect to +3.3 V or +5 V. Connect to ground. Reference 14.31818 MHz crystal oscillator buffered clock output. Clock output per table above. Select 0 for output clock. Connect to GND or VDD or float. See table above. Select 1 for output clock. Connect to GND or VDD or float. See table above. Crystal connection to a 14.31818 MHz crystal. Leave unconnected for clock input. MDS 513 D In te grated Circuit Systems 2 525 Ra ce Street, San Jose, CA 9512 6 Revision 070704 tel (4 08) 297 -1 201 w w w. i c s t . c o m ICS513 LOCOTM PLL Clock Generator External Components Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS513 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between VDD and the GND. It must be connected close to the ICS513 to minimize lead inductance. No external power supply filtering is required for the ICS513. used. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors, if needed, must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -12 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 8 pF [(16-12) x 2] = 8. Series Termination Resistor A 33 terminating resistor can be used next to the CLK and REF pins for trace lengths over one inch. Crystal Load Capacitors The total on-chip capacitance is approximately 12 pF. A parallel resonant, fundamental mode crystal should be Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS513. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD All Inputs and Outputs (referenced to GND) Ambient Operating Temperature Storage Temperature Soldering Temperature 7V Rating -0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 260C Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. 0 +3.0 Typ. Max. +70 +5.5 Units C V MDS 513 D In te grated Circuit Systems 3 525 Ra ce Street, San Jose, CA 9512 6 Revision 070704 tel (4 08) 297 -1 201 w w w. i c s t . c o m ICS513 LOCOTM PLL Clock Generator DC Electrical Characteristics VDD=5.0 V 5% , Ambient temperature 0 to +70C, unless stated otherwise Parameter Operating Voltage Input High Voltage, ICLK only Input Low Voltage, ICLK only Input High Voltage Input Low Voltage Input High Voltage Input Mid Voltage Input Low Voltage Output High Voltage Output Low Voltage IDD Operating Supply Current IDD Power-down Supply Current, 3.3 V Short Circuit Current On-Chip Pull-up Resistor Input Capacitance, S1, S0 Symbol VDD VIH VIL VIH VIL VIH VIM VIL VOH VOL Conditions ICLK (pin 1) ICLK (pin 1) S0 S0 S1 S1 S1 IOH = -25 mA IOL = 25 mA No load, 100MHz S1=S0=0 CLK output Pin 6 Pins 6, 7 Min. 3.0 (VDD/2)+1 2.0 Typ. VDD/2 VDD/2 Max. 5.5 (VDD/2)-1 0.8 Units V V V V V V V VDD-0.5 VDD/2 0.5 2.4 0.4 20 1.5 +70 270 4 V V V mA mA mA k pF AC Electrical Characteristics VDD = 5.0 V 5%, Ambient Temperature 0 to +70 C, unless stated otherwise Parameter Input Frequency, crystal input Input Frequency, clock input Output Frequency, VDD = 4.5 to 5.5 V Output Frequency, VDD = 3.0 to 3.6 V Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Power-up time, from PD to outputs stable Symbol FIN FIN FOUT FOUT tOR tOF tOD Conditions Min. 5 2 14 14 Typ. 14.31818 14.31818 100 100 1 1 Max. 27 50 140 100 Units MHz MHz MHz MHz ns ns 0.8 to 2.0 V 2.0 to 8.0 V 1.5 V,up to 140 MHz 45 49-51 5 55 10 % ms MDS 513 D In te grated Circuit Systems 4 525 Ra ce Street, San Jose, CA 9512 6 Revision 070704 tel (4 08) 297 -1 201 w w w. i c s t . c o m ICS513 LOCOTM PLL Clock Generator Parameter Power-down time, from running to PD state Absolute Clock Period Jitter One Sigma Clock Period Jitter Symbol Conditions Min. Typ. Max. 50 Units ns ps ps tja tjs Deviation from mean +140 50 Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol JA JA JA JC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 150 140 120 40 Max. Units C/W C/W C/W C/W Thermal Resistance Junction to Case Marking Diagram 8 5 Marking Diagram (Pb free) 8 5 ICS513M YYWW ###### 1 4 1 ICS513ML YYWW ###### 4 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year and the week. 3. "L" designates Pb (lead) fee package. MDS 513 D In te grated Circuit Systems 5 525 Ra ce Street, San Jose, CA 9512 6 Revision 070704 tel (4 08) 297 -1 201 w w w. i c s t . c o m ICS513 LOCOTM PLL Clock Generator Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 8 Inches Min Max Symbol Min Max E INDEX AREA H 12 D A A1 B C D E e H h L 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8 .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8 A A1 h x 45 C -Ce B SEATING PLANE L .10 (.004) C Ordering Information Part / Order Number ICS513M ICS513MT ICS513MLF ICS513MLFT Marking ICS513M ICS513M ICS513ML ICS513ML Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC Temperature 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C "LF" denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 513 D In te grated Circuit Systems 6 525 Ra ce Street, San Jose, CA 9512 6 Revision 070704 tel (4 08) 297 -1 201 w w w. i c s t . c o m |
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