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Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
FEATURES
* 18 LVCMOS/LVTTL outputs, 16 typical output impedance * Selectable LVCMOS_CLK or LVPECL clock inputs * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL * Maximum output frequency: 250MHz * Output skew: 150ps (maximum) * Part to part skew: 750ps (maximum) * Full 3.3V or 2.5V supply modes * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Lead-Free package fully RoHS compliant * Pin compatible with the MPC940L
GENERAL DESCRIPTION
The ICS83940 is a low skew, 1-to-18 LVPECLto-LVCMOS/LVTTL Fanout Buffer and a member HiPerClockSTM of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS83940 has two selectable clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines.
ICS
The ICS83940 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the ICS83940 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
GND VDDO Q0 Q1 Q2 Q3 Q4 Q5
CLK_SEL PCLK nPCLK LVCMOS_CLK GND 1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25
0
24 23 22
Q6 Q7 Q8 VDD Q9 Q10 Q11 GND
18
Q0:Q17
GND LVCMOS_CLK CLK_SEL PCLK nPCLK VDD VDDO
1
ICS83940
21 20 19 18 17
9 10 11 12 13 14 15 16
Q17 Q16 Q15 GND Q14 Q13 Q12 VDDO
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Pacakge Top View
83940BY
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REV. A DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Name GND Power Input Input Input Input Power Power Output Type Description Power supply ground. Pulldown Clock input. LVCMOS / LVTTL interface levels. Clock select input. Selects LVCMOS / LVTTL clock Pulldown input when HIGH. Selects PCLK, nPCLK inputs when LOW. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential LVPECL clock input. Pullup Inver ting differential LVPECL clock input. Core supply pins. Output supply pins. Clock outputs. 16 typical output impedance. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2, 12, 17, 25 3 4 5 6 7, 21 8, 16, 29 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32
LVCMOS_CLK CLK_SEL PCLK nPCLK VDD VDDO Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN C PD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance 11 VDD, VDDO = 3.47 VDD, VDDO = 2.625 Test Conditions Minimum Typical 4 13 11 51 51 16 21 Maximum Units pF pF pF K K
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input CLK_SEL 0 1 PCLK, nPCLK Selected De-selected Clock LVCMOS_CLK De-selected Selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK_SEL 0 0 0 0 0 0 1 1 LVCMOS_CLK -- -- -- -- -- -- 0 1 PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 -- -- nPCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 -- -- Outputs Q0:Q17 LOW HIGH LOW HIGH HIGH LOW LOW HIGH Input to Output Mode Differential to Single Ended Differential to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting Non Inver ting Non Inver ting
NOTE 1: Please refer to the Application Information section. "Wiring the Differential Input to Accept Single Ended Levels".
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REV. A DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0 TO 70
Symbol Parameter VDD VDDO IDD IDDO Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 25 25 Units V V mA mA
TABLE 4B. DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0 TO 70
Symbol Parameter VIH VIL VPP VCMR IIN VOH Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Input Common Mode Voltage; NOTE 1, 2 Input Current Output High Voltage LVCMOS_CLK LVCMOS_CLK PCLK, nPCLK PCLK, nPCLK 300 GND + 1.5 VDD 200 IOH = -20mA 2.4 0.5 Test Conditions Minimum 2.4 Typical Maximum VDD 0.8 Units V V mV V A V V
VOL Output Low Voltage IOL = 20mA NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. A DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Test Conditions PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK f 150MHz f 150MHz f > 150MHz f > 150MHz Measured on rising edge @VDDO/2 f < 150MHz f < 150MHz f > 150MHz f > 150MHz Measured on rising edge @VDDO/2 0.5 to 2.4V 0.5 to 2.4V 0.3 0.3 Minimum Typical Maximum 250 3.4 3.8 3.7 4 150 150 1.4 1.2 1.7 1.4 850 750 1.2 1.2 55 Units MHz ns ns ns ns ps ps ns ns ns ns ps ps ns ns %
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0 TO 70
Symbol Parameter fMAX Output Frequency tpLH Propagation Delay;
2 2.6 2 2.6
tpLH
Propagation Delay;
tsk(o) tsk(pp) tsk(pp) tsk(pp)
tR tF
Output Skew; NOTE 3, 5 Par t-to-Par t Skew; NOTE 6 Par t-to-Par t Skew; NOTE 6 Par t-to-Par t Skew; NOTE 4, 5 Output Rise Time Output Fall Time
odc Output Duty Cycle f < 134MHz 45 50 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0 TO 70
Symbol Parameter VDD VDDO IDD IDDO Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 Maximum 2.625 2.625 25 25 Units V V mA mA
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REV. A DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Test Conditions LVCMOS_CLK LVCMOS_CLK PCLK, nPCLK PCLK, nPCLK 300 GND + 1.5 VDD 200 IOH = -12mA 1.8 0.5 Minimum 2 Typical Maximum VDD 0.8 Units V V mV V A V V
TABLE 4D. DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0 TO 70
Symbol Parameter VIH VIL VPP VCMR IIN VOH Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Input Common Mode Voltage; NOTE 1, 2 Input Current Output High Voltage
VOL Output Low Voltage IOL = 12mA NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0 TO 70
Symbol Parameter fMAX Output Frequency tpLH Propagation Delay; PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK Test Conditions f 150MHz f 150MHz f > 150MHz f > 150MHz Measured on rising edge @VDDO/2 f < 150MHz f < 150MHz f > 150MHz f > 150MHz Measured on rising edge @VDDO/2 0.5 to 1.8V 0.5 to 1.8V 0.3 0.3 Minimum Typical Maximum 200 4.6 4.4 4.4 4.4 200 200 2.6 1.7 2.2 1.7 1.2 1.0 1.2 1.2 55 Units MHz ns ns ns ns ps ps ns ns ns ns ns ns ns ns %
2 2.7 2.2 2.7
tpLH
Propagation Delay;
tsk(o) tsk(pp) tsk(pp) tsk(pp)
tR tF
Output Skew; NOTE 3, 5 Par t-to-Par t Skew; NOTE 6 Par t-to-Par t Skew; NOTE 6 Par t-to-Par t Skew; NOTE 4, 5 Output Rise Time Output Fall Time
odc Output Duty Cycle f < 134MHz 45 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
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REV. A DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDD, V DDx
SCOPE
Qx
VDD, VDDx
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
V DD
2.5V OUTPUT LOAD AC TEST CIRCUIT
V
nPCLK
Qx
DDx
2
V
PCLK
PP
Cross Points
V
CMR
V
Qy
DDx
2 tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
PART 1 Qx
OUTPUT SKEW
2.4V 0.5V
tR tF 2.4V 0.5V
V
DDx
2
PART 2 Qy
V
DDx
Clock Outputs
2 tsk(pp)
PART-TO-PART SKEW
3.3V OUTPUT RISE/FALL TIME
VDD 2
LVCMOS_CLK
nPCLK
1.8V 0.5V tR
1.8V
PCLK
Clock Outputs
0.5V tF
Q0:Q17 VDDx 2
2.5V OUTPUT RISE/FALL TIME
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PROPAGATION DELAY
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REV. A DECEMBER 14, 2004
tPD
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V
3.3V
2.5V
2.5V 3.3V R3 120 SSTL Zo = 60 Ohm PCLK R4 120
3.3V
R1 50
R2 50
PCLK
CML
Zo = 50 Ohm
Zo = 60 Ohm
Zo = 50 Ohm
nPCLK
HiPerClockS PCLK/nPCLK
R1 120 R2 120
nPCLK
HiPerClockS PCLK/nPCLK
FIGURE 2A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3 125
R4 125
PCLK
3.3V
Zo = 50 Ohm
LVDS
R5 100
Zo = 50 Ohm
C1
R3 1K
R4 1K
PCLK
C2
Zo = 50 Ohm
nPCLK
LVPECL
R1 84
R2 84
HiPerClockS Input
Zo = 50 Ohm
nPCLK
HiPerClockS PCL K/n PC LK
R1 1K
R2 1K
FIGURE 2C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 2E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. A DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83940 is: 820
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REV. A DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-026
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REV. A DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Marking ICS83940BY ICS83940BY ICS83940BYLF ICS83940BYLF Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP on Tape and Reel Count 250 per tray 1000 250 per tray 1000 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS83940BY ICS83940BYT ICS83940BYLF ICS83940BYLFT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83940BY
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REV. A DECEMBER 14, 2004
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change CPD Value changed from 10pF to 13pF for 3.47V and added 11pF for 2.625V In Features section, first bullet changed Output Impedance from 23 to 16. T1 Pin Description, changed Q outputs description from 23 to 16 output impedanace. Updated format. 3V AC Characteristics - corrected Par t-to-Par t Skew (f<150MHz) unit from ps to ns. Updated Single Ended Signal Driving Differential Input diagram. Added LVPECL Input Interface section. Features Section - added Lead-Free bullet. Ordering Information Table - added Lead-Free par t number. Date 4/25/02 5/23/02 12/12/02
Rev A A A
Table T2
Page 2 1 2
T5A A
4 7 8 1 11
3/17/04
A
T8
12/14/04
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REV. A DECEMBER 14, 2004

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