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Integrated Circuit Systems, Inc.
ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
FEATURES
* Dual differential LVDS outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK * Output frequency range: 31.25MHz to 700MHz * Crystal input frequency range: 10MHz to 25MHz * VCO range: 250MHz to 700MHz * Parallel or serial interface for programming counter and output dividers * RMS period jitter: 2.7ps (typical) * Cycle-to-cycle jitter: 18ps (typical) * 3.3V supply voltage * 0C to 85C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS8442 is a general purpose, dual output Crystal-to-Differential LVDS High Frequency HiPerClockSTM Synthesizer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8442 has a selectable TEST_CLK or crystal input. The TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to LVDS levels. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interface to the configuration logic. The low phase noise characteristics of the ICS8442 makes it an ideal clock source for Gigabit Ethernet and Sonet applications.
ICS
BLOCK DIAGRAM
VCO_SEL
PIN ASSIGNMENT
VCO_SEL nP_LOAD XTAL_IN
M4
M3
M2
M1
M0
XTAL_SEL TEST_CLK XTAL_IN OSC XTAL_OUT 0
32 31 30 29 28 27 26 25 1 M5 M6 M7 M8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TEST VDD FOUT1 nFOUT1 VDD FOUT0 nFOUT0 GND
24 23 22
XTAL_OUT TEST_CLK XTAL_SEL VDDA S_LOAD S_DATA S_CLOCK MR
PLL
PHASE DETECTOR MR /M VCO 0 1 /1 /2 /4 /8 FOUT0 nFOUT0 FOUT1 nFOUT1
N0 N1 nc GND
ICS8442
21 20 19 18 17
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
CONFIGURATION INTERFACE LOGIC
TEST
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
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Integrated Circuit Systems, Inc.
ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
cific default state that will automatically occur during powerup. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 10 M 28. The frequency out is defined as follows: FOUT = fVCO = fxtal x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-toLOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: T1 0 0 1 1 T0 0 1 0 1 TEST Output LOW S_Data, Shift Register Input Output of M divider CMOS FOUT
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8442 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVDS output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8442 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a spe-
SERIAL LOADING
S_CLOCK S_DATA
t
T1
S
T0
H
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N1 nP_LOAD
t
S
M, N
t
H
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
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ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
Type Input Input Input Unused Power Output Power Output Output Pullup M divider inputs. Data latched on LOW-to-HIGH transistion Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels. Pulldown Determines output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. No connect. Power supply ground. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS / LVTTL interface levels. Core supply pins. Differential output for the synthesizer. LVDS interface levels. Differential output for the synthesizer. LVDS interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not effect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between cr ystal oscillator or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. Test clock input. LVCMOS / LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. LVCMOS / LVTTL interface levels. Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3, 4, 28, 29, 30, 31, 32 5, 6 7 8, 16 9 10, 13 11, 12 14, 15 Name M5 M6, M7, M8, M0, M1, M2, M3, M4 N0, N1 nc GND TEST VDD FOUT1, nFOUT1 FOUT0, nFOUT0
17
MR
Input
Pulldown
18 19 20 21 22 23 24, 25 26 27
S_CLOCK S_DATA S_LOAD VDDA XTAL_SEL TEST_CLK XTAL_IN, XTAL_OUT nP_LOAD VCO_SEL
Input Input Input Power Input Input Input Input Input
Pulldown Pulldown Pulldown
Pullup Pulldown
Pulldown Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL
AND
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK X X X L L X S_DATA X X X Data Data Data X Data Reset. When HIGH, forces the outputs to a differential LOW state (FOUTx = LOW and nFOUTx = HIGH), but does not effect loaded M, N, and T values. Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked.
MR H L L L L L L L
nP_LOAD X L H H H H H
M X Data Data X X X X X
N X Data Data X X X X X
S_LOAD X X L L L H
NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency (MHz) 250 275 * * 650 675 M Divide 10 11 * * 26 27 256 M8 0 0 * * 0 0 128 M7 0 0 * * 0 0 64 M6 0 0 * * 0 0 32 M5 0 0 * * 0 0 16 M4 0 0 * * 1 1 8 M3 1 1 * * 1 1 4 M2 0 0 * * 0 0 2 M1 1 1 * * 1 1 1 M0 0 1 * * 0 1 0
700 28 0 0 0 0 1 1 1 0 NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs N1 0 0 1 1 N0 0 1 0 1 N Divider Value 1 2 4 8 Output Frequency (MHz) Minimum 250 125 62.5 31.25 Maximum 70 0 350 175 87.5
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ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5V 10mA 15mA 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 85C
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 155 20 Units V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 85C
Symbol Parameter VIH Input High Voltage M0-M8, N0, N1, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD, XTAL_SEL, VCO_SEL TEST_CLK M0-M8, N0, N1, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD, XTAL_SEL, VCO_SEL TEST_CLK M0-M4, M6-M8, N0, N1, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD, M5, XTAL_SEL, VCO_SEL M0-M4, M6-M8, N0, N1, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD, M5, XTAL_SEL, VCO_SEL VOH Test Conditions Minimum Typical 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 5 A Units V V V V A
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
-150 V 0.5 V
Output TEST; NOTE 1 2.6 High Voltage Output TEST; NOTE 1 VOL Low Voltage NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information section, "3.3V Output Load Test Circuit".
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 85C
Symbol VOD VOD VOS VOS
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Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change
Test Conditions
Minimum 250 1.125
Typical 45 0 1.4
Maximum 600 50 1.6 50
Units mV mV V mV
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ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
Test Conditions Minimum Typical Maximum Units
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 85C
Symbol Parameter TEST_CLK; NOTE 1 10 25 MHz XTAL_IN, XTAL_OUT; Input Frequency 10 25 MHz fIN NOTE 1 S_CLOCK 50 MHz NOTE 1: For the input crystal and TEST_CLK frequency range the M value must be set for the VCO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 10MHz valid values of M are 25 M 70. Using the maximum frequency of 25MHz valid values of M are 10 M 28.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 10 Test Conditions Minimum Typical Maximum 25 50 7 1 Units MHz pF mW Fundamental
TABLE 7. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 85C
Symbol FOUT Parameter Output Frequency Cycle-to-Cycle Jitter; NOTE 1, 3 Period Jitter, RMS; NOTE 1, 3 Output Skew; NOTE 2, 3 Output Rise/Fall Time M, N to nP_LOAD tS Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH odc tPW Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD Output Duty Cycle; NOTE 4 Output Pulse Width N>1 N=1 20% to 80% 150 5 5 5 5 5 5 48 tPeriod/2 - 150 52 tPeriod/2 + 150 N = 1, 2 N=4 Test Conditions Minimum 31.25 18 27 2.7 Typical Maximum 700 28 45 7 15 650 Units MHz ps ps ps ps ps ns ns ns ns ns ns % ps ms
tjit(cc) tjit(per) tsk(o)
tR / tF
PLL Lock Time 1 tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: In the Applications Section, please refer to the application note, "Differential Duty Cycle Improvement."
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ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VDD
VDD out
SCOPE
Qx
Power Supply +
Float GND
DC Input
LVDS
out
-
LVDS
nQx
VOS/ VOS
3.3V OUTPUT LOAD TEST CIRCUIT
VDD
OFFSET VOLTAGE SETUP
nFOUTx
out
FOUTx
DC Input
LVDS
nFOUTy FOUTy
100
VOD/ VOD out
tsk(o)
DIFFERENTIAL OUTPUT VOLTAGE SETUP
nFOUT0, nFOUT1 FOUT0, FOUT1
OUTPUT SKEW
VOH VREF
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
Cycle-to-Cycle Jitter
nFOUT0, nFOUT1 FOUT0, FOUT1
t PW
t
PERIOD
odc =
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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tcycle n+1
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
VOL
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
Period Jitter
80% Clock Outputs 80% VSW I N G 20% tR tF 20%
t PW t PERIOD
x 100%
OUTPUT RISE/FALL TIME
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ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER APPLICATION INFORMATION
STORAGE AREA NETWORKS
A variety of technologies are used for interconnection of the elements within a SAN. The tables below lists the common frequencies used as well as the settings for the ICS8442 to generate the appropriate frequency.
Table 8. Common SANs Application Frequencies
Interconnect Technology Gigabit Ethernet Fibre Channel Infiniband Clock Rate 1.25 GHz FC1 1.0625 GHz FC2 2.1250 GHz 2.5 GHz Reference Frequency to SERDES (MHz) 125, 250, 156.25 106.25, 53.125, 132.8125 125, 250 Crystal Frequency (MHz) 25, 19.53125 16.6015625, 25 25
Table 9. Configuration Details for SANs Applications
Interconnect Technology Crystal Frequency (MHz) 25 25 Gigabit Ethernet 25 19.53125 25 Fiber Channel 1 25 Fiber Channel 2 Infiniband 25 250 0 0 0 0 1 0 1 0 0 0 1 16.6015625 25 106.25 132.8125 125 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 0 0 156.25 156.25 53.125 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 1 ICS8442 Output Frequency to SERDES (MHz) 125 250 ICS8442 M & N Settings M8 M7 M6 M5 M4 0 0 0 0 0 0 0 0 1 1 M3 M2 0 0 1 1 M1 M0 0 0 0 0 N1 1 0 N0 0 1
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8442 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD and V DDA, should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, better power supply isolation is required. Figure 2 illustrates how a 10 along |with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
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3.3V VDD .01F V DDA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
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ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
suitable for most applications. Additional accuracy can be achieved by adding two small capacitors C1 and C2 as shown in Figure 3. Typical results using parallel 18pF crystals are shown in Table 10.
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode operation. The ICS8442 has a built-in crystal oscillator circuit. This interface can accept either a series or parallel crystal without additional components and generate frequencies with accuracy
XTAL_IN C1 18p X1 18pF Parallel Crystal XTAL_OUT C2 22p
Figure 3. CRYSTAL INPUt INTERFACE
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
3.3V 3.3V Zo = 50 Ohm
LVDS_DRIVER R1 100
CLK
nCLK Zo = 50 Ohm HiPerClockS
100 Differential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
DIFFERENTIAL DUTY CYCLE IMPROVEMENT
The schematic below is recommended for applications using the /1 output configuration for improving the differential duty cycle.
Vcc = 3.3V
R2 1.3k Zo = 50 R1 100 Zo = 50 C1
R4 1.3k
.1uf C2
+
.1uf
LVDS Driv er
R3 800
R5 800
Receiv er_dif
FIGURE 5. DIFFERENTIAL DUTY CYCLE IMPROVEMENT
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ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board.
LAYOUT GUIDELINE
The schematic of the ICS8442 layout example used in this layout guideline is shown in Figure 6A. The ICS8442 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual
C1 X1
C2
U1
32 31 30 29 28 27 26 25
9 10 FOUT1 11 nFOUT1 12 VDD 13 FOUT0 14 nFOUT0 15 16
ICS8442
VDD
TEST VDD FOUT1 nFOUT1 VDD FOUT0 nFOUT0 GND
1 2 3 4 5 6 7 8
M4 M3 M2 M1 M0 VCO_SEL nP_LOAD X_IN
VDD 24 23 22 21 20 19 18 17 R7 10 VDDA C11 0.01u C16 10u
M5 M6 M7 M8 N0 N1 nc GND
X_OUT T_CLK nXTAL_SEL VDDA S_LOAD S_DATA S_CLOCK MR
Zo = 50 Ohm + Zo = 50 Ohm R1 100 -
C14 0.1u
C15 0.1u
Zo = 50 Ohm + R2 100
Zo = 50 Ohm
-
FIGURE 6A. RECOMMENDED SCHEMATIC LAYOUT
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
traces should be routed first and should be locked prior to routing other signal traces. * The traces with 50 transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock trace on same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. * Make sure no other signal trace is routed between the clock trace pair. The matching termination resistors R1 and R2 should be located as close to the receiver input pins as possible. Other termination scheme can also be used but is not shown in this example.
POWER
AND
GROUNDING
Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. If VDDA shares the same power supply with VDD, insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the VDDA as possible.
CLOCK TRACES
AND
TERMINATION
The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal
CRYSTAL
The crystal X1 should be located as close as possible to the pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
GND
C1 C2
VDD VIA
X1 U1
PIN 1
C11 C16 VDDA R7
C14 C15
TL1
TL1N
TL1
Close to the input pins of the receiver R1
For FOUT0/n FOUT0 output TL1, TL1N are 50 Ohm traces and equal length Same requirement fo FOUT1/nFOUT1
TL1N
FIGURE 6B. PCB BOARD LAYOUT
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ICS8442
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Integrated Circuit Systems, Inc.
ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 10. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8442 is: 3662
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ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 11. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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Integrated Circuit Systems, Inc.
ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
Marking Package 32 Lead LQFP 32 Lead LQFP 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature 0C to 85C 0C to 85C 0C to 85C 0C to 85C
TABLE 12. ORDERING INFORMATION
Part/Order Number ICS8442AY ICS8442AYT ICS8442AYLF ICS8442AYLFT ICS8442AY ICS8442AY ICS8442AYLF ICS8442AYLF
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8442AY
www.icst.com/products/hiperclocks.html
14
REV. D MAY 10, 2005
Integrated Circuit Systems, Inc.
ICS8442
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev A
Table T1 T4A
Page 2 3 5
Description of Change Corrected labels on the Parallel & Serial Load Operations diagram. Revised MR pin description. Power Supply table - changed IDD to 155mA max. from 130mA max., changed IDDA to 20mA max. from 15mA max., and changed IDDO to 55mA max. from 45mA max. Added LVDS Driver Termination Section. General Description & Features - changed VCO min. from 200MHz to 250MHz and replaced throughout the datasheet in: (Functional Description pg2, T3C Program. Output Divider Func. Table pg4, and T5 Input Freq Charac. Table pg6). - Features - changed min. Output Frequency Range from 25MHz to 31.25MHz. Pin Descriptions Table - revised XTAL1,XTAL2 pin description. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Prog. VCO Freq. Func. Table - deleted 200 and 225 rows, does not apply. Power Supply DC Characteristics Table - deleted VDDO & IDDO rows, does not apply. AC Characteristics Table - change FOUT 25MHz min. to 31.25MHz min. Revised Parallel & Serial Load Operations diagram. Cr ystal Characteristics Table - changed ESR from 70 max. to 50 max. Deleted Table 10, Typical Results of Cr ystal Input Interface Frequency Fine Tuning Absolute Maximum Ratings - updated Outputs rating. Ordering Information table - added "Lead-Free" par t number. AC Characteristics Table - added Note 4. Added Applications Note, "Differential Duty Cycle Improvement". Changed XTAL1/2 naming convention to XTAL_IN/_OUT throughout the datasheet. Pin Assignment, corrected pin 24 to read XTAL_OUT from XTAL1 and pin 25 to XTAL_IN from XTAL2. Updated Figure 1, Parallel & Serial Load Operations diagram. Cr ystal Characteristics Table - added Drive Level AC Characteristics Table - changed test conditions for Cycle-to-Cycle Jitter from = 350MHz to N = 1, 2 and < 350MHz to N = 4. Corrected Cr ystal Input Interface diagram. Updated Schematic Layout diagram. Add Lead-Free note to Ordering Information Table.
Date 12/18/02
B
2/13/03
B
9 1
3/12/03
C
T1 T2 T3B
3 3 4 5
5/9/03
T7 C T6
6 2 6 9 5 14 6 9 1
8/12/03
C C
T12 T7
7/8/04 12/15/04
D
T6 T7
2 6 6 9 10 14
5/10/05
T12
8442AY
www.icst.com/products/hiperclocks.html
15
REV. D MAY 10, 2005

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