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Integrated Circuit Systems, Inc.
ICS8537-01
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
FEATURES
* 12 LVPECL outputs * Selectable differential CLKx, nCLKx inputs * CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * Maximum output frequency: 700MHz * Translates any differential input signal (LVHSTL, SSTL, DCM) to LVPECL levels without external bias networks * Translates any single-ended input signal to LVPECL with resistor bias on nCLKx input * Output skew: 130ps (maximum) * Bank skew: 20ps (maximum) * Part-to-part skew: 350ps (maximum) * Propagation delay: 1.5ns (maximum) * 3.3V or 2.5V operating supply * 0C to 85C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8537-01 is a Hex low skew, high performance 1-to-2 Differential-to-3.3V/2.5 LVPECL HiPerClockSTM Clock Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8537-01 has six selectable clock inputs. The CLKx, nCLKx pairs can accept most differential input levels and translate them to 3.3V or 2.5V LVPECL output levels.
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Guaranteed output and part-to-part skew specifications make the ICS8537-01 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK0 nCLK0 Q0A nQ0A Q0B nQ0B Q1A nQ1A Q1B nQ1B Q2A nQ2A Q2B nQ2B Q3A nQ3A Q3B nQ3B Q4A nQ4A Q4B nQ4B Q5A nQ5A Q5B nQ5B
PIN ASSIGNMENT
nQ2A Q2A VCCO Q2B nQ2B VCC VEE nQ3A Q3A VCCO Q3B nQ3B
CLK1 nCLK1
CLK2 nCLK2
CLK3 nCLK3
nQ4A Q4A VCCO Q4B nQ4B VCC VEE nQ5B Q5B VCCO Q5A nQ5A
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS8537-01
nQ1B Q1B VCCO Q1A nQ1A VCC VEE nQ0B Q0B VCCO Q0A nQ0A
nCLK0 CLK0 nCLK1 CLK1 nCLK2 CLK2 nCLK3 CLK3 nCLK4 CLK4 nCLK5 CLK5
CLK4 nCLK4
CLK5 nCLK5
48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
8537AY-01
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REV. A JANUARY 29, 2003
Integrated Circuit Systems, Inc.
ICS8537-01
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
Type Output Power Output Power Power Output Output Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Pullup Pulldown Pullup Pulldown Pullup Pulldown Pullup Pulldown Pullup Pulldown Pullup Pulldown Description Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Core supply pins. Negative supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Inver ting differential clock input. Non-inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 10, 27, 34, 39, 46 4, 5 6, 31, 42 7, 30, 43 8, 9 11, 12 13 14 15 16 17 18 19 20 21 22 23 24 25, 26 28, 29 32, 33 35, 36 37, 38 40, 41 44, 45 47, 48 Name nQ4A, Q4A VCCO Q4B, nQ4B VCC VEE nQ5B, Q5B Q5A, nQ5A CLK5 nCLK5 CLK4 nCLK4 CLK3 nCLK3 CLK2 nCLK2 CLK1 nCLK1 CLK0 nCLK0 nQ0A, Q0A Q0B, nQ0B nQ1A, Q1A Q1B, nQ1B nQ2A, Q2A Q2B, nQ2B nQ3A, Q3A Q3B, nQ3B
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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REV. A JANUARY 29, 2003
Integrated Circuit Systems, Inc.
ICS8537-01
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
Test Conditions Minimum Typical 51 51 Maximum 4 Units pF K K
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs CLKx 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLKx 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0A:Q5A, Q0B:Q5B LOW HIGH LOW HIGH HIGH LOW Outputs nQ0A:nQ5A, nQ5B:nQ5B HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single ended levels".
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REV. A JANUARY 29, 2003
Integrated Circuit Systems, Inc.
ICS8537-01
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
4.6V -0.5V to VCC + 0.5 V -0.5V to VCCO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.465V, TA = 0C TO 85C
Symbol VCC VCCO IEE Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 2.375 2.375 Typical 3.3 3.3 Maximum 3.465 3.465 130 Units V V mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.465V, TA = 0C TO 85C
Symbol IIH IIL VPP Parameter Input High Current CLKx nCLKx Input Low Current CLKx nCLKx Test Conditions VIN = VCC = 3.465V VIN = VCC = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.15 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Voltage
Common Mode Voltage; NOTE 1, 2 VEE + 0.5 VCMR NOTE 1: For single ended appliations, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.465V, TA = 0C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 1.0 VCCO - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
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REV. A JANUARY 29, 2003
Integrated Circuit Systems, Inc.
ICS8537-01
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
Test Conditions 700MHz Minimum 1.1 Typical 1.3 Maximum 700 1.5 130 20 350 20% to 80% 300MHz 200 47 600 53 55 Units MHz ns ps ps ps ps % %
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.465V, TA = 0C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 5 Bank Skew; NOTE 3, 5 Par t-to-Par t Skew; NOTE 4, 5 Output Rise/Fall Time Output Duty Cycle
tsk(o) tsk(b) tsk(pp)
tR / tF odc
> 300MHz, 500MHz 45 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured from at the output differential cross points. NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 4: Defined as between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A JANUARY 29, 2003
Integrated Circuit Systems, Inc.
ICS8537-01
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCO = 2V VCC Qx
SCOPE
nCLKx
LVPECL
nQx CLKx
V
PP
Cross Points
V
CMR
VEE = -0.375V to -1.465V
V EE
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
tsk(pp)
nQx Qx nQy Qy
tsk(o)
PART-TO-PART SKEW
nQxA QxA nQxB QxB
OUTPUT SKEW
80%
80% V
SW I N G
20% Clock Outputs t
R
20% t
F
tsk(b)
BANK SKEW
nQx Qx
Pulse Width t
PERIOD
OUTPUT RISE/FALL TIME
nCLKx CLKx nQx Qx
tPD
odc =
t PW t PERIOD
odc & tPERIOD
8537AY-01
PROPAGATION DELAY
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REV. A JANUARY 29, 2003
Integrated Circuit Systems, Inc.
ICS8537-01
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
Zo = 50 5 2 Zo FOUT Zo = 50 FOUT 50 50 VCC - 2V Zo = 50 3 2 Zo FIN Zo = 50
3.3V 5 2 Zo
FIN
RTT =
1 (VOH + VOL / VCC -2) -2
Zo
FIGURE 2A. LVPECL OUTPUT TERMINATION
8537AY-01
RTT
3 2 Zo
FIGURE 2B. LVPECL OUTPUT TERMINATION
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Integrated Circuit Systems, Inc.
ICS8537-01
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8537-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8537-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 130mA = 450.5mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 12 * 30.2mW = 362.4mW
Total Power_MAX (3.465V, with all outputs switching) = 450.5mW + 362.4mW = 812.9mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.813W * 42.1C/W = 104.2C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE qJA
FOR
48-PIN LQFP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS8537-01
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 3.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = VOH_MAX = VCCO_MAX - 1.0V (V
CCO_MAX
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. A JANUARY 29, 2003
Integrated Circuit Systems, Inc.
ICS8537-01
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8537-01 is: 1201
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REV. A JANUARY 29, 2003
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ICS8537-01
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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REV. A JANUARY 29, 2003
Integrated Circuit Systems, Inc.
ICS8537-01
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V/2.5V LVPECL CLOCK BUFFER
Marking ICS8537AY-01 ICS8537AY-01 Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 85C 0C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8537AY-01 ICS8537AY-01T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8537AY-01
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