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Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
FEATURES
* 20 LVCMOS outputs, 7 typical output impedance * 1 LVCMOS clock input * Maximum output frequency: 250MHz * Bank enable logic allows unused banks to be disabled in reduced fanout applications * Output skew: 250ps (maximum) * Part-to-part skew: 600ps (maximum) * Bank skew: 200ps (maximum) * Multiple frequency skew: 300ps (maximum) * 3.3V or mixed 3.3V input, 2.5V output operating supply modes * 0C to 70C ambient operating temperature * Other divide values available on request
ICS8701
GENERAL DESCRIPTION
The ICS8701 is a low skew, /1, /2 LVCMOS Clock Generator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines.
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The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The bank enable inputs, BANK_EN0:1, support enabling and disabling each bank of outputs individually. The master reset input, nMR/ OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The ICS8701 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the ICS8701 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK /1 /2 DIV_SELA 1 QB0:QB4 0 DIV_SELB 1 QC0:QC4 0 DIV_SELC 1 QD0:QD4 0 DIV_SELD nMR/OE BANK_EN0 BANK_EN1 Bank Enable Logic 1 QA0:QA4 0
PIN ASSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
GND QB2 GND QB3 VDDO QB4 QC0 VDDO QC1 GND QC2 GND
QC3 VDDO QC4 QD0 VDDO QD1 GND QD2 GND QD3 VDDO QD4
ICS8701
QB1 VDDO QB0 QA4 VDDO QA3 GND QA2 GND QA1 VDDO QA0
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DIV_SELA DIV_SELB CLK GND VDD BANK_EN0 GND BANK_EN1 VDD nMR/OE DIV_SELC DIV_SELD
48-Pin LQFP 7mm x 7mm x 1.4mm Y Package Top View
REV. C AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
Type Power Description Output supply pins.
ICS8701
TABLE 1. PIN DESCRIPTIONS
Number 2, 5, 11, 26, 32, 35, 41, 44 7, 9, 18, 21, 28, 30, 37, 39, 46, 48 16, 20 25, 27, 29, 31, 33 34, 36, 38, 40, 42 43, 45, 47, 1, 3 4, 6, 8, 10, 12 22 Name VDDO
GND VDD QA0, QA1, QA2, QA3, QA4 QB0, QB1, QB2, QB3, QB4 QC0, QC1, QC2, QC3, QC4 QD0, QD1, QD2, QD3, QD4 CLK
Power Power
Power supply ground.
Positive supply pins. Bank A outputs.LVCMOS / LVTTLinterface levels. Output 7 typical output impedance. Bank B outputs.LVCMOS / LVTTLinterface levels. Output 7 typical output impedance. Bank C outputs.LVCMOS / LVTTLinterface levels. Output 7 typical output impedance. Bank D outputs. LVCMOS / LVTTLinterface levels. Output 7 typical output impedance. Input Pulldown LVCMOS / LVTTL clock input. Controls frequency division for Bank D outputs. 13 DIV_SELD Input Pullup LVCMOS / LVTTLinterface levels. Controls frequency division for Bank C outputs. 14 DIV_SELC Input Pullup LVCMOS / LVTTLinterface levels. Controls frequency division for Bank B outputs. 23 DIV_SELB Input Pullup LVCMOS / LVTTLinterface levels. Controls frequency division for Bank A outputs. 24 DIV_SELA Input Pullup LVCMOS / LVTTLinterface levels. Enables and disables outputs by banks. BANK_EN1, Input Pullup 17, 19 LVCMOS / LVTTLinterface levels. BANK_EN0 Master Reset and output enable. When HIGH, output drivers are 15 nMR/OE Input Pullup enabled. Whe LOW, output drivers are in HiZ and dividers are reset. LVCMOS / LVTTLinterface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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REV. C AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
Test Conditions Minimum Typical 51 51 VDD, VDDO = 3.465V 7 15 Maximum 4 Units pF K K pF
ICS8701
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance
TABLE 3. FUNCTION TABLE
nMR/OE 0 1 1 1 1 1 1 1 1 Inputs BANK_EN1 BANK_EN0 X X 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 DIV_SELx X 0 0 0 0 1 1 1 1 QA0:QA4 Hi Z Active Active Active Active Active Active Active Active QB0:QB4 Hi Z Hi Z Active Active Active Hi Z Active Active Active Outputs QC0:QC4 QD0:QD4 Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Active Hi Z Active Active Hi Z Hi Z Hi Z Hi Z Active Hi Z Active Active Qx Frequency zero fIN/2 fIN/2 fIN/2 fIN/2 fIN fIN fIN fIN
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REV. C AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C
ICS8701
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA =0C TO 70C
Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 95 Units V V mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA =0C TO 70C
Symbol Parameter Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDD = VDDO = 3.135V IOH = -36mA VDD = VDDO = 3.135V IOL = 36mA -150 -5 2.6 0.5 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 5 150 Units V V V V A A A A V V
VIH
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH VOL
Output High Voltage Output Low Voltage
8701CY
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REV. C AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
Test Conditions f 200MHz Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 30% to 70% 30% to 70% f 200MHz 280 280 tCYCLE/2 - 0.5 2 Minimum 2.2 Typical Maximum 250 3.4 200 250 300 600 850 850 tCYCLE/2 + 0.5 3 Units MHz ns ps ps ps ps ps ps ns ns ns ns
ICS8701
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA =0C TO 70C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Duty Cycle
tsk(b) tsk(o) tsk(w) tsk(pp)
tR tF odc
tCYCLE/2
f = 200MHz 2.5 Output Enable Time; tEN f = 10MHz 6 NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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REV. C AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 95 Units V V mA
ICS8701
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Power Supply Current
TABLE 4D. LVCMOS DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE CLK Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDD = 3.135V, VDDO = 2.375 IOH = -27mA VDD = 3.135V, VDDO = 2.375 IOL = 27mA -150 -5 1.8 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 5 150 Units V V V V A A A A V
VIH
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH
Output High Voltage
VOL
Output Low Voltage
0.5
V
8701CY
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REV. C AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
Test Conditions f 200MHz Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 Measured on rising edge atVDDO/2 30% to 70% 30% to 70% f 200MHz 280 280 tCYCLE/2 - 0.5 2 Minimum 2.6 Typical Maximum 250 3.6 225 250 300 600 850 850 tCYCLE/2 + 0.5 3 Units MHz ns ps ps ps ps ps ps ns ns ns ns
ICS8701
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise Time; NOTE 6 Output Fall Time; NOTE 6 Output Duty Cycle
tsk(b) tsk(o) tsk(w) tsk(pp)
tR tF odc
tCYCLE/2
f = 200MHz 2.5 Output Enable Time; tEN f = 10MHz 6 NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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REV. C AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
ICS8701
PARAMETER MEASUREMENT INFORMATION
1.65V 5%
SCOPE
VDD, VDDO
LVCMOS
Qx
GND = -1.25V 5%
3.3V OUTPUT LOAD TEST CIRCUIT
2.05V 5% 1.25V 5%
V DD VDDO
SCOPE
LVCMOS
VDDO GND = +1.25V
Qx
-1.25V 5%
3.3V/2.5 OUTPUT LOAD TEST CIRCUIT
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REV. C AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
VDDO 2
ICS8701
Qx
VDDO 2 Qy
tsk(o)
OUTPUT SKEW
PART 1 Qx
VDDO 2
PART 2 Qy
VDDO 2
tsk(pp)
PART-TO-PART SKEW
70%
70% V
SWING
30% Clock Outputs t
R
30% t
AND
F
OUTPUT RISE
FALL TIME
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REV. C AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
V
DD
ICS8701
CLK
2
V
QAx, QBx, QCx, QDx
DDO
2 t
PD
PROPAGATION DELAY
V
QAx, QBx, QCx, QDx
DDO
2 Pulse Width t
PERIOD
odc & tPERIOD
POWER CONSIDERATIONS
For Power Dissipation, please refer to a separate Application Note: Power Dissipation for LVCMOS Buffer.
DRIVER TERMINATION
For LVCMOS Output Termination, please refer to a separate Application Note: LVCMOS Driver Termination.
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REV. C AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR RELIABILITY INFORMATION
ICS8701
TABLE 6. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8701 is: 1743
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REV. C AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
ICS8701
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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REV. C AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
Marking ICS8701CY ICS8701CY Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 70C 0C to 70C
ICS8701
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS8701CY ICS8701CYT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8701CY
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REV. C AUGUST 19, 2002
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVCMOS CLOCK GENERATOR
REVISION HISTORY SHEET
ICS8701
Rev B
Table 5A 5B 4B 4D 1
C
C
Page 5 7 8 - 10 4 6 11 2 9
Description of Change Updated notes. Updated notes. Updated drawings. Revised VIH rows from 3.8 Maximum to VDD + 0.3 Maximum. Revised VIH rows from 3.8 Maximum to VDD + 0.3 Maximum. Added Power Dissipation and Driver Termination notes. Pin Description Table, revised nMR/OE description. Updated Output Rise/Fall Time Diagram.
Date 10/4/01
11/28/01
8/19/02
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REV. C AUGUST 19, 2002

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