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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889834
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
FEATURES
* 4 differential LVPECL/ECL outputs * 2 LVCMOS/LVTTL clock inputs * Output frequency: >1GHz (typical) * Output skew: TBD * Part-to-part skew: TBD * Additive jitter, RMS: <100fs (typical) * Propagation delay: 420ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.63V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.63V to -2.375V * -40C to 85C ambient operating temperature * Pin compatible with SY89834U
GENERAL DESCRIPTION
The ICS889834 is a high speed 2-to-4 LVCMOS/ LVTTL-to-LVPECL/ECL Clock Multiplexer and is HiPerClockSTM a member of the HiPerClockSTM family of high performance clock solutions from ICS. The ICS889834 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The device also has an output enable pin which may be useful for system test and debug purposes. The ICS889834 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in spaceconstrained applications.
ICS
BLOCK DIAGRAM
SEL
Q0 nQ0
PIN ASSIGNMENT
nQ0 VCC
Q1 1 nQ1 2 Q2 3 nQ2 4
16 15 14 13 12 11 10 9 5
Q3
Q0
VEE
IN1 SEL nc IN2
IN1
1 MUX
IN2
Q1 nQ1
6
nQ3
7
VCC
8
EN
0
Q2 D Q nQ2
ICS889834
16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View
EN
Q3 nQ3
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
889834AK
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REV. A JULY 9, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889834
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
Type Description Differential output pair. LVPECL / ECL interface levels. Differential output pair. LVPECL / ECL interface levels. Differential output pair. LVPECL / ECL interface levels. Positive supply pins. Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ outputs will go HIGH on the next LOW transition at IN inputs. Input threshold is VCC/2V. Includes a 37k pull-up resistor. Default state is HIGH when left floating. The internal latch is clocked on the falling edge of the input signal (IN1, IN2). LVTTL / LVCMOS interface levels. LVCMOS / LVTTL clock input. No connect. Pullup Pullup Select input pin. LVCMOS / LVTTL interface levels LVCMOS / LVTTL clock input. Negative supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 14 Name Q1, nQ1 Q2, nQ2 Q3, nQ3 VCC Output Output Output Power
8
EN
Input
Pullup
9 10 11 12 13
IN2 nc SEL IN1 V EE
Input Unused Input Input Power
Pullup
15, 16 Q0, nQ0 Output Differential output pair. LVPECL / ECL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLUP Parameter Input Pullup Resistor Test Conditions Minimum Typical 37 Maximum Units K
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REV. A JULY 9, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889834
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
Outputs Q0:Q3 Disabled; LOW nQ0:nQ3 Disabled; HIGH
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs EN 0 Selected Source IN1, IN2
1 IN, IN2 Enabled Enabled After EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.
Disabled
IN1, IN2 EN
Enabled
nQx Qx
FIGURE 1. EN TIMING DIAGRAM TABLE 3B. TRUTH TABLE
Inputs IN1 0 1 X X X IN2 X X 0 1 X EN 1 1 1 1 0 SEL 1 1 0 0 X 0 1 0 1 0
(1)
Outputs Q0:Q3 nQ0:nQ3 1 0 1 0 0(1)
NOTE 1: On next negative transition of the input signal (IN).
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REV. A JULY 9, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889834
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to VCC + 0.5 V cations only. Functional operation of product at 0.5V to VEE - 0.5V these conditions or any conditions beyond those 50mA 100mA 50mA 100mA -65C to 150C 51.5C/W (0 lfpm) listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current Input Current, IN, nIN VT Current, IVT Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.63V; VEE = 0V, TA = -40C TO 85C
Symbol VCC I EE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 45 Maximum 3.63 Units V mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.5V5% OR 3.3V10%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions Minimum 2 0 -125 Typical Maximum VCC + 0.3 0.8 20 -300 Units V V A A
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V5% OR 3.3V10%, TA = -40C TO 85C
Symbol VOH VOL VOUT VDIFF_OUT Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Voltage Swing Differential Output Voltage Swing Conditions Minimum VCC - 1.145 VCC - 1.945 550 1100 Typical VCC - 1.020 VCC - 1.820 800 1600 Maximum Units V V mV mV
Input and output parameters vary 1:1 with VCC. NOTE 1: Outputs terminated with 50 to VCC - 2V.
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REV. A JULY 9, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889834
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
Condition Minimum Typical >1.0 420 420 TBD TBD TBD <100 20% to 80% EN to IN1, IN2 EN to IN1, IN2 220 TBD TBD 50 Maximum Units GHz ps ps ps ps ps fs ps ps ps %
TABLE 5. AC CHARACTERISTICS, VCC = 2.5V5% OR 3.3V10%, TA = -40C TO 85C
Symbol fMAX Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, High-to-Low; NOTE 1 Switchover Time SEL to Q Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time Clock Enable Setup Time Clock Enable Hold Time Output Duty Cycle
tPLH tPHL t SW tsk(o) tsk(pp) tjit
tR/tF tS tH odc
All parameters characterized at 1GHz unless otherwise noted. NOTE 1: Measured from VCC/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
889834AK
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REV. A JULY 9, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889834
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
2V
nQx Qx nQy
VCC
Qx
SCOPE
LVPECL
nQx
VEE
Qy
tsk(o)
-0.375V to -1.63V
OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nQx PART 1 Qx nQy PART 2 Qy
tsk(pp)
VCC IN1, IN2 nQ0:nQ3 Q0:Q3 tPD 2
PART-TO-PART SKEW
PROPAGATION DELAY
80% Clock Outputs
80% VSW I N G
IN1, IN2
20% tR tF
20%
EN
t SET-UP
t HOLD
OUTPUT RISE/FALL TIME
nQ0:nQ3 Q0:Q3
SETUP & HOLD TIME
Pulse Width t
PERIOD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A JULY 9, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889834
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER APPLICATION INFORMATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50
FOUT
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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REV. A JULY 9, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889834
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
R1 250
Zo = 50 Ohm
R3 250
+
+
Zo = 50 Ohm
Zo = 50 Ohm
2,5V LVPECL Driv er
2,5V LVPECL Driv er
R1 50
R2 50
R2 62.5
R4 62.5
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A JULY 9, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889834
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS889834. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8889834 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 45mA = 163.4mW Power (outputs)MAX = 27.83mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 27.83mW = 111.3mW
Total Power_MAX (3.465, with all outputs switching) = 163.4mW + 111.3mW = 274.7mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a 0 air flow and a multi-layer board, the appropriate value is 51.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.275W * 51.5C/W = 99.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
16-PIN VFQFN, FORCED CONVECTION
JA at 0 Airflow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards 51.5C/W
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REV. A JULY 9, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4.
VCC
ICS889834
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V
OH_MAX
=V
CC_MAX
- 1.005V
(VCC_MAX - VOH_MAX) = 1.005 * For logic low, VOUT = V (V
CC_MAX
OL_MAX
=V
CC_MAX
- 1.78V
-V
OL_MAX
) = 1.78V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 1.005V)/50] * 1.005V = 20mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.78V)/50] * 1.78V = 7.83mW Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW
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REV. A JULY 9, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889834
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
16 LEAD VFQFN
JA at 0 Airflow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards 51.5C/W
TRANSISTOR COUNT
The transistor count for ICS889834 is: 259
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REV. A JULY 9, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889834
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.25 0.30 0.25 3.0 1.25 0.50 0.18 0.50 BASIC 4 4 3.0 1.25 0.80 0 0.25 Reference 0.30 MINIMUM 16 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
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REV. A JULY 9, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889834
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
Marking 834A 834A Package 16 Lead VFQFN 16 Lead VFQFN on Tape and Reel Count 120 per tube 3500 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS889834AK ICS889834AKT
The aforementioned trademarks, HiPerClockSTM , is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 889834AK
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