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Integrated Circuit Systems, Inc.
ICSSSTUA32866B
25-Bit Configurable Registered Buffer for DDR2
Recommended Application: * DDR2 Memory Modules * Provides complete DDR DIMM solution with ICS97ULP877 * Ideal for DDR2 400,533 and 667 Product Features: * 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality * Supports SSTL_18 JEDEC specification on data inputs and outputs * Supports LVCMOS switching levels on CSR# and RESET# inputs * Low voltage operation VDD = 1.7V to 1.9V * Available in 96 BGA package * Drop-in replacement for ICSSSTUA32864 * Green packages available
Pin Configuration
1 A B C D E F G H J K L M N P R T 2 3 4 5 6
Functionality Truth Table
I nputs RST# H H H H H H H H H H H H L DCS# L L L L L L H H H H H H X or Floating CSR# L L L H H H L L L H H H X or Floating L or H X or Floating L or H X or Floating L or H L or H L or H L or H L or H L or H CK CK# Dn, DODT, DCK E L H X L H X L H X L H X X or Floating Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs QCS# L L Q0 L L Q0 H H Q0 H H Q0 L QODT, QCKE L H Q0 L H Q0 L H Q0 L H Q0 L
96 Ball BGA (Top View)
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ICSSSTUA32866B
Ball Assignments
25 bit 1:1 Register
A DCKE B D2 C D3 D DODT E D5
PPO D15 D16 QERR# D17 V REF GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V REF V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V DD QCKE Q2 Q3 QODT Q5 Q6 C1 QCS# ZOH Q8 Q9 Q10 Q11 Q12 Q13 Q14 NC Q15 Q16 NC Q17 Q18 C0 NC ZOL Q19 Q20 Q21 Q22 Q23 Q24 Q25
D18 F D6 G PAR_IN RST#
H CK J CK# K D8 L D9 M D10 N D11 P D12 R D13 T D14 1
DCS# CSR# D19 D20 D21 D22 D23 D24 D25
2
3
4
5
6
C0 = 0, C1 = 0 14 bit 1:2 Registers
A DCKE B D2 C D3 D DODT E D5
PPO NC NC QERR# NC V REF GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V REF V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V DD QCKEA Q2A Q3A QODTA Q5A Q6A C1 QCSA# ZOH Q8A Q9A Q10A Q11A Q12A Q13A Q14A QCKEB Q2B Q3B QODTB Q5B Q6B C0 QCSB# ZOL Q8B Q9B Q10B Q11B Q12B Q13B Q14B
A D1 B D2 C D3 D D4 E D5
PPO NC NC QERR# NC
V REF GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V REF
V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V DD
Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA# ZOH Q8A Q9A Q10A QODTA Q12A Q13A QCKEA
Q1B Q2B Q3B Q4B Q5B Q6B C0 QCSB# ZOL Q8B Q9B Q10B QODTB Q12B Q13B QCKEB
NC F D6 G PAR_IN RST#
NC F D6 G PAR_IN RST#
H CK J K D8 L D9 M D10 N D11 P D12 R D13 T D14 1
CK#
DCS# CSR# NC NC NC NC NC NC NC
H CK J CK# K D8 L
D9
DCS# CSR# NC NC NC NC NC NC NC
M D10 N DODT P D12 R D13 T DCKE 1
2
3
4
5
6
2
3
4
5
6
Register A (C0 = 0, C1 = 1)
Register B (C0 = 1, C1 = 1)
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General Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUA32866B operates from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).
A - Pair Configuration (CO1 = 0, CI1 = 1 and CO2 = 0, CI2 = 1)
Parity that arrives one cycle after the data input to which it applies is checked on the PAR_IN of the first register. The second register produces to PPO and QERR# signals. The QERR# of the first register is left floating. The valid error information is latched on the QERR# output of the second register. If an error occurs QERR# is latched low for two cycles or until Reset# is low.
B - Single Configuration (CO = 0, C1 = 0)
The device supports low-power standby operation. When the reset input (RST#) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RST# is low all registers are reset, and all outputs are forced low. The LVCMOS RST# and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RST# must be held in the low state during power up. In the DDR-II RDIMM application, RST# is specified to be completely asynchronous with respect to CK and CK#. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST# until the input receivers are fully enabled, the design of the ICSSSTUA32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS# and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RST input has priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is not desired, then the CSR# input can be hardwired to ground, in which case, the setup-time requirement for DCS# would be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).
Parity and Standby Functionality Truth Table
Inputs
Rst# H H H H H H H H L DCS# L L L L H H H X CSR# X X X X L L H X CK L or H CK# L or H X or Floating Sum of Inputs = H (D1 - D25) Even Odd Even Odd Even Odd X X X or Floating PAR_IN L L H H L H X X X or Floating
Outputs
PPO L H H L L H PPO0 PPO0 L QERR# H L L H H L QERR0# QERR0# H
X or X or X or Floating Floating Floating
1. CO = 0 and CI = 0, Data inputs are D2, D3, D5, D6, D8 - D25. CO = 0 and CI = 1, Data inputs are D2, D3, D5, D6, D8 - D14 CO = 1 and CI = I, Data inputs are D1 - D6, D8 - D10, D12, D13 2. PAR_IN arrives one clock cycle after the data to which it applies when CO = 0. 3. PAR_IN arrives two clock cycles after the data to which it applies when CO = 1. 4. Assume QERR# is high at the CK and CK# crossing. If QERR# is low it stays latched low for two clock cycles on until Rst# is low.
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Ball Assignment
Terminal Name GND VDD VREF ZOH ZOL CK CK C0, C1 RST# CSR#, DCS# D1 - D25 DODT DCK E Q1 - Q25 QCS# QODT QCKE PPO PAR_IN QERR# Ground Power supply voltage Input reference voltage Reserved for future use Reserved for future use Positive master clock input Negative master clock input Configuration control inputs Asynchronous reset input - resets registers and disables VREF data and clock differential-input receivers Description Electrical Characteristics Ground input 1.8V nominal 0.9V nominal Input Input Differential input Differential input LVCMOS inputs LV C M O S i n p u t
Chip select inputs - disables D1 - D24 outputs switching when both inputs SSTL_18 input are high Data input - clock in on the crossing of the rising edge of CK and the falling edge of CK# The outputs of this register bit will not be suspended by the DCS# and CSR# control The outputs of this register bit will now be suspended by the DCS# and CSR# control Data ouputs that are suspended by the DCS# and CSR# control Data output that will not be suspended by the DCS# and CSR# control Data output that will not be suspended by the DCS# and CSR# control Data output that will not be suspended by the DCS# and CSR# control Par tial parity out indicates off parity of inputs D1 - D25. Parity input arrives one clock cycle after the corresponding data input Output error bit-generated one clock cycle after the corresponding data output SSTL_18 input SSTL_18 input SSTL_18 input 1.8V CMOS 1.8V CMOS 1.8V CMOS 1.8V CMOS 1.8V CMOS SSTL_18 input Open drain output
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Block Diagram for 1:1 mode (positive logic)
RST#
CK CK# VREF
DCKE
D C1 R QCKEA
DODT
D C1 R QODTA
DCS#
1D C1 R QCSA#
CSR#
D1
0 1 1D C1 R Q1B*
Q1A
To 21 Other Channels
*Note: Disabled in 1:1 configuration
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Block Diagram for 1:2 mode (positive logic)
RST#
CK CK# VREF
DCKE
1D C1 R
QCKEA
QCKEB*
DODT
1D C1 R
QODTA
QODTB*
DCS#
1D C1 R
QCSA#
QCSB#*
CSR#
D1
0 1 1D C1 R Q1B*
Q1A
To 10 Other Channels
*Note: Disabled in 1:1 configuration
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2. Device standard (cont'd)
G2 H1 J1 LPS0 (internal node) D2*D3, D5*D6, D8-D25 V REF 22 A3, T3 D R 22 D2*D3, D5*D6, D8*D25 CE CK Q D2*D3, D5*D6, D8*D25 22
RST# CK CK#
22
Q2*Q3, Q5*Q6, Q8*Q25
Parity Generator
C1
G5
0 D CK R PAR_IN G1 R Q 1 D CK CE R Q D CK Q
1 0
A2 PPO
D2 QERR#
C0
G6
CK 2*Bit Counter R
LPS1 (internal node)
0 D CK R Q 1
Figure 6 -- Parity logic diagram for 1:1 register configuration (positive logic); C0=0, C1=0
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2. Device standard (cont'd)
G2 H1 J1 LPS0 (internal node) D2 D3, 11 D5 D6, D8-D14 A3, T3 V REF D2 D3, D5 D6, D8 D14 Q 11 11 D2 D3, D5 D6, D8 D14 11 Q2B Q3B, Q5B Q6B, Q8B Q14B 11 Q2A Q3A, Q5A Q6A, Q8A Q14A
RST# CK CK#
D R
CE CK
Parity Generator
G5 C1 0 D CK R G1 PAR_IN D2 QERR# R CE Q 1 D CK R Q D CK Q 1 0
A2 PPO
C0
G6
CK 2 Bit Counter R
LPS1 (internal node)
0 D CK R Q 1
Figure 7 -- Parity logic diagram for 1:2 register-A configuration (positive logic); C0=0, C1=1
Figure 7 -- Parity logic diagram for 1:2 register-A configuration (positive logic); C0=0, C1=1
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2. Device standard (cont'd)
G2 H1 J1 LPS0 (internal node) D1*D6, D8-D13 V REF A3, T3 11 D R 11 D1*D6, D8*D13 CE CK Q 11 11 Q1B*Q6B, Q8B*Q13B D1*D6, D8*D13 11 Q1A*Q6A, Q8A*Q13A
RST# CK CK#
Parity Generator
C1
G5
0 D CK R PAR_IN G1 R Q 1 D CK CE R Q D CK Q
1 0
A2 PPO
D2 QERR#
C0
G6
CK 2*Bit Counter R
LPS1 (internal node)
0 D Q CK R 1
Figure 8 -- Parity logic diagram for 1:2 register-B configuration (positive logic); C0=1, C1=1
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2. Device standard (cont'd)
RST#
DCS#
CSR#
n CK
n+1
n+2
n+ 3
n +4
CK#
t act
tsu
th
D1*D25 tpdm , t pdmss CK to Q Q1*Q25 t su PAR_IN tpd CK to PPO PPO tPHL CK to QERR# t PHL , t PLH CK to QERR# th
QERR#
Data to QERR# Latency
H, L, or X
H or L
Figure 9 -- Timing diagram for SSTU32866 used as a single device; C0=0, C1=0; RST# Switches from L to H
After RST# is switched fro max, to avoid false error. low to high, al data and PAR_IN inputs signals must be se and held lo for a minimum time of tACT
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse.
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2. Device standard (cont'd)
RST#
DCS#
CSR#
n CK
n+1
n+2
n+3
n +4
CK#
tsu
th
D1*D25 tpdm , t pdmss CK to
Q1*Q25 tsu PAR_IN tpd CK to PPO PPO Data to PPO Latency QERR# Data to QERR# Latency tPHL or t PLH CK to QERR# th
Unknown input event
Output signal is dependent on the prior unknown input event
H or L
Figure 10 -- Timing diagram for SSTU32866 used as a single device; C0=0, C1=0; RST# being held high
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. If an error occurs and the QERR# output is driven low, it stays latched low for a minimum of two clock cycles or until RST# is driven low.
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2. Device standard (cont'd)
RST#
tinact DCS#
CSR#
CK
CK#
D1*D25 tRPHL RST# to Q Q1*Q25
PAR_IN t RPHL RST# to PPO PPO
QERR# tRPLH RST# to QERR#
H, L, or X
H or L
Figure 11 -- Timing diagram fo SSTU32866 used as a single device; C0=0, C1=0; RST# switches from H to L
After RST# is switched from high to low, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time of tINACT max
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2. Device standard (cont'd)
RST#
DCS#
CSR#
n CK
n+1
n+2
n+3
n +4
CK#
t act D1*D14
tsu
th
tpdm , t pdmss CK to Q Q1*Q14 tsu PAR_IN t pd CK to PPO PPO t PHL CK to QERR# QERR# (not used) t PHL , t PLH CK to QERR# th
Data to QERR# Latency
H, L, or X
H or L
Figure 12 -- Timing diagram for the firs SSTU32866 (1:2 register-A configration) device used in pair; C0 = 0, C1 = 1; RST# switches from L to H
After RST# is switched fro max, to avoid false error low to high, al data and PAR_IN inputs signals must be se and held lo for a minimum time of tACT
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse.
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2. Device standard (cont'd)
RST#
DCS#
CSR#
n CK
n+1
n+2
n+ 3
n +4
CK#
t su
th
D1*D14 tpdm , t pdmss CK to Q
Q1*Q14 tsu PAR_IN tpd CK to PPO PPO Data to PPO Latency QERR# (not used) Data to QERR# Latency tPHL or t PLH CK to QERR# th
Unknown input event
Output signal is dependent on the prior unknown input event
H or L
Figure 13 -- Timing diagram for the firs SSTU32866 (1:2 register-A configration) device used in pair; C0 = 0, C1 = 1; RST# bein held high
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse. If an error occurs and the QERR# output is driven low, it stays latched low for a minimum of two clock cycles or until RST# is driven low.
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2. Device standard (cont'd)
RST#
tinact DCS#
CSR#
CK
CK#
D1*D14 tRPHL RST# to Q Q1*Q14
PAR_IN t RPHL RST# to PPO PPO
QERR# (not used) t RPLH RST# to QERR#
H, L, or X
H or L
Figure 14 -- Timing diagram for the firs SSTU32866 (1:2 register-A configration) device used in pair; C0 = 0, C1 = 1; RST# switches from H to L
After RST# is switched from high to low, all data and clock inputs signals must be held at valid logic levels (not floating) for a minimum time of tINACT max
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2. Device standard (cont'd)
RST#
DCS#
CSR#
n CK
n +1
n +2
n+3
n+4
CK#
tact D1*D14
t su
th
t pdm , t pdmss CK to Q Q1*Q14 t su PAR_IN tpd CK to PPO PPO (not used) t PHL CK to QERR# tPHL , t PLH CK to QERR# th
QERR# Data to QERR# Latency
H, L, or X
H or L
Figure 15 -- Timing diagram for the second SSTU32866 (1:2 register-B configration) device used in pair; C0 = 1, C1 = 1; RST# switches from L to H
After RST# switched fro max, to avoid false error low to high, al data and PAR_IN inputs signals must be se and held lo for a minimum time of tACT

PAR_IN is driven from PPO of the first SSTU32866 device If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse.
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2. Device standard (cont'd)
RST#
DCS#
CSR#
n CK
n+1
n+2
n+3
n+4
CK#
t su
t h
D1 D14 t t pdm , pdmss CK to Q
Q1 Q14 t su PAR_IN t pd CK to PPO PPO Data to PPO Latency QERR# (not used) Data to QERR# Latency t t PHL or PLH CK to QERR# t h
Unknown input event
Output signal is dependent on the prior unknown input event
H or L
Figure 16 -- Timing diagram for the second SSTU32866 (1:2 register-B configration) device used in pair; C0 = 1, C1 = 1; RST# being held high
PAR_IN is driven from PPO of the first SSTU32866 device If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. If an error occurs and the QERR# output is driven low, it stays latched low for a minimum of two clock cycles or until RST# is driven low.
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2. Device standard (cont'd)
RST#
t inact DCS#
CSR#
CK
CK#
D1*D14 t RPHL RST# to Q Q1*Q14
PAR_IN tRPHL RST# to PPO PPO (not used)
QERR# tRPLH RST# to QERR#
H, L, or X
H or L
Figure 17 -- Timing diagram for the second SSTU32866 (1:2 register-B configration) device used in pair; C0 = 1, C1 = 1; RST# switches from H to L
After RST# is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) fo a minimum time of t INACT max
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* Register Configurations
DATA INPUT: D2, D3, D5, D6, D8 - D25 D2, D3, D5, D6, D8 - D14 D1 - D6, D8 D10, D12, D13 DATA OUTPUT: D2, D3, D5, D6, D8 - D25 D2, D3, D5, D6, D8 - D14 D1 - D6, D8 D10, D12, D13 CO 0 CI 0
0
1
1
1
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Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clamp Current . . . . . . . . . . . . . . . . . . . . Output Clamp Current . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . VDD or GND Current/Pin . . . . . . . . . . . . . . . . Package Thermal Impedance3
...............
-65C to +150C -0.5V to 2.5V -0.5V to +2.5V -0.5V to VDD + 0.5V 50 mA 50mA 50mA 100mA 36C
Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This value is limited to 2.5V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Recommended Operating Conditions
PARAMETER VDDQ VREF VTT VI VIH (DC) VIH (AC) VIL (DC) VIL (AC) VIH VIL VICR VID IOH IOL TA
1
DESCRIPTION I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage Input High Voltage Level RST#, C0, C1 Input Low Voltage Level Common mode Input Range CK, CK# Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature
MIN TYP 1.7 1.8 0.49 x VDD 0.5 x VDD V REF - 0.04 VREF 0 VREF + 0.125 VREF + 0.250
MAX 1.9 0.51 x V DD VREF + 0.04 VDDQ
UNITS
VREF - 0.125 VREF - 0.250 0.65 x VDDQ 0.675 0.600 0.35 x VDDQ 1.125 -8 8 70
V
mA C
0
Guaranteed by design, not 100% tested in production. Note: Rst# and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless Rst# is low.
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Electrical Characteristics - DC
TA = 0 - 70C; VDD = 1.8 +/-0.1V (unless otherwise stated) SYMBOL PARAMETERS VIK VOH VOL All Inputs II Standby (Static) I DD Operating (Static) CONDITIONS VDD 1.7V 1.7V 1.9V 1.9V 40 39 MIN 1.2 -5 0.5 5 100 TYP I I = -18mA I OH = -6mA I OL = 6mA V I = VDD or GND RESET# = GND V I = VIH(AC) or VIL(AC), RESET# = V DD RESET# = V DD, Dynamic operating V I = VIH(AC) or V IL(AC), (clock only) CLK and CLK# switching 50% duty cycle. IO = 0 Dynamic Operating RESET# = V DD, (per each data input) V I = VIH(AC) or V IL (AC), CLK and CLK# switching 1:1 mode 50% duty cycle. One data Dynamic Operating input switching at half (per each data input) clock frequency, 50% 1:2 mode duty cycle V I = VREF 350mV Data Inputs V ICR = 1.25V, VI(PP) = 360mV CLK and CLK# RESET# V I = VDD or GND MAX -1.2 UNITS V A A mA
/clock MHz
IDDD
1.8V
19 A/ clock MHz/data 35 2.5 2 2.5 3.5 3
Ci
pF
Notes: 1 - Guaranteed by design, not 100% tested in production.
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7) VDD = 1.8V 0.1V PARAMETER UNIT MIN MAX dV/dt_r 1 4 V/ns dV/dt_f 1 4 V/ns 1 dV/dt_ 1 V/ns 1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
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Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted) SYMBOL f clock tW t ACT tINACT t su t su t su t su t su tH Notes: Clock frequency Pulse duration, CK, CK HIGH or LOW Differential inputs active time (See Notes 1 and 2) Differential inputs inactive time (See Notes 1 and 3) Setup time Setup time Setup time Setup time Setup time Hold time DSR# before CK, CK#, CSR# high CSR# before CK, CK#, DCS# high DCS# before CK, CK#, CSR# low DODT, DCKE and data before CK, CK# PAR_IN before CK, CK# DCS#, DODT, DCKE and Q after CK, CK# PARAMETERS VDD = 1.8V 0.1V MIN MAX 410 1 0.7 0.7 0.5 0.5 0.5 0.50 0.50 10 15 UNITS MHz ns ns ns ns ns ns ns ns ns ns
PAR_IN after CK, CK# Hold time 1 - Guaranteed by design, not 100% tested in production. 2 - For data signal input slew rate of 1V/ns. 3 - For data signal input slew rate of 0.5V/ns and < 1V/ns. 4 - CLK/CLK# signal input slew rate of 1V/ns.
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted) Measurement Symbol Parameter MIN MAX Conditions fmax t PDM Max input clock frequency 410 1.1 0.5 1.2 1 1.9 1.8 3 2.4 2 3 3 3 Units MHz ns ns ns ns ns ns ns ns
Propagation delay, single CK to CK# QN bit switching Propagation delay CK to CK# to PPO t PD Low to High propagation t LH CK to CK# to QERR# delay High to low propagation t HL CK to CK# to QERR# delay Propagation delay CK to CK# QN t PDMSS simultaneous switching High to low propagation t PHL Rst# to QN delay High to low propagation Rst# to PPO t PHL delay Low to High propagation t PLH Rst# to QERR# delay 2. Guaranteed by design, not 100% tested in production.
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ICSSSTUA32866B
VDD
DUT TL=50 * CK Inputs Test Point RL = 100 * Test Point VCMOS RST# Inp ut t in act IDD (see Note 2) LOAD CIRCUIT VDD VDD /2 VDD/2 0V t act 90% 10% VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES tw Inpu t VICR VICR LVCMOS RST# Input VIH VDD /2 t RPHL t su Inpu t VREF th VREF VIH VOH Ou tput VTT VOL VIL VID Ou tput VTT VTT CK VICR CK t PL H t PH L VOH VOL VIC R CK# CK TL=350p s, 50 Out CL = 30 pF (see Note 1) RL = 1000 * Test Point RL = 1000 *
VID
VOLTAGE WAVEFORMS - PROPAGATION DELA TIMES
VOLTAGE WAVEFORMS - PULSE DURATION VID CK VICR CK
VIL VOLTAGE WAVEFORMS - SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS - PROPAGATION DELA TIMES
Figure 6 -- Parameter M easurement I nfor mation (V DD = 1.8 V 0.1 V)
Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR 10 MHz, Zo=50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VREF = VDD/2 6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600 mV 9. tPLH and tPHL are the same as tPDM.
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ICSSSTUA32866B
VDD DUT RL = 50 Out C L = 10 pF (see Note 1) Test Point
LOAD CIRCUIT - HIGH-TO-LOW SLEW-RATE MEASUREMENT Output 80% 20% dv _f dt _f VOL VOH
VOLTAGE WAVEFORMS - HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
Out CL = 10 pF (see Note 1)
Test Point RL = 50
LOAD CIRCUIT - LOW-TO-HIGH SLEW-RATE MEASUREMENT dv _r dt _r 80% 20% Output VOL VOLTAGE WAVEFORMS - LOW-TO-HIGH SLEW-RATE MEASUREMENT VOH
Figure 7 -- Output Slew-Rate M easurement I nfor mation (V DD = 1.8 V 0.1 V)
Notes: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified).
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ICSSSTUA32866B
3 Test circuits and switching waveforms (cont'd) 3.3 Error output load circuit and voltage measurement information (VDD = 1.8 V 0.1 V) All input pulses are supplied by generators having the following characteristics: PRR Zo = 50 ; input slew rate = 1 V/ns 20%, unless otherwise specified. 10 MHz;
VDD DUT RL = 1K Out CL = 10 pF (see Note 1) Test Point
LOAD CIRCUIT - HIGH-TO-LOW SLEW-RATE MEASUREMENT (1) CL includes probe and jig capacitance.
Figure 28 -- Load circuit, error output measurements
LVCMOS RST# Input t PLH Output Waveform 2
V CC V CC /2 0V V OH 0.15 V ___________ 0V
Figure 29 -- Voltage waveforms, open-drain output low-to-high transition time with respect to reset input
V I(PP) Timing Inputs tPHL Output Waveform 1 VICR V ICR
___________
V CC /2
V CC V OL
Figure 30 -- Voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs
V I(PP) Timing Inputs tPHL Output Waveform 2 V OH 0.15 V 0V VICR VICR
Figure 31 -- Voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs
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ICSSSTUA32866B
Test circuits and switching waveforms (cont'd) 3.4 Partial-parity-out load circuit and voltage measurement information (VDD = 1.8 V 0.1 V) All input pulses are supplied by generators having the following characteristics: PRR Zo = 50 input slew rate = 1 V/ns 20%, unless otherwise specified. 10 MHz;
DUT
Out
Test Point
CL = 5 pF (see Note A) RL = 1 k
(1) CL includes probe and jig capacitance.
Figure 32 -- Partial-parity-out load circuit,
CK VICR CK tPLH tPHL VOH OUTPUT VTT VOL
002aaa375
VICR
Vi(p-p)
VTT = VDD /2 tPLH an tPHL are the same as tPD . VI(PP) = 600 mV
Figure 33 -- Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs
LVCMOS RST# VIH INPUT VDD/2 VIL tPHL VOH OUTPUT VTT
002aaa376
VOL
VTT = VDD /2 tPLH an tPHL are the same as tPD . VIH = VRE F + 250 mV (AC voltage levels for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VRE F 250 mV (A voltag levels) for differential inputs. VIL = VDD for LVCMOS inputs.
Figure 34 -- Partial-parity-out voltage waveforms; propagation delay times with respect to reset input
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ICSSSTUA32866B
C Seating Plane A1 T b REF Numeric Designations for Horizontal Grid 4321 A B C D
D
Alpha Designations for Vertical Grid (Letters I, O, Q & S not used)
d TYP D1 - e - TYP TOP VIEW
E
h TYP 0.12 C
c REF E1
- e - TYP
ALL DIMENSIO NS IN MILLIMETERS
----- BALL GRID ----Max. T e HORIZ VERT TOTAL d Min/Max Min/Max 13.50 Bsc 5.50 Bsc 1.30/1.50 0.80 Bsc 6 16 96 0.40/0.50 11.50 Bsc 5.00 Bsc /1.20 0.65 Bsc 6 16 96 0.38/0.48 Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. D E
h Min/Max 0.25/0.41 0.27/0.37
REF. DIMENSIONS b c 0.75 0.875 0.75 0.875
* Source Ref.: JEDEC Publication 95, 10-0055C
MO-205
Ordering Information
ICSSSTUA32866Bz(LF)T
Example:
ICS XXXX y z (LF) T
Designation for tape and reel packaging Lead Free (Optional) Package Type H = LFBGA (standard size: 5.5 x 13.50) HM = TFBGA (reduced size: 5.0 x 11.50) Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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