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CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
FEATURES:
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IDT723616
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Two independent FIFOs (64 X 36 storage capacity each) buffer data between bidirectional 36-bit port A and two unidirectional 18/9-bit ports (Port B transmits, Port C receives) Clock frequencies up to 67 MHz (10 ns access time) Free-running clock lines for each port: CLKA, CLKB and CLKC, may be asynchronous or coincident (simultaneous reading and writing of data is permitted) IDT Standard timing Empty flag functions: EFA (synchronized by CLKA) and EFB (synchronized by CLKB) Full flag functions: FFA (synchronized by CLKA) and FFC (synchronized by CLKC) Programmable Almost-Empty and Almost-Full flags; each has four default offsets (4, 8, 12 and 16) Bus sizing of 18-bits (word) and 9-bits (byte) for ports B and C Byte order swapping on ports B and C Passive parity checking on ports A and C Parity generation can be selected for ports A and B Master Reset clears data and configures FIFO
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Width can be easily expanded by adding FIFOs Auto power down minimizes power dissipation Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) High performance sub-micron CMOS technology Industrial temperature range (-40oC to +85oC) is available
DESCRIPTION:
The IDT723616 is a monolithic, high-speed, low-power, CMOS Triple Bus SyncFIFOTM (clocked) memory which supports clock frequencies up to 67 MHz and has read access times as fast as 10 ns. Two independent 64 x 36 dual-port SRAM FIFOs on board each chip buffer data between a bidirectional 36-bit bus (Port A) and two unidirectional 18-bit buses (Port B transmits data, Port C receives data.) FIFO data can be read out of ports B and written into port C using either 18-bit or 9-bit formats. Reset (RST) initializes the read and write pointers to the first location of the memory array and selects one of four possible default flag offset settings: 4, 8, 12 or 16. Each FIFO has flags to indicate empty and full conditions and two programmable flags (Almost-Full and Almost-Empty) to indicate when a selected number of words is stored in memory. Data on Port B can be accessed in 18-
FUNCTIONAL BLOCK DIAGRAM
CLKA CSA W/RA ENA PEFA
Bus Matching and Byte Swapping
Parity Generation
Input Register
RAM ARRAY 64 x 36
Output Register
Port-A Control Logic Parity check
PGB
18
B0 - B17 CLKB RENB
Port-B Control Logic
Write Pointer
36
Read Pointer Status Flag Logic Common Port Control Logic (B and C) EFB AEB SWB0 SWB1 SWC0 SWC1 SIZ0 SIZ1 FFC AFC
FFA AFA
FIFO 1
FS0 FS1 A0 - A35 EFA AEA
FIFO 2
Programmable Flag Offset Registers
Status Flag Logic Read Pointer Write Pointer
Parity Generation
ODD/EVEN
Output Register
Input Register
RAM ARRAY 64 x 36
Bus Matching and Byte Swapping
RST
FIFO2, FIFO1 Reset/ Control Logic
36
Parity Check
PEFC
18
C0 - C17 CLKC WENC
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Port-C Control Logic
PGA
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
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(c) 2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MARCH 2002
DSC-3107/1
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
bit and 9-bit formats. FIFO Data on Port C can be input in 18-bit and 9-bit formats. Byte-order swapping on ports B and C is possible with any bus size selection. Parity is checked passively on ports A and C and may be ignored if not desired. Parity generation can be selected for data read from ports A and B. Two or more devices can be used in parallel to create wider or deeper FIFO configurations.
This device is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOWto-HIGH transition of a continuous (free-running) port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses controlled by a synchronous interface.
PIN CONFIGURATION
GND A27 A28 A29 GND Vcc A30 A31 A32 A33 A34 A35 GND B17 B16 B15 B14 B13 B12 GND Vcc B11 B10 B9 Vcc GND
INDEX
CLKA W/RA NC Vcc PGA PEFA NC SWC1 FS1 FS0 ODD/EVEN RST GND NC SWC0 SWB1 SWB0 SIZ1 SIZ0 NC PEFC PGB Vcc NC CLKC CLKB
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Vcc A26 A25 A24 A23 A22 A21 GND A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 GND A9 A8 A7 Vcc A6 A5 A4 A3 GND A2 A1 A0 EFA AEA AFA FFA CSA ENA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
NC B8 B7 B6 B5 B4 B3 GND B2 B1 B0 C17 C16 C15 C14 C13 C12 C11 C10 GND C9 C8 C7 Vcc C6 C5 C4 C3 GND C2 C1 C0 EFB AEB AFC FFC RENB WENC
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NOTE: 1. NC - No internal connection.
TQFP (PK128-1, ORDER CODE: PF) TOP VIEW
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IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
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This FIFO employs IDT Standard Mode timing; that is to say, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). Each FIFO has an Empty Flag (EFA and EFB) and a Full Flag (FFA and FFC). EF indicates whether or not the FIFO memory is empty. FF shows whether the memory is full or not. Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a programmable Almost-Full flag (AFA and AFC). AEA and AEB indicate when a selected number of words written to FIFO memory achieve a predetermined "almost-empty state". AFA and AFC indicate when a selected number of words written to the memory achieve a predetermined "almost-full state". FFA, FFC, AFA and AFC are two-stage synchronized to the port clock that writes data into its array. EFA, EFB, AEA, and AEB are two-stage synchronized
to the port clock that reads data from its array. Four default offset settings are also provided. The AEA and AEB threshold can be set at 4, 8, 12 or 16 locations from the empty boundary and the AFA and AFC threshold can be set at 4, 8, 12 or 16 locations from the full boundary. All these choices are made using the FS0 and FS1 inputs during Reset. Two or more FIFOs may be used in parallel to create wider data paths. Such a width expansion requires no additional, external components. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption (ICC) is at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the Power Down state. The IDT723616 are characterized for operation from 0C to 70C. They are fabricated using IDT's high speed, submicron CMOS technology.
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IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
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PIN DESCRIPTION
Symbol A0-A35 AEA AEB AFA AFC B0-B17 C0-C17 CLKA Name Port A Data Port A Almost-Empty Flag Port B Almost-Empty Flag Port A Almost-Full Flag Port C Almost-Full Flag Port B Data. Port-C Data Port A Clock I/O I/O O O O O O I I Description 36-bit bidirectional data port for side A. Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of 36-bit words in FIFO2 is less than or equal to the value in the offset register, X. Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of 36-bit words in FIFO1 is less than or equal to the value in the offset register, X. Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty locations in FIFO1 is less than or equal to the value in the offset register, X. Programmable Almost-Full flag synchronized to CLKC. It is LOW when the number of 36-bit empty locations in FIFO2 is less than or equal to the value in the offset register, X. 18-bit output data port for side B. 18-bit input data port for side C. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB and CLKC. EFA, FFA, AFA, and AEA are synchronized to the LOW-to-HIGH transition of CLKA. CLKB is a continuous clock that synchronizes all data read from port B and can be asynchronous or coincident to CLKA and CLKC. Port B byte swapping and data port sizing operations are also synchronous to the LOW-to-HIGH transition of CLKB. EFB and AEB are synchronized to the LOW-to-HIGH transition of CLKB. CLKC is a continuous clock that synchronizes all data written to port C and can be asynchronous or coincident to CLKA and CLKC. FFC and AFC are synchronized to the LOW-to-HIGH transition of CLKC. CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is LOW, FIFO2 is empty, and reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory. EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is LOW, the FIFO1 is empty, and reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory. ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is LOW, FIFO1 is full, and writes to its memory are disabled. FFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after reset. FFC is synchronized to the LOW-to-HIGH transition of CLKC. When FFC is LOW, FIFO2 is full, and writes to its memory are disabled. FFC is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKC after reset. The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which selects one of four preset values for the Almost-Full flag and Almost-Empty flag offset. Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled for a read operation. When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA. Therefore, if a mail2 read parity generation is setup by having W/RA LOW, and PGA HIGH, the PEFA flag is forced HIGH regardless of the A0-A35 inputs.
CLKB
Port B Clock
I
CLKC
Port-C Clock
I
CSA EFA
Port A Chip Select Port A Empty Flag
I O
EFB
Port B Empty Flag
O
ENA FFA FFC
Port A Enable Port A Full Flag
I O
Port C Full Flag
O
FS1, FS0 ODD/ EVEN PEFA
Flag-Offset Selects Odd/Even Parity Select Port A Parity Error Flag
I I
O
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IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Symbol PEFC Name Port C Parity Error Flag I/O O Description When any valid byte applied to terminals B0-B17 fails parity, PEFC is LOW. Bytes are organized as B0-B8 and B9-B17 with the most significant bit of each byte serving as the parity bit. A byte is valid when it is used by the bus size selected for Port C. The type of parity checked is determined by the state of the ODD/ EVEN input. The parity trees used to check the B0-B17 inputs are shared by the mail 1 register to generate parity if parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having WENC LOW, SIZ1 and SIZ0 HIGH, and PGB HIGH, the PEFC flag is forced HIGH regardless of the state of the B0-B17 inputs. Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte. Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8 and B9-B17. The generated parity bits are output in the most significant bit of each byte. RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on port B. To reset the device, four LOW-to-HIGH transitions of CLKA, four LOW-to-HIGH transitions of CLKB, and four LOW-to-HIGH transitions of CLKC must occur while RST is LOW. This sets the AFA and AFC flags HIGH and the EFA, EFB, AEA, AEB, FFA, and FFC flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select Almost-Full and AlmostEmpty flag offsets. The levels on these inputs determine the bus size for ports B and C . These levels must be stable before Master Reset and must remain static for the duration of FIFO operation. Either a word or a byte size may be selected for both ports B and C together; the ports cannot be configured independently. The levels on these inputs select one of four modes of byte-order swapping for Port B. These levels must be stable before Master Reset and must remain static for the duration of FIFO operation. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is possible with any bus size selection. The levels on these inputs select one of four modes of byte-order swapping for Port C. These levels must be stable before Master Reset and must remain static for the duration of FIFO operation. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is possible with any bus size selection. A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH. A HIGH selects a Port C write operation for a LOW-to-HIGH transition of CLKC.
PGA
Port A Parity Generation Port B Parity Generation Port B Read Enable Reset
I
PGB
I
RENB RST
I I
SIZ0, SIZ1
Bus Size Select (Ports B and C)
I
SWB0 SWB1
Port B Byte Swap
I
SWC0
Port C Byte Swap
I
W/RA WENC
Port A Write/Read Select Port C Write Enable
I I
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IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(1)
Symbol VCC VI
(2) (2)
Rating Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current, (VI < 0 or VI > VCC) Output Clamp Current, (VO < 0 or VO > VCC) Continuous Output Current, (VO = 0 to VCC) Continuous Current Through VCC or GND Storage Temperature Range
Commercial -0.5 to 7 -0.5 to VCC+0.5 -0.5 to VCC+0.5 20 50 50 500 -65 to 150
Unit V V V mA mA mA mA C
VO
IIK IOK IOUT ICC, IGND TSTG
NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIH VIL IOH IOL TA Parameter Supply Voltage HIGH Level Input Voltage LOW-Level Input Voltage HIGH-Level Output Current LOW-Level Output Current Operating Free-air Temperature Min. 4.5 2 -- -- -- 0 Max. 5.5 -- 0.8 -4 8 70 Unit V V V mA mA C
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
IDT723616 Commercial & Industrial(1) tA = 15, 20 ns Parameter VOH VOL II IOZ ICC(3) CIN COUT VCC = 4.5V, IOH = -4 mA VCC = 4.5 V, IOL = 8 mA VCC = 5.5 V, VI = VCC or 0 VCC = 5.5 V, VO = VCC or 0 VCC = 5.5 V, IO = 0 mA, VI = VCC or GND VI = 0, f = 1 MHz VO = 0, f = 1 MHz Test Conditions Min. 2.4 -- -- -- -- -- -- Typ.(1) -- -- -- -- -- 4 8 Max. -- 0.5 50 50 1 -- -- Unit V V A A mA pF pF
NOTES: 1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order. 2. All typical values are at VCC = 5V, TA = 25C. 3 For additional ICC information, see following page.
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IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
400 VCC = 5.5V 350 f data = 1/2 f s T A = 25 C C L = 0 pF VCC = 5V
300
VCC = 4.5V
Supply Current ICC(f)
mA
250
200
150
100
50
0 0 10 20 30 40 50 60 70 80
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fs Clock Frequency MHz
Figure 1. Typical Characteristics: Supply Current vs Clock Frequency
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723616 with CLKA and CLKB set to fs. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation below. With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT723616 can be calculated by: PT = VCC x ICC(f) + (CL x VOH2 x fo) where: = CL fo = VOH = output capacitance load switching frequency of an output output high level voltage
When no reads or writes are occurring on the IDT723616, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is calculated by: PT=VCC x fS x 0.290 mA/MHz
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IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C; Industrial; VCC = 5.0V 10%,TA = 40C to +85C) Commercial Symbol fS tCLK tCLKH tCLKL tDS tENS tSZS tSWS tPGS tRSTS tFSS tDH tENH tSZH tSWH tPGH tRSTH tFSH tSKEW1
(4)
Com'l & Ind'l(1) IDT723616L20 Min. Max. - 20 8 8 5 5 5 7 5 6 6 1 1 2 0 0 6 4 8 16 50 - - - - - - - - - - - - - - - - - - - Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter Clock Frequency, CLKA, CLKB, or CLKC Clock Cycle Time, CLKA, CLKB, or CLKC Pulse Duration, CLKA, CLKB, and CLKC Pulse Duration, CLKA, CLKB, and CLKC Setup Time, A0-A35 before CLKA and C0-C17 before CLKC Setup Time, CSA, W/RA, and ENA before CLKA; RENB before CLKB; WENC before CLKC Setup Time, SIZ0 and SIZ1 before CLKB and CLKC Setup Time, SWB0 and SWB1 before CLKB, SWCO and SWC1, before CLKC Setup Time, ODD/EVEN and PGA before CLKA; ODD/EVEN and PGB before CLKB(2) Setup Time, RST LOW before CLKA, CLKB, or CLKC(3) Setup Time, FS0 and FS1 before RST HIGH Hold Time, A0-A35 after CLKA and C0-C17 after CLKC Hold Time, CSA, W/RA, and ENA after CLKA; RENB after CLKB; WENB after CLKC Hold Time, SIZ0 and SIZ1 after CLKB and CLKC Hold Time, SWB0 and SWB1 after CLKB, SWC0 and SWC1 after CLKC Hold Time, ODD/EVEN and PGA after CLKA; ODD/EVEN and PGB after CLKB(2) Hold Time, RST LOW after CLKA, CLKB or CLKC(2) Hold Time, FS0 and FS1 after RST HIGH Skew Time, between CLKA and CLKB for EFB and FFA; between CLKC and CLKA for EFA and FFC Skew Time, between CLKA and CLKB for AEB and AFA; between CLKC and CLKA for AEA and AFC
IDT723616L15 Min. Max. - 15 6 6 4 5 4 5 4 5 5 1 1 2 0 0 5 4 8 14 66.7 - - - - - - - - - - - - - - - - - - -
tSKEW2(4)
NOTES: 1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Only applies for a clock edge that does a FIFO read. 3. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationships among CLKA cycle, CLKB cycle and CLKC.
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IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C; Industrial; VCC = 5.0V 10%,TA = 40C to +85C)
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF
Commercial Symbol tA tWFF tREF tPAE tPAF tPPE(2) tPDPE tPOPE tPEPE tEN tDIS Parameter Access Time, CLKA to A0-A35 and CLKB to B0-B17 Propagation Delay Time, CLKA to FFA and CLKC to FFC Propagation Delay Time, CLKA to EFA and CLKB to EFB Propagation Delay Time, CLKA to AEA and CLKB to AEB Propagation Delay Time, CLKA to AFA and CLKC to AFC Propagation delay time, CLKB to PEFB Propagation Delay Time, A0-A35 valid to PEFA valid; C0-C17 valid to PEFC valid Propagation Delay Time, ODD/EVEN to PEFA and PEFC Propagation Delay Time, W/RA or PGA to PEFA Enable Time, CSA and W/RA LOW to A0-A35 active and RENB HIGH to B0-B17 active Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and RENB LOW to B0-B17 at high-impedance IDT723616L15 Min. Max. 2 2 2 2 2 2 2 2 1 2 1 10 10 10 10 10 10 10 10 10 10 8 Com'l & Ind'l(1) IDT723616L20 Min. Max. 2 2 2 2 2 2 2 2 1 2 1 12 12 12 12 12 12 11 12 12 12 9 Unit ns ns ns ns ns ns ns ns ns ns ns
NOTE: 1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Only applies when a new port B bus size is implemented by the rising CLKB edge.
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IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
RESET The IDT723616 is reset by taking the reset (RST) input LOW for at least four Port A clock (CLKA), four Port B clock (CLKB) and four Port C clock (CLKC) LOW-to-HIGH transitions. The reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFC) LOW, the empty flags (EFA, EFB) LOW, the Almost-Empty flags (AEA, AEB) LOW and the Almost-Full flags (AFA, AFC) HIGH. After a reset, FFA is set HIGH after two LOW-to-HIGH transitions of CLKA and FFC is set HIGH after two LOW-to-HIGH transitions of CLKC. The device must be reset after power up before data is written to its memory. A LOW-to-HIGH transition on the RST input loads the Almost-Full and Almost-Empty Offset register (X) with the values selected by the flagselect (FS0, FS1) inputs. The values that can be loaded into the registers are shown in Table 1.
TABLE 1 FLAG PROGRAMMING
FS1 H H L L FS0 H L H L RST ALMOST-FULL AND ALMOST-EMPTY FLAG OFFSET REGISTER (X) 16 12 8 4
FIFO WRITE/READ OPERATION The state of Port A data A0-A35 outputs is controlled by the Port A chip select (CSA) and the Port A write/read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, and FFA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, and EFA is HIGH (see Table 2). The state of the Port B data (B0-B17) outputs is controlled by Port B read select (RENB). The B0-B17 outputs are in the high-impedance state when REN is LOW. The B0-B17 outputs are active when REN IS HIGH. Data is read from FIFO1 to the B0-B17 outputs by a LOW-to-HIGH transition of CLKB when RENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1 is LOW (see Table 3). Data is loaded into FIFO2 from the C0-C17 inputs on a LOW-to-HIGH transition of CLKC when WENC is HIGH, FFC is HIGH, and either SIZ0 or SIZ1 is LOW (see Table 4). The setup and hold time constraints to the Port Clocks for the Port A chip select (CSA) and write/read selects (W/RA, RENB, WENC) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the Port Chip select (for Port A) and write/read select (for all ports) can change states during the setup and hold time window of the cycle.
TABLE 2 PORT-A ENABLE FUNCTION TABLE
CSA H L L L L W/RA X H H L L ENA X L H L H CLKA X X X A0-A35 Outputs In High-Impedance State In High-Impedance State In High-Impedance State Active, FIFO2 Output Register Active, FIFO2 Output Register Port Functions None None FIFO1 Write None FIFO2 Read
TABLE 3 PORT-B ENABLE FUNCTION TABLE
RENB L H SIZ1, SIZ0 X One or the other LOW
(1)
CLKB X
B0-B17 Outputs In High-Impedance State Active, FIFO1 Output Register
Port Functions None FIFO1 read
NOTE: 1. At no time during the operation of the FIFO is it permissible to apply a LOW logic level simultaneously to both SIZ0 and SIZ1, nor is it permissible to apply a HIGH logic level simultaneously to both these inputs. These state combinations are reserved.
TABLE 4 PORT-C ENABLE FUNCTION TABLE
WENC L H SIZ1, SIZ0 X One or the other LOW
(1)
CLKC X
C0-C17 Inputs In High-Impedance State In High-Impedance State
Port Functions None FIFO2 write
NOTE: 1. At no time during the operation of the FIFO is it permissible to apply a LOW logic level simultaneously to both SIZ0 and SIZ1, nor is it permissible to apply a HIGH logic level simultaneously to both these inputs. These state combinations are reserved.
10
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its Port Clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA operates asynchronously relative to CLKB or CLKC. EFA, AEA, FFA, and AFA are synchronized to CLKA. EFB and AEB are synchronized to CLKB. FFC and AFC are synchronized to CLKC. Tables 5 and 6 show the relationship of each port flag to FIFO1 and FIFO2. EMPTY FLAGS (EFA, EFB) The empty flag of a FIFO is synchronized to the Port Clock that reads data from its array. When the empty flag is HIGH, new data can be read to the FIFO output register. When the empty flag is LOW, the FIFO is empty and attempted FIFO reads are ignored. When reading FIFO1 with a byte or word size on Port B, EFB is set LOW when the fourth byte or second word of the last long word is read. The read pointer of a FIFO is incremented each time a new word is clocked to the output register. The state machine that controls an empty flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. A word written to a FIFO can be read to the FIFO output register in a minimum of three cycles of the empty flag synchronizing clock. Therefore, an empty flag is LOW if a word in memory is the next data to be sent to the FIFO output register and two cycles of the Port Clock that reads data from the FIFO have not elapsed since the time the word was written. The empty flag of the FIFO is set HIGH by the second LOW-toHIGH transition of the synchronizing clock, and the new data word can be read to the FIFO output register in the following cycle. A LOW-to-HIGH transition on an empty flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 12 and 13). FULL FLAG (FFA, FFC) The full flag of a FIFO is synchronized to the Port Clock that writes data to its array. When the full flag is HIGH, a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is LOW and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls a full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is full, full1, or full-2. From the time a word is read from a FIFO, the previous memory
location is ready to be written in a minimum of three cycles of the full flag synchronizing clock. Therefore, a full flag is LOW if less than two cycles of the full flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the full flag synchronization clock after the read sets the full flag HIGH and the data can be written in the following clock cycle. A LOW-to-HIGH transition on a full flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 14 and 15). ALMOST-EMPTY FLAGS (AEA, AEB) The Almost-Empty flag of a FIFO is synchronized to the Port Clock that reads data from its array. The state machine that controls an Almost-Empty flag monitors a write-pointer and a read-pointer comparator that indicates when the FIFO SRAM status is almost-empty, almost-empty+1, or almost-empty+2. The almost-empty state is defined by the value of the Almost-Full and AlmostEmpty Offset register (X). This register is loaded with one of four preset values during a device reset (see Reset above). An Almost-Empty flag is LOW when the FIFO contains X or less long words in memory and is HIGH when the FIFO contains (X+1) or more long words. Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock are required after a FIFO write for the Almost-Empty flag to reflect the new level of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1) or more long words remains LOW if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An AlmostEmpty flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost-Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) long words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figure 16 and 17). ALMOST-FULL FLAGS (AFA, AFC) The Almost-Full flag of a FIFO is synchronized to the Port Clock that writes data to its array. The state machine that controls an Almost-Full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost-full, almost-full-1, or almost-full-2. The almost-full state is defined by the value of the Almost-Full and Almost-Empty Offset register (X).
TABLE 5 FIFO1 FLAG OPERATION
Number of 36-Bit Words in the FIFO1(1) 0 1 to X (X+1) to [64-(X+1)] (64-X) to 63 64 Synchronized to CLKB EFB L H H H H AEB L L H H H Synchronized to CLKA AFA H H H L L FFA H H H H L
TABLE 6 FIFO2 FLAG OPERATION
Number of 36-Bit Words in the FIFO2(1 0 1 to X (X+1) to [64-(X+1)] (64-X) to 63 64 Synchronized to CLKA EFA L H H H H AEA L L H H H Synchronized to CLKC AFC H H H L L FFC H H H H L
NOTE: 1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register.
11
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
This register is loaded with one of four preset values during a device reset (see Reset above). An Almost-Full flag is LOW when the FIFO contains (64-X) or more long words in memory and is HIGH when the FIFO contains [64-(X+1)] or less long words. Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a FIFO read for the Almost-Full flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing [64-(X+1)] or less words remains LOW if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of long words in memory to [64-(X+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock after the FIFO read that reduces the number of long words in memory to [64-(X+1)]. A LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of long words in memory to [64-(X+1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figure 18 and 19). BUS SIZING Both ports B and C, taken together, may be configured for either an 18bit word or a 9-bit byte format, thus determining the word width of the data read from FIFO1 or written to FIFO2. Whichever bus size is selected applies to both ports B and C. It is not possible to configure the bus width of ports B and C independently. The levels applied to the bus size select (SIZ0, SIZ1) inputs must be static through out FIFO operation. These levels can only be changed when the FIFO is idle (no read or write activity) just preceding Master Reset operation. The bus size as selected using SIZ0 and SIZ1 is implemented according to Figure 2. Note that neither a HIGH nor a LOW logic level should be applied to both SIZ0 and SIZ1 at the same time; these states are reserved. Only 36-bit long-word data is written to or read from the two FIFO memories on the IDT723616. Bus-matching operations are done after data is read from the FIFO1 RAM and before data is written to the FIFO2 RAM. BUS-MATCHING FIFO1 READS Data is read from the FIFO1 RAM in 36-bit long word increments. Since Port B can only have a byte or word size, only the first one or two bytes appear on the selected portion of the FIFO1 output register, with the rest of the long word stored in auxiliary registers. In this case, subsequent FIFO1 reads with the same bus size implementation output the rest of the long word to the FIFO1 output register in the order shown by Figure 2. When reading data from FIFO1 in byte format, the unused B0-B17 outputs remain inactive but static, with the unused FIFO1 output register bits holding the last data value to decrease power consumption. BUS-MATCHING FIFO2 WRITES Data is written to the FIFO2 RAM in 36-bit long word increments. Data can be written to FIFO2 with a byte or word bus size. This action stores the initial bytes or words in auxiliary registers. The CLKC rising edge that writes the fourth byte or the second word of long word to FIFO2 also stores the entire long word in FIFO2 RAM. The bytes are arranged in the manner shown in Figure 2. BYTE SWAPPING The byte-order arrangement of data read from FIFO1 or data written to FIFO2 can be changed synchronous to the rising edge of CLKB. Four modes of byte-order swapping (including no swap) can be done with any
data port size selection. The order of the bytes are rearranged within the long word, but the bit order within the bytes remains constant. The swap configuration can be selected independently for ports B and C. The Port B Swap Select inputs (SWB0 and SWB1) are used to choose the byte arrangement for Port B. The Port C Swap Select inputs (SWC0 and SWC1) are used to choose the byte arrangement for Port C. The levels applied to the swap select must be static throughout FIFO operation. These levels can only be changed when the FIFO is idle (no read or write activity) just preceding Master Reset operation. Figures 3 and 4 are examples of the byte-order swapping operations available for 18-bit words. Performing a byte swap and bus size simultaneously for a FIFO1 read first rearranges the bytes as shown in Figure 3, then outputs the bytes as shown in Figure 2. Simultaneous bus sizing and byte swapping operations for FIFO2 writes first loads the data according to Figure 2, then swaps the bytes as shown in Figure 4 when the long word is loaded to FIFO2 RAM. PARITY CHECKING The Port A inputs (A0-A35) have four parity trees to check the parity of incoming (or outgoing) data; the Port B inputs (B0-B17) have two parity trees to check the parity of outgoing data; Port C inputs (C0-C17) have two parity trees to check the parity of incoming data. A parity failure on one or more bytes of the Port A data bus is reported by a LOW level on the port parity error flag (PEFA). A parity failure on one or more bytes of the Port C data bus that are valid for the bus size implementation is reported by a LOW level on the Port C parity error flag (PEFC). Odd or even parity checking can be selected, and the parity error flags can be ignored if this feature is not desired. Parity status is checked on each input bus according to the level of the ODD/ EVEN parity select input. A parity error on one or more valid bytes of a port is reported by a LOW level on the corresponding port parity error flag (PEFA, PEFC) output. Port A bytes are arranged as A0-A8, A9-A17, A18-A26, and A27-A35. Port C bytes are arranged as C0-C8 and C9-C17, and its valid bytes are those used in a Port C bus size implementation. When ODD/EVEN parity is selected, a port parity error flag (PEFA, PEFC) is LOW if any byte on the port has an ODD/EVEN number of LOW levels applied to the bits. PARITY GENERATION A HIGH level on the Port A parity generate select (PGA) or Port B parity generate select (PGB) enables the IDT723616 to generate parity bits for port reads from a FIFO. Port A bytes are arranged as A0-A8, A9-A17, A18-26, and A27-A35, with the most significant bit of each byte used as the parity bit. Port B bytes are arranged as B0-B8 and B9-B17, with the most significant bit of each byte used as the parity bit. A write to a FIFO stores the levels applied to all nine inputs of a byte regardless of the state of the parity generate select (PGA, PGB) inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the most significant bits of each byte as the word is read to the data outputs. Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the output register. Therefore, the Port A parity generate select (PGA) and ODD/EVEN parity select (ODD/EVEN) have setup and hold time constraints to the Port A clock (CLKA) and the Port B parity generate select (PGB) and ODD/EVEN have setup and hold-time constraints to the Port B clock (CLKB). These timing constraints only apply for a rising clock edge used to read a new long word to the FIFO output register.
12
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
A35A27
BYTE ORDER ON PORT A:
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
A26A18 A17A9 A8A0
A
B
C
D
Write to FIFO1/ Read From FIFO2
B17B9 SIZ1 L SIZ0 H B17B9
B8B0
C17C9 1st: Read from FIFO1
C8C0
A
B
B8B0
C
C17C9
D
C8C0
1st: Write to FIFO2
C
D
2nd: Read from FIFO1
WORD SIZE
A
B
2nd: Write to FIFO2
B17B9 SIZ1 H SIZ0 L
B8B0 1st: Read from FIFO1 B8B0 2nd: Read from FIFO1 B8B0 3rd: Read from FIFO1 B8B0 4th: Read from FIFO1
BYTE SIZE
C17C9
C8C0
A
B17B9
D
C17C9 C8C0
1st: Write to FIFO2
B
B17B9
C
C17C9 C8C0
2nd: Write to FIFO2
C
B17B9
B
C17C9 C8C0
3rd: Write to FIFO2
D
A
4th: Write to FIFO2
3520 fig01
NOTE: 1. At no time during the operation of the FIFO is it permissible to apply a LOW logic level simultaneously to both SIZ0 and SIZ1, nor is it permissible to apply a HIGH logic level simultaneously to both these inputs. These state combinations are reserved.
Figure 2. Bus Sizing
13
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Byte order on Port A: A35A27 A26A18 A17A9 A8A0
A
B
C
D
Write to FIFO1
SWB1 SWB0 L L
B17B9
B8B0
A
B
1st: Read from FIFO1
C
NO SWAP
D
2nd: Read from FIFO1
SWB1 SWB0 L H
B17B9
B8B0
D
C
1st: Read from FIFO1
B
BYTE SWAP
A
2nd: Read from FIFO1
SWB1 SWB0 H L
B17B9
B8B0
C
D
1st: Read from FIFO1
A
WORD SWAP
B
2nd: Read from FIFO1
SWB1 SWB0 H H
B17B9
B8B0
B
A
1st: Read from FIFO1
D
C
2nd: Read from FIFO1
3520 fig01a
BYTE-WORD SWAP
Figure 3. Port B Byte Swapping (Word Size Example)
14
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
A35A27 BYTE ORDER ON PORT A:
A26A18
A17A9
A8A0
A
B
C
D
Read from FIFO2
C17C9 SWC1 SWC0 L L
C8C0
C
D
1st: Write to FIFO2
A
NO SWAP
B
2nd: Write to FIFO2
C17C9 SWC1 SWC0 L H
C8C0
B
A
1st: Write to FIFO2
D
BYTE SWAP
C
2nd: Write to FIFO2
C17C9 SWC1 SWC0 H L
C8C0
A
B
1st: Write to FIFO2
C
WORD SWAP
D
2nd: Write to FIFO2
C17B9 SWC1 SWC0 H H
C8B0
D
C
1st: Write to FIFO2
B
A
2nd: Write to FIFO2
3520 fig01b
BYTE-WORD SWAP
Figure 4. Port C Byte Swapping (Word Size Example)
15
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CLKA CLKB
} tRSTH
CLKC tRSTS } RST FS1,FS0 tWFF FFA tREF EFA tWFF FFB tREF EFB tPAE AEA tPAF AFA tPAE AEB tPAF AFC
Figure 5. Device Reset Loading the X Register with the Value of Eight
3520 drw05
tFSS
tFSH
0,1 tWFF
tWFF
tCLKH CLKA FFA HIGH CSA
tCLK tCLKL
tENS tENS
tENH tENH tENH tDH W1
(1)
W/RA tENS ENA tDS A0 - A35 ODD/ EVEN PEFA
NOTE: 1. Written to FIFO1.
tENS
tENH
tENS
tENH
W2(1)
No Operation
tPDPE Valid
tPDPE Valid
3520 drw06
Figure 6. Port-A Write Cycle Timing for FIFO1
16
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CLKC FFC HIGH tENS WENC tDS C0-C17 ODD/EVEN tPDPE PEFC VALID tPDPE VALID
3520 drw07
tENH tDH
tENS
tENH
NOTE: 1. PEFC indicates parity error for the following bytes: C17-C9 and C8-C0.
DATA SWAP TABLE FOR WORD WRITES TO FIFO2
SWAP MODE SWC1 L SWC0 L 1 2 L H H H L H 1 2 1 2 1 2 WRITE NO. DATA WRITTEN TO FIFO2 C17-C9 C A B D A C D B C8-C0 D B A C B D C A A A A B B B C C C D D D A35-27 A DATA READ FROM FIFO2 A26-A18 B A17-A9 C A8-A0 D
Figure 7. Port-C Word Write Cycle Timing for FIFO2
17
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CLKC FFC HIGH WENC tDS C0-C8 ODD/EVEN tPPE PEFC Valid
NOTE: 1. PEFC indicates parity error for the following byte: C8--C0.
tENS
tENH
tENS
tENH
tDH
tPDPE Valid
tPDPE Valid
tPDPE Valid
3520 drw08
DATA SWAP TABLE FOR BYTE WRITES TO FIFO2
SWAP MODE SWC1 SWC0 1 L L 2 3 4 1 2 3 4 1 H L 2 3 4 1 2 3 4 WRITE NO. DATA WRITTEN TO FIFO2 C8-C0 D C B A A B C D B A D C C D A B A B C D A B C D A35-27 A26-A18 DATA READ FROM FIFO2 A17-A9 A8-A0
L
H
A
B
C
D
H
H
A
B
C
D
Figure 8. Port-C Byte Write Cycle Timing for FIFO2
18
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CLKB EFB RENB tPGS PGB, ODD/ EVEN B0-B17 tPGH HIGH tENS tENH
tEN
tA Previous Data
tA Read 1 Read 2
tDIS
3520drw09
DATA SWAP TABLE FOR WORD READS FROM FIFO1
SWAP MODE SWB1 L L H H SWB0 L H L H A35-A27 A A A A DATA WRITTEN TO FIFO1 A26-A18 B B B B A17-A9 C C C C A8-A0 D D D D 1 2 1 2 1 2 1 2 READ NO. DATA READ FROM FIFO1 B17-B9 A C D B C A B D B8-B0 B D C A D B A C
Figure 9. Port-B Word Read Cycle Timing for FIFO1
19
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CLKB EFB HIGH tENS RENB PGB, ODD/ EVEN B0-B8 tSZS tSZH tPGS tPGH tENH
tEN
tA Previous Data
tA Read 1
tA Read 2
tA Read 3
tDIS Read 4
3520 drw10
NOTE: 1. Unused bytes hold last FIFO1 output register data for byte-size reads.
DATA SWAP TABLE FOR BYTE READS FROM FIFO1
SWAP MODE SWB1 SWB0 A35-A27 DATA WRITTEN TO FIFO 1 A26-A18 A17-A9 A8-A0 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 READ NO. DATA READ FROM FIFO 1 B17-B9 A B C D D C B A C D A B B A D C
L
L
A
B
C
D
L
H
A
B
C
D
H
L
A
B
C
D
H
H
A
B
C
D
Figure 10. Port-B Byte Read Cycle Timing for FIFO1
20
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tCLK tCLKH CLKA EFA HIGH CSA W/RA tENS ENA tEN A0 - A35 tPGS PGA, ODD/ EVEN
NOTE: 1. Read from FIFO2.
tCLKL
tENH
tENS
tENH
tENS
No Operation
tENH
tA Previous Data tPGH Word 1 (1) tPGS
tA tPGH
tDIS
Word 2 (1)
3520 drw11
Figure 11. Port-A Read Cycle Timing for FIFO2
tCLK tCLKH tCLKL CLKA CSA WRA ENA FFA A0 - A35 HIGH tDS W1 tSKEW1 CLKB EFB RENB tEN B0 -B17 tA tA Read 1 tDIS Read 2
3520 drw12 (1)
LOW HIGH tENS tENH
tDH tCLK tCLKH tCLKL 1
2 tREF tREF tENS tENH
FIFO1 Empty
Previous Data
NOTES: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown. 2. Port-B size is word or byte; EFB is set LOW by the last word or byte read from FIFO1, respectively. (The word-size case is shown.)
Figure 12. EFB Flag Timing and First Data Read when FIFO1 is Empty
21
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tCLK tCLKH tCLKL CLKC tENS WENC FFC C0 - C17 CLKA EFA CSA W/RA ENA tA A0 -A35 W1
3520 drw13
tENH
HIGH tDS
Write 1
tDH tDS
Write 2
tDH
(1)
tSKEW1
tCLKH 1
tCLK tCLKL 2 tREF tREF
FIFO2 Empty LOW LOW tENS tENH
NOTES: 1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown. 2. Port-C size is word or byte; tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively. (The word-size case is shown.)
Figure 13. EFA Flag Timing and First Data Read when FIFO2 is Empty
tCLKH CLKB tENS RENB EFB B0 - B17
Previous Word in FIFO1 Output Register
tCLK
tCLKL tENH
HIGH tEN
tA
Read 1
tA tSKEW1(1)
tDIS
Read 2
tCLKH 1 FIFO1 Full
tCLK tCLKL 2 tWFF tWFF
CLKA FFA CSA WRA ENA LOW HIGH
tENS tDS
tENH tDH
To FIFO1
3520 drw14
A0 - A35
NOTES: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown. 2. Port-B size is word or byte; tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively. (The word-size case is shown.)
Figure 14. FFA Flag Timing and First Available Write when FIFO1 is Full
22
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
tCLK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tCLKH CLKA CSA LOW W/RA LOW
tCLKL
tENS ENA EFA HIGH A0 - A35
tENH
tA
Next Word From FIFO2
Previous Word in FIFO2 Output Register
tSKEW1(1) CLKC FFC WENC
tCLKH 1
tCLK
tCLKL 2 tWFF tWFF tENS tDS tDH
To FIFO2
FIFO2 Full tENH tDS tDH
3520 drw15
C0 - C17
NOTES: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown. 2. Port-C size is word or byte; FFC is set LOW by the last word or byte write of the long word, respectively. (The word-size case is shown.)
Figure 15. FFC Flag Timing and First Available Write when FIFO2 is Full
CLKA tENS ENA tSKEW2 CLKB AEB RENB
3520 drw16 (1)
tENH
1
X Long Word in FIFO1
2 tPAE tENS tPAE
(X+1) Long Words in FIFO1
tENH
NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = HIGH). 3. Port-B size is word or byte; AEB is set LOW by the last word or byte read of the long word, respectively.
Figure 16. Timing for AEB when FIFO1 is Almost-Empty
CLKC tENS WENC
tSKEW2 (1)
tENH
CLKA AEA ENA
1
X Long Words in FIFO2
2 tPAE tENS tPAE
(X+1) Long Words in FIFO2
tENH
3520 drw17
NOTES: 1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown. 2. FIFO2 read (CSA = LOW, W/RA = LOW). 3. Port-C size is word or byte; tSKEW2 is referenced from the rising CLKC edge that writes the last word or byte of the long word, respectively.
Figure 17. Timing for AEA when FIFO2 is Almost-Empty
23
IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
tSKEW2 CLKA tENS ENA tPAF AFA [64-(X+1)] Long Words in FIFO1 CLKB tENS RENB tENH tENH
(1)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2
tPAF (64-X) Long Words in FIFO1
3520 drw18
NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = HIGH). 3. Port-B size is word or byte; tSKEW2 is referenced from the last word or byte read of the long word, respectively.
Figure 18. Timing for AFA when FIFO1 is Almost-Full
tSKEW2 (1) CLKC tENS WENC tPAF AFC CLKA tENS ENA
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1 tENH
2
[64-(X+1)] Long Words in FIFO2
(64-X) Long Words in FIFO2
tPAF
tENH
NOTES: 1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKC edge and rising CLKA edge is less than tSKEW2, then AFC may transition HIGH one CLKA cycle later than shown. 2. Port-C size is word or byte; AFC is set LOW by the last word or byte read of the long word, respectively.
Figure 19. Timing for AFC when FIFO2 is Almost-Full
ODD/ EVEN W/RA PGA tPOPE PEFA Valid Valid tPOPE Valid tPEPE tPEPE Valid
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Figure 20. ODD/EVEN, W/RA and PGA to PEFA Timing
ODD/ EVEN
tPOPE
PEFC
Valid Valid
tPOPE
Valid
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Figure 21. ODD/EVEN to PEFC Timing
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IDT723616 CMOS TRIPLE BUS SyncFIFOTM WITH TM BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION
5V
1.1 k From Output Under Test 30 pF 680
(1)
LOAD CIRCUIT
3V Timing Input tS Data, Enable Input 1.5 V 1.5 V GND th 3V 1.5 V GND VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Low-Level Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS High-Level Input 1.5 V tW 1.5 V
3V GND 3V 1.5 V GND
Output Enable tPLZ Low-Level Output
3V 1.5 V 1.5 V tPZL 1.5 V tPZH 1.5 V VOL VOH In-Phase Output GND 3 V Input 3V 1.5 V tPD 1.5 V 1.5 V GND tPD 1.5 V VOH VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
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High-Level Output
tPHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
OV
NOTE: 1. Includes probe and jig capacitance.
Figure 22. Load Circuit and Voltage Waveforms
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ORDERING INFORMATION
IDT XXXXXX Device Type X Power XX Speed XX Package X Process/ Temperature Range BLANK I(1) PF 15 20 L 723616 Commercial (0C to +70C) Industrial (40C to +85C) Thin Quad Flat Pack (TQFP, PK128-1) Commercial Only Com'l & Ind'l Low Power 4 x 36 x 2Triple Bus SyncFIFO
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Clock Cycle Time (tCLK) Speed in Nanoseconds
NOTE: 1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
DATASHEET DOCUMENT HISTORY
03/05/2002 pgs. 1, 6, 8, 9 and 26. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
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for Tech Support: e-mail: FIFOhelp@idt.com Phone: (408) 330-1753

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