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M48T59 M48T59Y/M48T59V
5.0 or 3.3V, 64 Kbit (8 Kbit x 8) TIMEKEEPER(R) SRAM
FEATURES SUMMARY s INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, and BATTERY
s
Figure 1. 28-pin PCDIP, CAPHATTM Package
FREQUENCY TEST OUTPUT FOR REAL TIME CLOCK SOFTWARE CALIBRATION AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48T59: VCC = 4.75 to 5.5V 4.5V VPFD 4.75V - M48T59Y: VCC = 4.5 to 5.5V 4.2V VPFD 4.5V - M48T59V: VCC = 3.0 to 3.6V 2.7V VPFD 3.0V SELF-CONTAINED BATTERY and CRYSTAL IN THE CAPHATTM DIP PACKAGE PACKAGING INCLUDES A 28-LEAD SOIC and SNAPHAT(R) TOP (to be ordered separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY and CRYSTAL MICROPROCESSOR POWER-ON RESET (Valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT ACTIVE IN THE BATTERY BACK-UP MODE BATTERY LOW FLAG
28 1 28 1
s
s
PCDIP28 (PC) Battery/Crystal CAPHAT
s
Figure 2. 28-pin SOIC Package
s
s
SNAPHAT (SH) Battery/Crystal
s
s
s
SOH28 (MH)
May 2002
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M48T59, M48T59Y, M48T59V
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Logic Diagram (Figure 3.) . . . . . . . . . . . . . . . . . . . . Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . 28-pin SOIC Connections (Figure 4.) . . . . . . . . . . . PCDIP28 CAPHAT Connections (Figure 5.) . . . . . . Block Diagram (Figure 6.) . . . . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... .....4 .....4 .....5 .....5 .....5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AC Measurement Load Circuit (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating Modes (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 READ Mode AC Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 READ Mode AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE Enable Controlled, WRITE Mode AC Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . 11 Chip Enable Controlled, WRITE Mode AC Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Down/Up Mode AC Waveforms (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Down/Up AC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power Down/Up Trip Points DC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Register Map (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Calibrating the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Alarm Interrupt Reset Waveform (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Alarm Repeat Mode (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Back-up Mode Alarm Waveforms (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power-on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Programmable Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Battery Low Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Initial Power-on Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Default Values (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Crystal Accuracy Across Temperature (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clock Calibration (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VCC Noise And Negative Going Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Supply Voltage Protection (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SNAPHAT Battery Table (Table 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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M48T59, M48T59Y, M48T59V
SUMMARY DESCRIPTION The M48T59/Y/V TIMEKEEPER (R) RAM is an 8 Kb x 8 non-volatile static RAM and real time clock. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution. The M48T59/Y/V is a non-volatile pin and function equivalent to any JEDEC standard 8 Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 28-pin, 600mil DIP CAPHATTM houses the M48T59/Y/V silicon with a quartz crystal and a long life lithium button cell in a single package. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT(R) housing con-
taining the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4T28-BR12SH" or "M4T32-BR12SH" (see Table 15, page 22). Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
Figure 3. Logic Diagram
VCC
Table 1. Signal Names
A0-A12 DQ0-DQ7 Address Inputs Data Inputs / Outputs Interrupt / Frequency Test Output (Open Drain) Reset Output (Open Drain) Chip Enable Output Enable Write Enable Supply Voltage Ground
13 A0-A12 M48T59 M48T59Y M48T59V
8 DQ0-DQ7
IRQ/FT RST
W E G
E
IRQ/FT RST
G W VCC VSS
VSS
AI01380E
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Figure 4. 28-pin SOIC Connections
RST A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 28 27 2 26 3 25 4 24 5 23 6 7 M48T59Y 22 8 M48T59V 21 20 9 19 10 18 11 17 12 16 13 15 14
AI01382E
Figure 5. PCDIP28 CAPHAT Connections
VCC W IRQ/FT A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 RST A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 28 1 27 2 26 3 25 4 24 5 23 6 7 M48T59 22 8 M48T59Y 21 20 9 19 10 18 11 17 12 13 16 14 15
AI01381D
VCC W IRQ/FT A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Figure 6. Block Diagram
IRQ/FT
OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL POWER
16 x 8 BiPORT SRAM ARRAY
A0-A12
8176 x 8 SRAM ARRAY LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD
DQ0-DQ7
E W G
VCC
RST
VSS
AI01383D
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MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 2. Absolute Maximum Ratings
Symbol TA TSTG TSLD(1,2) VIO VCC IO PD Parameter Grade 1 Ambient Operating Temperature Grade 6 Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Input or Output Voltages M48T59/M48T59Y Supply Voltage M48T59V Output Current Power Dissipation -0.3 to 4.6 20 1 mA W -40 to 85 -40 to 85 260 -0.3 to 7 -0.3 to 7 V C C V Value 0 to 70 C Unit
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. For DIP package: Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). 2. For SO package: Reflow at peak temperature of 215C to 225C for < 60 seconds (total thermal budget not to exceed 180C for between 90 to 120 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Grade 1 Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
M48T59 4.75 to 5.5 0 to 70 n/a 100 5 0 to 3 1.5
M48T59Y 4.5 to 5.5 0 to 70 -40 to 85 100 5 0 to 3 1.5
M48T59V 3.0 to 3.6 0 to 70 -40 to 85 50 5 0 to 3 1.5
Unit V C C pF ns V V
Grade 6
Figure 7. AC Measurement Load Circuit
DEVICE UNDER TEST
645
(1) CL = 100pF
1.75V
CL includes JIG capacitance
Note: Excluding open-drain output pins 1. 50pF for M48T59V.
AI02325
Table 4. Capacitance
Symbol CIN CIO(3) Input Capacitance Input / Output Capacitance Parameters(1,2) Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
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Table 5. DC Characteristics
Symbol ILI ILO(2) ICC ICC1 ICC2 VIL(3) VIH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage VOL Output Low Voltage (IRQ/FT and RST) (4) Output High Voltage IOL = 2.1mA IOL = 10mA IOH = -1mA 2.4 Test Condition(1) 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC - 0.2V -0.3 2.2 M48T59/Y Min Max 1 1 50 3 3 0.8 VCC + 0.3 0.4 0.4 2.4 -0.3 2 M48T59V Unit Min Max 1 1 30 2 1 0.8 VCC + 0.3 0.4 0.4 A A mA mA mA V V V V V
VOH
Note: 1. Valid for Ambient Operating Temperature: T A = 0 to 70C or -40 to 85C; VCC = 4.5 to 5.5V, 4.75 to 5.5V, or 3.0 to 3.6V (except where noted). 2. Outputs deselected. 3. Negative spikes of -1V allowed for up to 10ns once per cycle. 4. The IRQ/FT and RST pins are Open Drain.
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OPERATION MODES As Figure 6, page 5 shows, the static memory array and the quartz-controlled clock oscillator of the M48T59/Y/V are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDETM clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour BCD format (except for the century). Corrections for 28, 29 (leap year valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations Table 6. Operating Modes
Mode Deselect WRITE READ READ Deselect Deselect VCC 4.75 to 5.5V or 4.5 to 5.5V or 3.0 to 3.6V VSO to VPFD (min)(1) VSO(1) E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ7-DQ0 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
consisting of BiPORTTM READ/WRITE memory cells. The M48T59/Y/V includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T59/Y/V also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V/3.3V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns.
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10, page 14 for details.
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READ Mode The M48T59/Y/V is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter Figure 8. READ Mode AC Waveforms
tAVAV A0-A12 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI01385
of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
VALID tAXQX tEHQZ
tGHQZ
Note: WRITE Enable (W) = High.
Table 7. READ Mode AC Characteristics
M48T59/Y/V Symbol Parameter
(1)
-70 Min Max
Unit
tAVAV tAVQV(2) tELQV(2) tGLQV(2) tELQX(3) tGLQX(3) tEHQZ(3) tGHQZ(3) tAXQX(2)
READ Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
70 70 70 35 5 5 25 25 10
ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: T A = 0 to 70C or -40 to 85C; VCC = 4.5 to 5.5V, 4.75 to 5.5V, or 3.0 to 3.6V (except where noted). 2. CL = 100pF (see Figure 7, page 7). 3. CL = 5pF (see Figure 7, page 7).
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WRITE Mode The M48T59/Y/V is in the WRITE Mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of anoth-
er READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; however, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls.
Figure 9. WRITE Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A12 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01386
tWHAX
tWHQX
Figure 10. Chip Enable Controlled, WRITE Mode AC Waveforms
tAVAV A0-A12 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01387B
tELEH
tEHAX
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Table 8. WRITE Mode AC Characteristics
M48T59/Y/V Symbol Parameter
(1)
-70 Min Max
Unit
tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2,3) tAVWH tAVEH tWHQX(2,3)
WRITE Cycle Time Address Valid to WRITE Enable Low Address Valid to Chip Enable Low WRITE Enable Pulse Width Chip Enable Low to Chip Enable High WRITE Enable High to Address Transition Chip Enable High to Address Transition Input Valid to WRITE Enable High Input Valid to Chip Enable High WRITE Enable High to Input Transition Chip Enable High to Input Transition WRITE Enable Low to Output Hi-Z Address Valid to WRITE Enable High Address Valid to Chip Enable High WRITE Enable High to Output Transition
70 0 0 50 55 0 0 30 30 5 5 25 60 60 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: T A = 0 to 70C or -40 to 85C; VCC = 4.5 to 5.5V, 4.75 to 5.5V, or 3.0 to 3.6V (except where noted). 2. CL = 5pF (see Figure 7, page 7). 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
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Data Retention Mode With valid VCC applied, the M48T59/Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "don't care." Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T59/Y/V may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. ThereFigure 11. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tPD tFB tDR tREC RST tRB tR
fore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T59/Y/V for an accumulated period of at least 7 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected and the power supply is switched to external VCC. Deselect continues for tREC after VCC reaches VPFD (max). For more information on Battery Storage Life refer to the Application Note AN1012.
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI03258
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Table 9. Power Down/Up AC Characteristics
Symbol tPD tF(2) tFB(3) tR tRB tREC(4) Parameter(1) E or W at VIH before Power Down VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time VPFD (max) to RST High Min 0 300 10 10 1 40 200 Max Unit s s s s s ms
Note: 1. Valid for Ambient Operating Temperature: T A = 0 to 70C or -40 to 85C; VCC = 4.5 to 5.5V, 4.75 to 5.5V, or 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. 4. tREC (min) = 20ms for industrial temperature grade 6 device.
Table 10. Power Down/Up Trip Points DC Characteristics
Symbol Parameter(1,2) M48T59 VPFD Power-fail Deselect Voltage M48T59Y M48T59V M48T59/Y VSO Battery Back-up Switchover Voltage M48T59V Grade 1 tDR(3) Expected Data Retention Time Grade 6 7 10(4) Min 4.5 4.2 2.7 Typ 4.6 4.35 2.9 3.0 VPFD -100mV Max 4.75 4.5 3.0 Unit V V V V V YEARS YEARS
Note: 1. Valid for Ambient Operating Temperature: T A = 0 to 70C or -40 to 85C; VCC = 4.5 to 5.5V, 4.75 to 5.5V, or 3.0 to 3.6V (except where noted). 2. All voltages referenced to VSS. 3. At 25C. 4. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - Grade 6 device).
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CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER(R) registers should be halted before clock data is read to prevent reading data in transition. The BiPORTTM TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ Bit, D6 in the Control register (1FF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.' Setting the Clock Bit D7 of the Control register (1FF8h) is the WRITE Bit. Setting the WRITE Bit to a '1,' like the READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 11, page 16). Resetting the WRITE Bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIME-
KEEPER counters and allows normal operation to resume. After the WRITE Bit is reset, the next clock update will occur within approximately one second. See the Application Note AN923, "TIMEKEEPER Rolling Into the 21st Century" for information on Century Rollover. Note: Upon power-up following a power failure, both the WRITE Bit and the READ Bit will be reset to '0.' Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T59/Y/V in the DIP package is shipped from STMicroelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T59/Y/V oscillator starts within one second. Note: It is not necessary to set the WRITE Bit when setting or resetting the FREQUENCY TEST Bit (FT), the STOP Bit (ST) or the CENTURY ENABLE Bit (CEB).
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Table 11. Register Map
Data Address D7 1FFFh 1FFEh 1FFDh 1FFCh 1FFBh 1FFAh 1FF9h 1FF8h 1FF7h 1FF6h 1FF5h 1FF4h 1FF3h 1FF2h 1FF1h 1FF0h 0 0 0 0 0 ST W WDS AFE RPT4 RPT3 RPT2 RPT1 Y WDF R BMB4 Y Y Y D6 D5 D4 D3 D2 Year 10 M Month Date 0 Day Hours Minutes Seconds Calibration BMB2 Y BMB1 Y BMB0 Y RB1 Y RB0 Y D1 D0 10 Years 0 0 FT 0 0 Function/Range BCD Format Year Month Date Century/Day Hours Minutes Seconds Control Watchdog Interrupts Alarm Date Alarm Hours Alarm Minutes Alarm Seconds Y Z Unused Flags 01-31 00-23 00-59 00-59 00-99 01-12 01-31 00-01/01-07 00-23 00-59 00-59
10 Date CEB CB
10 Hours 10 Minutes 10 Seconds S BMB3 ABE
Al. 10 Date Al. 10 Hours
Alarm Date Alarm Hours Alarm Minutes Alarm Seconds Y Z Y Z Y Z
Alarm 10 Minutes Alarm 10 Seconds Y AF Y Z Y BL
Keys: S = SIGN Bit FT = FREQUENCY TEST Bit R = READ Bit W = WRITE Bit ST = STOP Bit 0 = Must be set to '0' Y = '1' or '0' Z = '0' and are Read only AF = Alarm Flag (Read only) BL = Battery Low (Read only)
WDS = Watchdog Steering Bit BMB0-BMB4 = Watchdog Multiplier Bits RB0-RB1 = Watchdog Resolution Bits AFE = Alarm Flag Enable ABE = Alarm in Battery Back-up Mode Enable RPT1-RPT4 = Alarm Repeat Mode Bits WDF = Watchdog Flag (Read only) CEB = Century Enable Bit CB = Century Bit
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Calibrating the Clock The M48T59/Y/V is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T59/Y/V improves to better than +1/-2 ppm at 25C. The oscillation rate of any crystal changes with temperature (see Figure 14, page 20). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome "trim" capacitors. The M48T59/Y/V design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 15, page 21. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit Calibration byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Byte occupies the five lower order bits (D4-D0) in the Control register (1FF8h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles; for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration Byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T59/Y/V may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the fi-
nal product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the Calibration Byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT pin. The pin will toggle at 512 Hz when the Stop Bit (D7 of 1FF9h) is '0,' the FT Bit (D6 of 1FFCh) is '1,' the AFE Bit (D7 of 1FF6h) is '0,' and the Watchdog Steering Bit (D7 of 1FF7h) is '1' or the Watchdog Register is reset (1FF7h = 0). Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (WR001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency Test output frequency. The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper operation. A 500-10k resistor is recommended in order to control the rise time. The FT Bit is cleared on power-down. For more information on calibration, see Application Note AN934, "TIMEKEEPER Calibration." Setting the Alarm Clock Registers 1FF5h-1FF2h contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific day of the month or repeat every month, day, hour, minute, or second. It can also be programmed to go off while the M48T59/Y/V is in the battery back-up mode of operation to serve as a system wake-up call. Bits RPT1-RPT4 put the alarm in the repeat mode of operation. Table 12, page 18 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. Note: User must transition address (or toggle chip enable) to see Flag Bit change. When the clock information matches the alarm clock settings based on the match criteria defined by RPT1-RPT4, AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT pin. To disable the alarm, write '0' to the Alarm Date Register and RPT1-4. The Alarm Flag and the IRQ/FT output are cleared by a READ to the Flags Register as shown in Figure 12, page 18. A subsequent READ of the Flags Register is necessary to see that the value of the Alarm Flag has been reset to '0.'
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The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an alarm occurs and both the ABE (Alarm in Battery Back-up Mode Enable) and the AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will Figure 12. Alarm Interrupt Reset Waveform
15ns Min A0-A12 ADDRESS 1FF0h
only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M48T59/Y/V was in the deselect mode during power-down. Figure 13, page 18 illustrates the back-up mode alarm timing.
ACTIVE FLAG BIT
IRQ/FT HIGH-Z
AI01388B
Table 12. Alarm Repeat Mode
RPT4 1 1 1 1 0 RPT3 1 1 1 0 0 RPT2 1 1 0 0 0 RPT1 1 0 0 0 0 Alarm Activated Once per Second Once per Minute Once per Hour Once per Day Once per Month
Figure 13. Back-up Mode Alarm Waveforms
tREC VCC VPFD (max) VPFD (min) VSO
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT HIGH-Z HIGH-Z
AI03254B
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Watchdog Timer The watchdog timer can be used to detect an outof-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the eight-bit Watchdog Register (Address 1FF7h). The five bits (BMB4-BMB0) that store a binary multiplier and the two lower order bits (RB1-RB0) select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3 x 1 or 3 seconds). Note: Accuracy of timer is within the selected resolution. If the processor does not reset the timer within the specified period, the M48T59/Y/V sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the Flags Register (Address 1FF0h). Note: User must transition address (or toggle chip enable) to see Flag Bit change. The most significant bit of the Watchdog Register is the Watchdog Steering Bit. When set to a '0,' the watchdog will activate the IRQ/FT pin when timedout. When WDS is set to a '1,' the watchdog will output a negative pulse on the RST pin for a duration of tREC. The Watchdog Register, the FT Bit, and the AFE and ABE Bits will reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1.' The watchdog timer resets when the microprocessor performs a re-write of the Watchdog Register. The time-out period then starts over. The watchdog timer is disabled by writing a value of 00000000 to the eight bits in the Watchdog Register. The watchdog function is automatically disabled upon power-down and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied. Power-on Reset The M48T59/Y/V continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC passes VPFD (max). RST is valid for all VCC conditions. The RST pin is an open drain output and an appropriate resistor to VCC should be chosen to control rise time. Programmable Interrupts The M48T59/Y/V provides two programmable interrupts; an alarm and a watchdog. When an interrupt condition occurs, the M48T59/Y/V sets the
appropriate flag bit in the Flag Register 1FF0h. The interrupt enable bits in (AFE and ABE) in 1FF6h and the Watchdog Steering (WDS) Bit in 1FF7h allow the interrupt to activate the IRQ/FT pin. The Alarm flag and the IRQ/FT output are cleared by a READ to the Flags Register. An interrupt condition reset will not occur unless the addresses are stable at the flag location for at least 15ns while the device is in the READ Mode as shown in Figure 12, page 18. The IRQ/FT pin is an open drain output and requires a pull-up resistor (10k recommended) to VCC. The pin remains in the high impedance state unless an interrupt occurs or the Frequency Test Mode is enabled. Battery Low Flag The M48T59/Y/V automatically performs periodic battery voltage monitoring upon power-up and at factory-programmed time intervals of 24 hours (at day rollover) as long as the device is powered and the oscillator is running. The Battery Low Flag (BL), Bit D4 of the Flags Register 1FF0h, will be asserted high if the internal or SNAPHAT(R) battery is found to be less than approximately 2.5V. The BL Flag will remain active until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery voltage is below 2.5V (approximately), which may be insufficient to maintain data integrity. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates the battery is near end of life. However, data has not been compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, it is recommended that the battery be replaced. The SNAPHAT top may be replaced while VCC is applied to the device. Note: This will cause the clock to lose time during the interval the battery/crystal is removed. Note: Battery monitoring is a useful technique only when performed periodically. The M48T59/Y/V only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
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Century Bit Bit D5 and D4 of Clock Register 1FFCh contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Note: The WRITE Bit must be set in order to write to the CENTURY Bit. Table 13. Default Values
Condition Initial Power-up (Battery Attach for SNAPHAT)(2) Subsequent Power-up / RESET(3) Power-down(4)
Note: 1. 2. 3. 4.
Initial Power-on Defaults Upon application of power to the device, the following register bits are set to a '0' state: WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; FT (see Table 13).
W 0 0 0
R 0 0 0
FT 0 0 0
AFE 0 0 1
ABE 0 0 1
WATCHDOG Register(1) 0 0 0
WDS, BMB0-BMB4, RBO, RB1. State of other control bits undefined. State of other control bits remains unchanged. Assuming these bits set to '1' prior to power-down.
Figure 14. Crystal Accuracy Across Temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C
Temperature C
AI00999
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Figure 15. Clock Calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 16) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.
Figure 16. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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PART NUMBERING Table 14. Ordering Information Scheme
Example: M48T 59Y -70 MH 1 TR
Device Type M48T
Supply Voltage and Write Protect Voltage 59(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 59Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V 59V = VCC = 3.0 to 3.6V; VPFD = 2.7 to 3.0V
Speed -70 = 70ns
Package PC = PCDIP28 MH(2) = SOH28
Temperature Range 1 = 0 to 70C 6(3) = -40 to 85C
Shipping Method for SOIC blank = Tubes TR = Tape & Reel
Note: 1. The M48T59 part is offered with the PCDIP28 (e.g., CAPHATTM) package only. 2. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT (R)) which is ordered separately under the part number "M4TXX-BR12SH" in plastic tube or "M4TXX-BR12SHTR" in Tape & Reel form. 3. Available in SOIC package only. Caution: Do not place the SNAPHAT battery/crystal package "M4TXX-BR12SH" in conductive foam as it will drain the lithium button-cell battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 15. SNAPHAT Battery Table
Part Number M4T28-BR12SH M4T32-BR12SH Description Lithium Battery (48mAh) SNAPHAT Lithium Battery (120mAh) SNAPHAT Package SH SH
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PACKAGE MECHANICAL INFORMATION Figure 17. PCDIP28 - 28-pin Plastic DIP, battery CAPHAT, Package Outline
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Note: Drawing is not to scale.
Table 16. PCDIP28 - 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm Symb Typ A A1 A2 B B1 C D E e1 e3 eA L N Min 8.89 0.38 8.38 0.38 1.14 0.20 39.37 17.83 2.29 29.72 15.24 3.05 28 Max 9.65 0.76 8.89 0.53 1.78 0.31 39.88 18.34 2.79 36.32 16.00 3.81 Typ Min 0.350 0.015 0.330 0.015 0.045 0.008 1.550 0.702 0.090 1.170 0.600 0.120 28 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.570 0.722 0.110 1.430 0.630 0.150 inches
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M48T59, M48T59Y, M48T59V
Figure 18. SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note: Drawing is not to scale.
Table 17. SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm Symb Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches
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M48T59, M48T59Y, M48T59V
Figure 19. SH - 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note: Drawing is not to scale.
Table 18. SH - 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches
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M48T59, M48T59Y, M48T59V
Figure 20. SH - 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note: Drawing is not to scale.
Table 19. SH - 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090 inches
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REVISION HISTORY Table 20. Document Revision History
Date October 1999 03/22/00 07/13/00 05/14/01 07/31/01 08/06/01 05/20/02 First Issue Century Bit Paragraph added; tFB value changed (Table 9) From Preliminary Data to Data Sheet Reformatted, Ind. Temp. added (Table 3), SNAPHAT table added (Table 15), temp/voltage info. added to tables (Table 4, 5, 7, 8, 9, 10) Formatting changes from recent document review findings Fix text for Setting the Alarm Clock (Figure 12) Modify reflow time and temperature footnotes (Table 2) Revision Details
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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