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M65656G
32 K 8 Very Low Power CMOS SRAM Rad Tolerant
Introduction
The M65656G is a very low power CMOS static RAM organized as 32768 x 8 bits. TEMIC brings the solution for applications where fast computing is as mandatory as low consumption, such as aerospace electronics, portable instruments or embarked systems. Using an array of six transistors (6T) memory cells, the M65656G combines an extremely low standby supply current (Typical value = 0.1 A) with a fast access time at 40 ns. The high stability of the 6T cell provides excellent protection against soft errors due to noise. Extra protection against heavy ions is given by the use of an epitaxial layer of a P substrate. The M65656G is processed according to the methods of the latest revision of the MIL STD 883 (class B or S), ESA SCC 9000 and QML.
Features
D Access time 40, 55 ns D Very low power consumption active : 50 mW (typ) standby : 0.5 W (typ) data retention : 0.4 W (typ) D D D D D D D Wide temperature range : -55 to + 125C 300 and 600 mils width package TTL compatible inputs and outputs Asynchronous Single 5 volt supply Equal cycle and access time Gated inputs : no pull-up/down resistors are required
Interface
Block Diagram
Rev. E - June 30,1999)
1
M65656G
Pin Configuration
Side Brazed 600/300 mils 28 pins Multilayer Flat Pack 28 pins
(Top View)
Pin Names
A0-A14 : I/O0-I/O7 : VCC : GND : Address inputs Input/Output Power Ground CS : W: OE : Chip-Select Write Enable Output Enable
Truth Table
CS
H L L L
W
X H L H
OE
X L X H
INPUTS/ OUTPUTS
Z DATA OUT DATA IN Z
MODE
Deselect/ POWER-DOWN Read Write Output Disable
L = low, H = high, X = H or L, Z = high impedance
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : . . . . . . . . . . . . . . . -0.3 V to + 7.0 V Input or Output voltage applied : . . . . . (Gnd - 0.3 V) to (Vcc + 0.3 V) Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . -65 oC to + 150 oC Electro static discharge voltage . . . . . . . . . . > 2000 V (MIL STD 883, METHOD 3015)
Operating Range
OPERATING VOLTAGE
Military VCC = 5 V 10 %
OPERATING TEMPERATURE
- 55 _C to + 125 _C
DC Operating Conditions
PARAMETER
Vcc Gnd VIL VIH(1) Note : (1) Ground Input low voltage input high voltage
DESCRIPTION
Supply voltage
MINIMUM
4.5 0.0 - 0.3 2.2
TYPICAL
5.0 0.0 0.0 -
MAXIMUM
5.5 0.0 0.8 Vcc + 0.3
UNIT
V V V V
1. VIH max = Vcc + 0.3 V, VIL min = -0.3 V or -1.0 pulse 50 ns.
2
Rev. E - June 30,1999)
M65656G
Capacitance
PARAMETER
Cin Cout Note : (2) (2)
DESCRIPTION
Input capacitance Output capacitance
MINIMUM
- -
TYPICAL
- -
MAXIMUM
8 8
UNIT
pF pF
2. TA = 25C, f = 1 MHz, Vcc = 5.0 V, these parameters are not tested.
DC Parameter
PARAMETER
IIX IOZ (3) VOL VOH Notes : (4) (4) (3)
DESCRIPTION
Input leakage current Output leakage current Output low voltage Output high voltage
MINIMUM
- 1.0 - 1.0 - 2.4
TYPICAL
- - - -
MAXIMUM
1.0 1.0 0.4 -
UNIT
A A V V
3. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output disabled. 4. Vcc min, IOL = 4 mA, IOH = -1.0 mA.
Consumption
SYMBOL
ICCSB (5) ICCSB1 (6) ICCOP (7) Notes : 5. 6. 7. (*)
PARAMETER
Standby supply current Standby supply current Operating supply current
M65656G V - 45
5 100 70
M65656G V - 55
5 100 70
UNIT
mA A mA
VALUE
max max max
CS VIH, Vin VIH or Vin VIL. CS Vcc - 0.3 V, Iout = 0 mA. Vin Vcc - 0.3 V or Vin 0.3 V. Vcc max, Iout = 0 mA, Vin = Gnd/Vcc. Duty cycle 100 %, F = 5 MHz, derating = 10 mA/MHz. Preliminary. Please consult sales.
Data Retention Mode
MHS CMOS RAM's are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention : 1. Chip select (CS) must be held high during data retention ; within Vcc to Vcc - 0.2 V. 2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation. 3. CS must be kept between Vcc -0.3 V and 70 % of Vcc during the power up and power down transitions. 4. The RAM can begIn operation > 45 ns after Vcc reaches the minimum operating voltage (4.5 V).
Timing
Rev. E - June 30,1999)
3
M65656G
Data Retention Characteristics
PARAMETER
VCCDR TCDR TR ICCDR1 (10) ICCDR2 (10)
DESCRIPTION
Vcc for data retention Chip deselect to data retention time Operation recovery time Data retention current @ 2.0 V : M-65656GV Data retention current @ 3.0 V : M-65656GV
MINIMUM
2.0 0.0 TAVAV (9)
TYPICAL (8)
- - - 0.1 0.3
MAXIMUM
- - - 80 90
UNIT
V ns ns A A
Notes :
8. TA = 25C. 9. TAVAV = Read cycle time. 10. CS = Vcc, Vin = Gnd/Vcc, this parameter is only tested at Vcc = 2 V.
4
Rev. E - June 30,1999)
M65656G
AC Parameters
AC Conditions
Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output load : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See fig. 1a, 1b
Write Cycle
SYMBOL
TAVAV TAVWL TAVWH TDVWH TELWH TWLQZ TWLWH (11) TWHAX TWHDX TWHQX (11)
PARAMETER
Write cycle time Address set-up time Address valid to end of write Data set-up time CS low to write end Write low to high Z Write pulse width Address hold to end of write Data hold time Write high to low Z
M65656G - 40
40 0 30 22 30 15 30 0 0 0
M65656G - 55
55 0 40 25 40 20 40 0 0 0
UNIT
ns ns ns ns ns ns ns ns ns ns
VALUE
min min min min min min min min min min
Notes : 11. Specified with CL = 5 pF (see figure 1b). Guaranteed but not tested.
Rev. E - June 30,1999)
5
M65656G
Write Cycle 1 : W Controlled (note 12)
Write Cycle 2 : CS Controlled (note 12)
Note :
12. The internal write time of the memory is defined by the overlap of CS LOW and W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. Data out is high impedance if OE = VIH.
AC Test Loads and Waveforms
Figure 1 a Figure 1 b Figure 2
Equivalent to : THEVENIN EQUIVALENT
6
Rev. E - June 30,1999)
M65656G
Read Cycle
SYMBOL
TAVAV TAVQV TAVQX TELQV TELQX(13) TEHQZ(13) TGLQV TGLQX(13) TGHQZ(13)
PARAMETER
Read cycle time Address access time Address valid to low Z Chip-select access time CS low to low Z CS high to high Z Output Enable access time OE low to low Z OE high to high Z
M65656G - 40
40 40 5 40 5 15 20 5 15
M65656G - 55
55 55 5 55 5 15 25 5 20
UNIT
ns ns ns ns ns ns ns ns ns
VALUE
min max min max min max max min max
Notes : 13. Specified with CL = 5 pF (see figure 1b). Guaranteed but not tested.
Rev. E - June 30,1999)
7
M65656G
Read Cycle nb 1 (notes 14, 15)
Read Cycle nb 2 (notes 14, 16)
Notes : 14. W is high for read cycle. 15. Device is continuously selected CS & OE = VIL. 16. Address valid prior to or coincident with CS transition low.
8
Rev. E - June 30,1999)
M65656G
Ordering Information
TEMPERATURE RANGE S M PACKAGE CP DEVICE - 65656 GRADE V SPEED - 40 FLOW SC
M = Military S = Space
-55 to +125C 32K x 8 STATIC RAM V = Very low power
35 ns 45 ns
CP = 28 pins DIL SIDE-BRAZED 300 mils DP = 28 pins Multilayers flat pack 0 = die
blank /883 SB/SC QM SV
= = = = =
MHS standards MIL STD 883 Class B or S SCC 9000 level B/C QML-Q QML-V
The information contained herein is subject to change without notice. No responsibility is assumed by TEMIC for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
Rev. E - June 30,1999)
9

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