View MAX9965-MAX9966_990692.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-3016; Rev 1; 1/04
Quad Low-Power, 500Mbps ATE Driver/Comparator
General Description
The MAX9965/MAX9966 four-channel, low-power, highspeed pin electronics driver and comparator ICs include for each channel a three-level pin driver, comparator, and variable clamps. The MAX9965/MAX9966 are similar to the MAX9963/MAX9964, but with even lower window comparator dispersion for enhanced accuracy. The driver features a wide voltage range and high-speed operation, includes high-Z and active termination (3rd-level drive) modes, and is highly linear even at low-voltage swings. The dual bipolar-input comparator provides very low dispersion (timing variation) over a wide variety of input conditions. The clamps provide damping of high-speed DUT waveforms when the device is configured as a high-impedance receiver. High-speed, differential control inputs compatible with ECL, LVPECL, LVDS, and GTL levels are provided for each channel. ECL/LVPECL or flexible open-collector outputs are available for the comparators. The A-grade version provides tight matching of gain and offset for the driver and comparator, allowing reference levels to be shared across multiple channels in cost-sensitive systems. For system designs that incorporate independent reference levels for each channel, the B-grade version is available at reduced cost. Optional internal resistors at the high-speed inputs provide differential termination of LVDS inputs, while optional internal resistors provide the pullup voltage and source termination for open-collector comparator outputs. These features significantly reduce the discrete component count on the circuit board. The MAX9965/MAX9966 operating range is -1.5V to +6.5V, with powerdissipation of only 975mW per channel. These devices are available in a 100-pin, 14mm x 14mm body, 0.5mm pitch TQFP with an exposed 8mm x 8mm die pad on the top (MAX9965) or bottom (MAX9966) of the package for efficient heat removal. The MAX9965/MAX9966 are specified to operate with an internal die temperature of +60C to +100C, and feature a die temperature monitor output.
Features
Small Footprint: Four Channels in 0.4in2 Low Power Dissipation: 975mW/Channel (typ) High Speed: 500Mbps at 3VP-P Very Low Timing Dispersion Wide Operating Range: -1.5V to +6.5V Active Termination (3rd-Level Drive) Low-Leakage Mode: 15nA Maximum Integrated Clamps Interface Easily with Most Logic Families Digitally Programmable Slew Rate Internal Logic Termination Resistors Low Gain and Offset Error
MAX9965/MAX9966
Ordering Information
PART MAX9965ADCCQ* MAX9965AKCCQ* MAX9965AGCCQ* MAX9965AHCCQ* MAX9965AJCCQ* MAX9965BDCCQ* MAX9965BKCCQ* MAX9965BGCCQ MAX9965BHCCQ* MAX9965BJCCQ MAX9966ADCCQ* MAX9966AKCCQ* MAX9966AGCCQ* MAX9966AHCCQ* MAX9966AJCCQ* MAX9966BDCCQ* MAX9966BKCCQ* MAX9966BGCCQ MAX9966BHCCQ* TEMP RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 100 TQFP-EPR*** 100 TQFP-EPR*** 100 TQFP-EPR*** 100 TQFP-EPR*** 100 TQFP-EPR*** 100 TQFP-EPR*** 100 TQFP-EPR*** 100 TQFP-EPR*** 100 TQFP-EPR*** 100 TQFP-EPR*** 100 TQFP-EP** 100 TQFP-EP** 100 TQFP-EP** 100 TQFP-EP** 100 TQFP-EP** 100 TQFP-EP** 100 TQFP-EP** 100 TQFP-EP** 100 TQFP-EP**
Applications
Memory Testers Low-Cost Mixed-Signal/System-on-Chip Testers Structural Testers Pattern/Data Generators
MAX9966BJCCQ* 0C to +70C 100 TQFP-EP** *Future product--contact factory for availability. **EP = Exposed pad. ***EPR = Exposed pad reversed.
Pin Configurations and Selector Guide appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
ABSOLUTE MAXIMUM RATINGS
VCC to GND .........................................................-0.3V to +11.5V VEE to GND............................................................-7.0V to +0.3V All Other Pins ...................................(VEE - 0.3V) to (VCC + 0.3V) VCC - VEE ................................................................-0.3V to +18V DUT_ to GND.........................................................-2.5V to +7.5V DATA_, NDATA_, RCV_, NRCV_ to GND ................-2.5 to +5.0V DATA_ to NDATA_ ............................................................1.5V RCV_ to NRCV_ ................................................................1.5V VCCO_ _ to GND .......................................................-0.3V to +5V SCLK, DIN, CS, RST to GND ..................................-1.0V to +5V DHV_, DLV_, DTV_, CHV_, CLV_ to GND .............-2.5V to +7.5V CPHV_ to GND ......................................................-2.5V to +8.5V CPLV_ to GND.......................................................-3.5V to +7.5V DHV_ to DLV_....................................................................10V DHV_ to DTV_....................................................................10V DLV_ to DTV_ ....................................................................10V CHV_ or CLV_ to DUT_......................................................10V CH_, NCH_, CL_, NCL_ to GND...............................-2.5V to +5V Current into DHV_, DLV_, DTV_, CHV_, CLV_, CPHV_, CPLV_........................................10mA Current into TEMP ............................................-0.5mA to +20mA DUT_ Short Circuit to -1.5V to +6.5V .........................Continuous Power Dissipation (TA = +70C) MAX9965__CCQ (derate 167mW/C above +70C) ...............................................................13.3W* MAX9966__CCQ (derate 47.6mW/C above +70C) .................................................................3.8W* Storage Temperature Range .............................-65C to +150C Junction Temperature ...................................................+125C Lead Temperature (soldering, 10s) ...............................+300C
*Dissipation wattage values are based on still air with no heat sink for the MAX9965 and slug soldered to board copper for the MAX9966. Actual maximum power dissipation is a function of users' heat extraction technique and may be substantially higher.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +9.75V, VEE = -5.25V, VCCO_ _ = 2.5V, SC1 = SC0 = 0, VCPHV_ = 7.2V, VCPLV_ = -2.2V, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +60C to +100C, unless otherwise noted.) (Note 1)
PARAMETER POWER SUPPLIES Positive Supply Negative Supply Positive Supply Negative Supply Power Dissipation DUT_ CHARACTERISTICS Operating Voltage Range Max Leakage Current in High-Z Mode Leakage Current in Low-Leakage Mode Combined Capacitance Low-Leakage Enable Time Low-Leakage Disable Time Low-Leakage Recovery VDUT IDUT (Note 4) LLEAK = 0, 0 VDUT_ 3V LLEAK = 0, VDUT_ = -1.5V, 6.5V LLEAK = 1, 0 VDUT_ 3V, TJ < +90C IDUT LLEAK = 1, VDUT_ = -1.5V,TJ < +90C LLEAK = 1, VDUT_ = 6.5V, TJ < +90C CDUT Driver in term mode (DUT_ = DTV_) Driver in high-Z mode (Notes 5, 7) (Notes 6, 7) Time to return to the specified maximum leakage after a 3V, 4V/ns step at DUT_ (Note 7) 3 5 20 20 10 -1.5 +6.5 2 5 15 30 30 pF s s s nA V A VCC VEE ICC IEE PD (Note 2) (Note 2) (Notes 2, 3) 9.5 -6.5 9.75 -5.25 200 -370 3.9 10.5 -4.5 225 -425 4.5 V V mA mA W SYMBOL CONDITIONS MIN TYP MAX UNITS
2
_______________________________________________________________________________________
Quad Low-Power, 500Mbps ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ _ = 2.5V, SC1 = SC0 = 0, VCPHV_ = 7.2V, VCPLV_ = -2.2V, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +60C to +100C, unless otherwise noted.) (Note 1)
PARAMETER Input Bias Current Settling Time Input High Voltage Input Low Voltage Differential Input Voltage Input Resistor VIH VIL VDIFF MAX996_ _GCCQ, MAX996_ _JCCQ, between signal and complement VIH VIL fSCLK tCH tCL tCSS0 tCSS1 tCSH1 tDS tDH tCSWH TJ = +70C, RL 10M 8 8 3.5 3.5 3.5 3.5 3.5 20 3.43 +10 15 SYMBOL IBIAS To 5mV -1.6 -2.0 0.15 96 1 +3.5 +3.1 1.0 104 CONDITIONS MIN TYP MAX 25 UNITS A s V V V
MAX9965/MAX9966
LEVEL PROGRAMMING INPUTS (DHV_, DLV_, DTV_, CHV_, CLV_, CPHV_, CPLV_)
DIFFERENTIAL CONTROL INPUTS (DATA_, NDATA_, RCV_, NRCV_)
SINGLE-ENDED CONTROL INPUTS (CS, RST, SCLK, DIN) Input High Voltage Input Low Voltage SCLK Frequency SCLK Pulse Width High SCLK Pulse Width Low CS Low to SCLK High Setup CS High to SCLK High Setup SCLK High to CS High Hold DIN to SCLK High Setup DIN to SCLK High Hold CS Pulse Width High TEMPERATURE MONITOR (TEMP) Nominal Voltage Temperature Coefficient Output Resistance DRIVERS (Note 8) DC OUTPUT CHARACTERISTICS (RL 10M ) DHV_, DLV_, DTV_, Output Offset Voltage DHV_, DLV_, DTV_, Gain DHV_, DLV_, DTV_, Output Voltage Temperature Coefficient Linearity Error VOS AV At DUT_ with VDHV_= 3V, VDTV_= 1.5V, VDLV_= 0 Measured with VDHV_, VDLV_, VDTV_ at 0 and 4.5V MAX996_B MAX996_B 0.96 75 5 15 100 1.001 mV V/V V/C mV V mV/C k 1.6 -0.1 3.5 +0.9 50 V V MHz ns ns ns ns ns ns ns ns
SERIAL INTERFACE TIMING (Figure 5)
Includes both gain and offset temperature effects 0V VDUT_ 3V (Note 9) Full range (Notes 9, 10)
_______________________________________________________________________________________
3
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ _ = 2.5V, SC1 = SC0 = 0, VCPHV_ = 7.2V, VCPLV_ = -2.2V, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +60C to +100C, unless otherwise noted.) (Note 1)
PARAMETER DHV_ to DLV_ Crosstalk DLV_ to DHV_ Crosstalk DTV_ to DLV_ and DHV_ Crosstalk DHV_ to DTV_ Crosstalk DLV_ to DTV_ Crosstalk DHV_, DLV_, DTV_ DC Power-Supply Rejection Ratio Maximum DC Drive Current DC Output Resistance DC Output Resistance Variation PSRR IDUT_ RDUT_ RDUT_ IDUT_ = 30mA (Note 11) IDUT_ = 1.0mA to 40mA VDLV_ = 0, VDHV_ = 0.1V Drive Mode Overshoot Term Mode Overshoot Settling Time to Within 25mV Settling Time to Within 5mV Prop Delay, Data to Output Prop Delay Match, TLH vs. THL Prop Delay Match, Drivers Within Package Prop Delay Temperature Coefficient Prop Delay Change vs. Pulse Width Prop Delay Change vs. Common-Mode Voltage Prop Delay, Drive to High-Z Prop Delay, High-Z to Drive Prop Delay, Drive to Term Prop Delay, Term to Drive tPDDZ tPDZD tPDDT tPDTD 3VP-P, 40MHz, 2.5ns to 22.5ns pulse width, relative to 12.5ns pulse width VDHV_ - VDLV_ = 1V, VDHV_ = 0 to 6V VDHV_ = 1.0V, VDLV_ = -1.0V, VDTV_ = 0 VDHV_ = 1.0V, VDLV_ = -1.0V, VDTV_ = 0 VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V 0.2 VP-P, 20% to 80% Rise and Fall Time tR , tF 1 VP-P, 10% to 90% 3 VP-P, 10% to 90% 5 VP-P, 10% to 90% 500 1.1 tPDD 3VP-P (Note 15) VDLV_ = 0, VDHV_ = 1V VDLV_ = 0, VDHV_ = 3V (Note 12) 3V step (Note 13) 3V step (Note 13) SYMBOL CONDITIONS VDLV_ = 0, VDHV_ = 200mV, 6.5V VDHV_ = 5V, VDLV_ = -1.5V, 4.8V VDHV_ = 3V, VDLV_ = 0, VDTV_ = -1.5V, +6.5V VDTV_ = 1.5V, VDLV_ = 0, VDHV_ =1.6V, 3V VDTV_ = 1.5V, VDHV_ = 3V, VDLV_ = 0, 1.4V VCC and VEE independently set to their min/max values 40 60 49 50 1 30 40 50 0 10 20 2 50 40 +3 60 85 2.9 2.9 2.3 2.0 330 670 1.3 2.0 800 1.6 2.75 mV ns ns ns ps ps ps/C ps ps ns ns ns ns mV 120 51 2.5 MIN TYP MAX 2 2 2 3 3 UNITS mV mV mV mV mV dB mA
DYNAMIC OUTPUT CHARACTERISTICS (ZL = 50)
TIMING CHARACTERISTICS (ZL = 50) (Note 14)
DYNAMIC PERFORMANCE (ZL = 50) ps ns
4
_______________________________________________________________________________________
Quad Low-Power, 500Mbps ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ _ = 2.5V, SC1 = SC0 = 0, VCPHV_ = 7.2V, VCPLV_ = -2.2V, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +60C to +100C, unless otherwise noted.) (Note 1)
PARAMETER SC1 = 0, SC0 = 1 Slew Rate SC1 = 1, SC0 = 0 Slew Rate SC1 = 1, SC0 = 1 Slew Rate SYMBOL CONDITIONS Percent of full speed (SC0 = SC1 = 0), 3VP-P, 20% to 80% Percent of full speed (SC0 = SC1 = 0), 3VP-P, 20% to 80% Percent of full speed (SC0 = SC1 = 0), 3VP-P, 20% to 80% 0.2VP-P, VDHV_ = 0.2V, VDLV_ = 0 Minimum Pulse Width (Note 16) 1VP-P, VDHV_ = 1V, VDLV_ = 0 3VP-P, VDHV_ = 3V, VDLV_ = 0 5VP-P, VDHV_ = 5V, VDLV_ = 0 0.2VP-P, VDHV_ = 0.2V, VDLV_ = 0 Data Rate (Note 17) 1VP-P, VDHV_ = 1V, VDLV_ = 0 3VP-P, VDHV_ = 3V, VDLV_ = 0 5VP-P, VDHV_ = 5V, VDLV_ = 0 Dynamic Crosstalk Rise and Fall Time, Drive to Term Rise and Fall Time, Term to Drive COMPARATORS DC CHARACTERISTICS Input Voltage Range Differential Input Voltage Hysteresis Input Offset Voltage Input Offset Voltage Temperature Coefficient Common-Mode Rejection Ratio Linearity Error Power-Supply Rejection Ratio AC CHARACTERISTICS (Note 22) MAX996_ _GCCQ Minimum Pulse Width Prop Delay Prop Delay Temperature Coefficient tPW(MIN) tPDL (Note 23) MAX996_ _HCCQ, MAX996_ _JCCQ 0.6 0.9 1.2 2.6 2.0 ns ns ps/C PSRR CMRR VDUT_ = -1.5V, 6.5V (Note 20) VDUT_ = 1.5V (Note 9) VDUT_ = -1.5V and 6.5V (Note 9) VDUT_ = -1.5V, 6.5V (Note 21) 50 50 VIN VDIFF VHYST VOS VDUT_ = 1.5V MAX996_B 50 55 1 1 66 5 10 (Note 4) -1.5 8 0 100 +6.5 V V mV mV V/C dB mV dB (Note 18) VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, tDTR, tDTF 10% to 90% (Note 19) tTDR, tTDF VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, 10% to 90% (Note 19) MIN TYP 75 50 25 0.65 1.0 2.0 2.9 1700 1000 500 350 20 1.6 0.7 mVP-P ns ns Mbps ns MAX UNITS % % %
MAX9965/MAX9966
_______________________________________________________________________________________
5
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ _ = 2.5V, SC1 = SC0 = 0, VCPHV_ = 7.2V, VCPLV_ = -2.2V, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +60C to +100C, unless otherwise noted.) (Note 1)
PARAMETER Prop Delay Match, High/Low vs. Low/High Prop Delay Match, Comparators Within Package Prop Delay Dispersion vs. Common-Mode Input Prop Delay Dispersion vs. Overdrive Prop Delay Dispersion vs. Pulse Width Prop Delay Dispersion vs. Slew Rate (Note 15) VCHV_ = VCLV_ = -1.4, 6.4V (Note 24) 50mV to 500mV 2.0ns to 23ns pulse width, relative to 12.5ns pulse width MAX996_ _GCCQ MAX996_ _HCCQ, MAX996_ _JCCQ SYMBOL CONDITIONS MIN TYP 40 40 20 60 25 45 50 50 ps High-Z mode 250 ps MAX UNITS ps ps ps ps
0.5V/ns to 6.5V/ns slew rate, peak-to-peak variation VDUT_ = 1.0VP-P, tR = tF = 1.0ns 10% to 90%, relative to timing at 50% point Term mode
ps
Waveform Tracking 10% to 90%
OPEN-COLLECTOR LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_: MAX996_ _GCCQ) VCCO_ _ Voltage Range Output Low Voltage Compliance Output High Voltage Output Low Voltage Output Voltage Swing Termination Resistor Differential Rise Time Differential Fall Time VCCO_ _ Voltage Range VCCO_ _ Supply Current Output High Voltage Output Low Voltage Output Voltage Swing RTERM tR tF VCCO_ _ IVCCO_ _ VOH VOL All outputs 50 to (VVCCO_ _ - 2V) 50 to (VVCCO_ _ - 2V) 50 to (VVCCO_ _ - 2V) 50 to (VVCCO_ _ - 2V) 800 Single-ended measurement from VCCO_ _ to CH_, NCH_, CL_, NCL_ 20% to 80% 20% to- 80% -0.1 330 VCCO_ _ VCCO_ _ -1 - 0.88 VCCO_ _ VCCO_ _ - 1.73 - 1.6 850 900 VOH VOL VVCCO_ _ Set by IOUT, RTERM, and VCCO_ _ ICH_ = INCH_ = ICL_ = INCL_ = 0 ICH_ = INCH_ = ICL_ = INCL_ = 0 0.350 48 200 200 3.5 0 -0.5 VCCO_ _ VCCO_ _ - 0.1 - 0.02 VCCO_ _ - 0.4 0.380 0.442 52 3.5 V V V V V ps ps V mA V V mV
OPEN-EMITTER LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_: MAX996_ _JCCQ)
6
_______________________________________________________________________________________
Quad Low-Power, 500Mbps ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ _ = 2.5V, SC1 = SC0 = 0, VCPHV_ = 7.2V, VCPLV_ = -2.2V, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +60C to +100C, unless otherwise noted.) (Note 1)
PARAMETER Differential Rise Time Differential Fall Time CLAMPS High Clamp Input Voltage Range Low Clamp Input Voltage Range Clamp Offset Voltage Offset Voltage Temperature Coefficient VCC and VEE independently set to their min and max values, IDUT_ = 1mA, VCPHV_ = 0 VCC and VEE independently set to their min and max values, IDUT_ = -1mA, VCPLV_ = 0 Voltage Gain Voltage Gain Temperature Coefficient IDUT_ = 1mA, VCPLV_ = -1.5V, VCPHV_ = -0.3V to 6.5V IDUT_ = -1mA, VCPHV_ = 6.5V, VCPLV_ = -1.5V to 5.3V Short-Circuit Output Current IDUT VCPHV_ = 0, VCPLV_ = -1.5V, VDUT_ = 6.5V VCPLV_ = 5V, VCPHV_ = 6.5V, VDUT_ = -1.5V VCPHV_ = 3V, VCPLV_ = 0, IDUT = -5mA and -15mA VCPHV_ = 3V, VCPLV_ = 0, IDUT = 5mA and 15mA 50 -95 50 50 AV 40 dB 40 0.96 -100 10 mV 10 95 -50 55 55 mA 1.00 V/V ppm/C VCPH_ VCPL_ VOS At DUT_ with IDUT_ = 1mA, VCPHV_ = 1.5V At DUT_ with IDUT_ = -1mA, VCPLV_ = 1.5V 0.5 -0.3 -2.5 +7.5 +5.3 100 100 V V mV mV/C SYMBOL tR tF 20% to 80% 20% to 80% CONDITIONS MIN TYP 500 500 MAX UNITS ps ps
MAX9965/MAX9966
Clamp Power-Supply Rejection
PSRR
Clamp Linearity
Clamp DC Impedance
ROUT
Note 1: All min and max limits are 100% tested in production. Tests are performed at worst-case supply voltages where applicable. Note 2: Total for quad device at worst-case setting. RL 10M. The applicable supply currents are measured with typical supply voltages. Note 3: Does not include internal dissipation of the comparator outputs. With output loads of 50 to (VVCCO_ _ - 2V), this adds 240mW typical to the total chip power (MAX996_ _HCCQ, MAX996_ _JCCQ). Note 4: Provided that the Absolute Maximum Ratings are not exceeded, externally forced voltages may exceed this range. Note 5: Transition time from LLEAK being asserted to leakage current dropping below specified limits. Note 6: Transition time from LLEAK being deasserted to output returning to normal operating mode. Note 7: Based on simulation results only. Note 8: With the exception of Offset and Gain/CMRR tests, reference input values are calibrated for offset and gain. Note 9: Relative to straight line between 0 and 3V. Note 10: Full ranges are -1.3V VDHV_ 6.5V, -1.5V VDTV_ 6.5V, -1.5V VDLV_ 6.3V. Note 11: Nominal target value is 50. Contact factory for alternate trim selections within the 40 to 50 range. Note 12: VDTV_ = 1.5V, RS = 50. External signal driven into T-line is a 0 to 3V edge with 1.2ns rise time (10% to 90%). Measurement is made using the comparator. Note 13: Measured from the crossing point of DATA_ inputs to the settling of the driver output. _______________________________________________________________________________________ 7
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
Note 14: Prop delays are measured from the crossing point of the differential input signals to the 50% point of expected output swing. Rise time of the differential inputs DATA_ and RCV_ is 250ps (10% to 90%). Note 15: Rising edge to rising edge or falling edge to falling edge. Note 16: Specified amplitude is programmed. At this pulse width, the output reaches at least 95% of its nominal (DC) amplitude. The pulse width is measured at DATA_. Note 17: Specified amplitude is programmed. Maximum data rate specified in transitions per second. A square wave that reaches at least 95% of its programmed amplitude may be generated at one-half of this frequency. Note 18: Crosstalk from any driver to the other three channels. Aggressor channel is driving 3VP-P into a 50 load. Victim channels are in term mode with VDTV_ = 1.5V. Note 19: Indicative of switching speed from DHV_ or DLV_ to DTV_ and DTV_ to DHV_ or DLV_ when VDLV_ < VDTV_ < VDHV_. If VDTV_ < VDLV_ or VDTV_ > VDHV_, switching speed is degraded by approximately a factor of 3. Note 20: Change in Offset Voltage over input range. Note 21: Change in Offset Voltage with power supplies independently set to their minimum and maximum values. Note 22: Unless otherwise noted, all Prop Delays are measured at 40MHz, VDUT_ = 0 to 2V, VCHV_ = VCLV_ = 1V, slew rate = 2V/ns, ZS = 50, driver in Term Mode with VDTV_ = 0V. Comparator outputs are terminated with 50 to GND at scope input with VCCO_ _ = 2V. Open-collector outputs are also terminated (internally or externally) with RTERM = 50 to VCCO_ _. Measured from VDUT_ crossing calibrated CHV_/CLV_ threshold to crossing point of differential outputs. Note 23: VDUT_ = 0 to 1V, VCHV_ = VCLV_ = 0.5V. At this pulse width, the output reaches at least 90% of its DC Voltage swing. The pulse width is measured at the crossing points of the differential outputs. Note 24: Relative to propagation delay at VCHV_ = VCLV_ = 1.5V. VDUT_ = 200mVP-P. Overdrive = 100mV.
8
_______________________________________________________________________________________
Quad Low-Power, 500Mbps ATE Driver/Comparator
Typical Operating Characteristics
MAX9965/MAX9966
DRIVER SMALL-SIGNAL RESPONSE
MAX9965 toc01
DRIVER LARGE-SIGNAL RESPONSE
DLV_ = 0V RL = 50
MAX9965 toc02
DRIVE TO TERM TRANSITION
MAX9965 toc03
DLV_ = 0V RL = 50
DHV_ = 500mV DHV_ = 200mV
DHV_ = 5V DHV_ = 3V
DHV_ TO DTV_ V = 0.25V/div
V = 500mV/div
V = 50mV/div
DLV_ TO DTV_ 0 DHV_ = 100mV t = 2.5ns/div 0 DHV_ = 1V t = 2.5ns/div 0 RL = 50 t = 5.0ns/div
DRIVER TRAILING-EDGE TIMING ERROR vs. PULSE WIDTH
MAX9965 toc04
DRIVER TIME DELAY vs. COMMON-MODE VOLTAGE
55 45 TIME DELAY (ps) 35 25 15 5 -5 FALLING EDGE RISING EDGE V = 0.25V/div NORMALIZED TO VCM = 1.5V
MAX9965 toc05
HIGH-Z TO DRIVE TRANSITION
MAX9965 toc06
40 20 TIMING ERROR (ps) 0 -20 -40 -60 HIGH PULSE -80 -100 0 NORMALIZED TO PW = 12.5ns PERIOD = 25ns, DHV_ = 3V, DLV_ = 0V 5 10 15 20 LOW PULSE
65
HIGH-Z TO DHV_
0
-15 -25 -35 25 0 1 2 3 4 5 6
HIGH-Z TO DLV_ RL = 50 t = 5.0ns/div
PULSE WIDTH (ns)
COMMON-MODE VOLTAGE (V)
DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE
MAX9965 toc07
DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE
MAX9965 toc08
DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE
DUT_ = DTV_
MAX9965 toc09
6 5 4 LINEARITY ERROR (mV) 3 2 1 0 -1 -2 -3 -4 -5 -6 -1.5 -0.5 0.5 1.5 2.5 3.5
DUT_ = DHV_
6 5 4 LINEARITY ERROR (mV) 3 2 1 0 -1 -2 -3 -4 -5 -6
DUT_ = DLV_
6 5 4 LINEARITY ERROR (mV) 3 2 1 0 -1 -2 -3 -4 -5 -6
4.5
5.5
6.5
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
6.5
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
6.5
VDUT_ (V)
VDUT_ (V)
VDUT_ (V)
_______________________________________________________________________________________
9
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
Typical Operating Characteristics (continued)
CROSSTALK TO DUT_ FROM DLV_ WITH DUT_ = DHV_
MAX9965 toc10
CROSSTALK TO DUT_ FROM DTV_ WITH DUT_ = DHV_
MAX9965 toc11
CROSSTALK TO DUT_ FROM DHV_ WITH DUT_ = DLV_
1.6 1.2 DUT_ ERROR (mV) 0.8 0.4 0 -0.4 -0.8 -1.2 DLV_ = 0 DTV_ = 1.5V
MAX9965 toc12
2.0 1.6 1.2 DUT_ ERROR (mV) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 -2.0
DHV_ = 5V DTV_ = 1.5V
0.5 0.4 0.3 DUT_ ERROR (mV) 0.2 0.1 0 -0.1 -0.2 -0.3
DHV_ = 3V DLV_ = 0
2.0
NORMALIZED AT DLV_ = 0V -1.5 0 1.5 3.0 4.5 6.0
-0.4 -0.5
NORMALIZED AT DTV_ = 1.5V -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
-1.6 -2.0 -0.5 0.5 1.5
NORMALIZED AT DHV_ = 5V 2.5 3.5 4.5 5.5 6.5
DLV_ VOLTAGE (V)
DTV_ VOLTAGE (V)
DHV_ VOLTAGE (V)
CROSSTALK TO DUT_ FROM DTV_ WITH DUT_ = DLV_
MAX9965 toc13
CROSSTALK TO DUT_ FROM DLV_ WITH DUT_ = DTV_
MAX9965 toc14
CROSSTALK TO DUT_ FROM DHV_ WITH DUT_ = DTV_
DTV_ = 1.5V DLV_ = -1.5V
MAX9965 toc15
0.5 0.4 0.3 DUT_ ERROR (mV) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
DLV_ = 0 DHV_ = 3V
2.0 1.5 DUT_ ERROR (mV) 1.0 0.5 0 -0.5
DTV_ = 1.5V DHV_ = 6.5V
1.0 0.5 DUT_ ERROR (mV) 0 -0.5 -1.0 -1.5
NORMALIZED AT DTV_ = 1.5V -1.0 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 -1.5 0
NORMALIZED AT DLV_ = 0 -2.0 1.5 3.0 4.5 6.0 -0.5 0.5 1.5
NORMALIZED AT DHV_ = 3V 2.5 3.5 4.5 5.5 6.5
DTV_ VOLTAGE (V)
DLV_ VOLTAGE (V)
DHV_ VOLTAGE (V)
DRIVER GAIN vs. TEMPERATURE
MAX9965 toc16
DRIVER OFFSET vs. TEMPERATURE
MAX9965 toc17
COMPARATOR OFFSET vs. COMMON-MODE VOLTAGE
1.5 1.0 OFFSET (mV) 0.5 0 -0.5 -1.0 -1.5 NORMALIZED AT VCM = 1.5V -2.0
MAX9965 toc18
1.0008 1.0006 1.0004 1.0002 1.0000 0.9998 0.9996 NORMALIZED AT TJ = +85C 0.9994 60 70 80 TEMPERATURE (C) 90
0.25 NORMALIZED AT TJ = +85C 0.20 0.15 OFFSET (mV) 0.10 0.05 0 -0.05 -0.10
2.0
GAIN (V/V)
100
60
70
80 TEMPERATURE (C)
90
100
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
6.5
COMMON-MODE VOLTAGE (V)
10
______________________________________________________________________________________
Quad Low-Power, 500Mbps ATE Driver/Comparator
Typical Operating Characteristics (continued)
MAX9965/MAX9966
COMPARATOR RISING EDGE TIMING VARIATION vs. COMMON-MODE VOLTAGE
MAX9965 toc19
COMPARATOR FALLING EDGE TIMING VARIATION vs. COMMON-MODE VOLTAGE
MAX9965 toc20
COMPARATOR TIMING VARIATION vs. OVERDRIVE
130 110 90 DELAY (ps) FALLING EDGE
MAX9965 toc21
100 75 TIMING VARIATION (ps) 50 25 0 -25 -50 -75 -100 NORMALIZED TO ZERO AT VCM = 1.5V -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
100 75 TIMING VARIATION (ps) 50 25 0 -25 -50 -75 -100 NORMALIZED TO ZERO AT VCM = 1.5V -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
150
70 50 30 10 -10 -30 -50 RISING EDGE 0 0.1 0.2 0.3 0.4 0.5 0.6
6.5
6.5
COMMON-MODE VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
OVERDRIVE (V)
COMPARATOR TRAILING EDGE TIMING ERROR vs. PULSE WIDTH, MAX996_ _GCCQ
NORMALIZED TO PW = 12.5ns PERIOD = 25ns
MAX9965 toc22
COMPARATOR TRAILING EDGE TIMING ERROR vs. PULSE WIDTH, MAX996_ _JCCQ
MAX9965 toc23
COMPARATOR TIMING VARIATION vs. INPUT SLEW RATE, DUT_ RISING
MAX9965 toc24
30 20 TIMING ERROR (ps) 10 0 -10 -20 LOW PULSE -30 -40 0 5 10 15 20 HIGH PULSE
40 20 0 TIMING ERROR (ps) -20 -40 -60 -80 -100 -120 -140 0 NORMALIZED TO PW = 12.5ns PERIOD = 25ns 5 10 15 20 HIGH PULSE LOW PULSE
60 50 PROPAGATION DELAY (ps) 40 30 20 10 0 NORMALIZED TO SR = 2V/ns -10
25
25
0.5
1.5
2.5
3.5
4.5
5.5
6.5
PULSE WIDTH (ns)
PULSE WIDTH (ns)
SLEW RATE (V/ns)
COMPARATOR TIMING VARIATION vs. INPUT SLEW RATE, DUT_ FALLING
MAX9965 toc25
COMPARATOR DIFFERENTIAL OUTPUT RESPONSE (MAX996_ _GCCQ)
MAX9965 toc26
COMPARATOR DIFFERENTIAL OUTPUT RESPONSE (MAX996_ _JCCQ)
MAX9965 toc27
60 50 PROPAGATION DELAY (ps) 40 30 20 10 0 NORMALIZED TO SR = 2V/ns -10 0.5 1.5 2.5 3.5 4.5 5.5
VDUT = 50mV/div
0
VDUT = 200mV/div t = 2.50ns/div VDUT = 0 TO 3V PULSE, CHV_ = CLV_ = 1.5V, EXTERNAL LOAD = 50
0
6.5
t = 2.50ns/div VDUT = 0 TO 3V PULSE, CHV_ = CLV_ = 1.5V, EXTERNAL LOAD = 50
SLEW RATE (V/ns)
______________________________________________________________________________________
11
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
Typical Operating Characteristics (continued)
COMPARATOR RESPONSE vs. HIGH SLEW-RATE OVERDRIVE
MAX9965 toc28
COMPARATOR OFFSET vs. TEMPERATURE
MAX9965 toc29
CLAMP RESPONSE
MAX9965 toc30
0.6 0.4 0.2
TERM MODE
RISING V = 500mV/div
V = 500mV/div
OFFSET (mV)
INPUT
DIGITIZED OUTPUT
0 -0.2 -0.4
FALLING 0 NORMALIZED TO TJ = +85C 75 79 83 87 91 95 t = 5.0ns/div VDUT = 0V TO 3V SQUARE WAVE, RS = 25 CPLV_ = -0.1V, CPHV_ = +3.1V
0 INPUT SLEW-RATE = 17V/ns t = 2.50ns/div
-0.6 -0.8
TEMPERATURE (C)
HIGH-Z LEAKAGE CURRENT vs. DUT_ VOLTAGE
MAX9965 toc31
CLAMP CURRENT vs. DIFFERENCE VOLTAGE
1200 1100 1000 900 800 700 600 500 400 300 200 100 0 -100 CPHV_ VOLTAGE (V) VDUT_ = 3V 100 0 -100 -200 -300 -400 -500 -600 -700 -800 -900 -1000 -1100 -1200 -1.50
MAX9965 toc32
CLAMP CURRENT vs. DIFFERENCE VOLTAGE
MAX9965 toc33
1.2 1.0 LEAKAGE CURRENT (A) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
DUT_ CURRENT (A)
DUT_ CURRENT (A)
VDUT_ = 0 -1.25 -1.00 -0.75 -0.50 -0.25 0
6.5
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
DUT_ VOLTAGE (V)
CPLV_VOLTAGE (V)
LOW-LEAKAGE CURRENT vs. DUT_ VOLTAGE
MAX9965 toc34
DRIVER REFERENCE CURRENT vs. INPUT VOLTAGE
1.4 1.3 INPUT CURRENT (A) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -0.75 -1.00 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 DLV_ DHV_ DTV_
MAX9965 toc35
COMPARATOR REFERENCE INPUT CURRENT vs. INPUT VOLTAGE
0.75 INPUT CURRENT (A) 0.50 0.25 0 -0.25 -0.50 CLV_ CHV_
MAX9965 toc36
0 -0.5 LEAKAGE CURRENT (nA) -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
1.5
1.00
6.5
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
6.5
DUT_ VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
12
______________________________________________________________________________________
Quad Low-Power, 500Mbps ATE Driver/Comparator
Typical Operating Characteristics (continued)
MAX9965/MAX9966
INPUT CURRENT vs. INPUT VOLTAGE, CPHV_
MAX9965 toc37
INPUT CURRENT vs. INPUT VOLTAGE, CPLV_
MAX9965 toc38
SUPPLY CURRENT ICC vs. VCC
170 155 140 125 ICC (mA) 110 95 80 65 50 35 C A B
MAX9965 toc39
600 CPLV_ = -2.2V
-500
185
CPHV_ CURRENT (nA)
CPLV_ CURRENT (nA)
500
-600
-700
400
-800
300 -900 CPHV_ = 7.2V -1000 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 CPHV_ VOLTAGE (V) CPLV_ VOLTAGE (V)
200
20 9.50 9.75 10.00 10.25 10.50 VCC (V) A: DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0, CHV_ = CLV_ = 0, CPHV_ = 7.2V, CPLV_ = -2.2V B: SAME AS A EXCEPT DUT_ = HIGH-Z C: SAME AS B EXCEPT DUT_ = LOW LEAK
SUPPLY CURRENT IEE vs. VEE
MAX9965 toc40
ICC vs. TEMPERATURE
MAX9965 toc41
IEE vs. TEMPERATURE
-329.2 SUPPLY CURRENT (mA) -329.4 -329.6 -329.8 -330.0 -330.2 -330.4 60 70 80 90 100 110 TEMPERATURE (C) DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0, CHV_ = CLV_ = 0, CPHV_ = 7.2V, CPLV = -2.2V, VCC = 9.75V, VEE = -5.25V
MAX9965 toc42
-220 -240 -260 -280 IEE (mA) -300 -320 -340 -360 -380 -400 B A C
168.0 167.5 SUPPLY CURRENT (mA) 167.0 166.5 166.0 165.5 165.0 164.5 164.0 163.5
-329.0
-6.50 -6.25 -6.00 -5.75 -5.50 -5.25 -5.00 -4.75 -4.50 VEE (V) A: DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0, CHV_ = CLV_ = 0, CPHV_ = 7.2V, CPLV_ = -2.2V B: SAME AS A EXCEPT DUT_ = HIGH-Z C: SAME AS B EXCEPT DUT_ = LOW LEAK
60
70
80
90
100
110
TEMPERATURE (C) DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0, CHV_ = CLV_ = 0, CPHV_ = 7.2V, CPLV = -2.2V, VCC = 9.75V, VEE = -5.25V
______________________________________________________________________________________
13
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
Pin Description
PIN MAX9965 MAX9966 NAME FUNCTION Channel 3/4 Collector Voltage Input. For open-collector outputs, this is the pullup voltage for the internal termination resistors. For open-emitter outputs, this is the collector voltage of the output transistors. Not internally connected on open-collector versions without internal termination resistors. VCCO34 services both channel 3 and channel 4. Channel 4 Multiplexer Control Inputs. Differential controls DATA4 and NDATA4 select driver 4's input from DHV4 or DLV4. Drive DATA4 above NDATA4 to select DHV4. Drive NDATA4 above DATA4 to select DLV4. Channel 4 Multiplexer Control Inputs. Differential controls RCV4 and NRCV4 place channel 4 into receive mode. Drive RCV4 above NRCV4 to place channel 4 into receive mode. Drive NRCV4 above RCV4 to place channel 4 into drive mode. Channel 3 Multiplexer Control Inputs. Differential controls DATA3 and NDATA3 select driver 3's input from DHV3 or DLV3. Drive DATA3 above NDATA3 to select DHV3. Drive NDATA3 above DATA3 to select DLV3. Channel 3 Multiplexer Control Inputs. Differential controls RCV3 and NRCV3 place channel 3 into receive mode. Drive RCV3 above NRCV3 to place channel 3 into receive mode. Drive NRCV3 above RCV3 to place channel 3 into drive mode. Negative Power-Supply Input
1
25
VCCO34
2 3 4 5 6 7 8 9
24 23 22 21 20 19 18 17
DATA4 NDATA4 RCV4 NRCV4 DATA3 NDATA3 RCV3 NRCV3 VEE
10, 27, 54, 55, 16, 27, 54, 55, 60, 61, 65, 66, 60, 61, 65, 66, 71, 72, 99 71, 72, 99 11, 28, 51, 56, 15, 28, 51, 56, 62, 64, 70, 75, 62, 64, 70, 75, 98 98 12 13 14 15 14 13 12 11
GND
Ground Connection Reset Input. Asynchronous reset input for the serial register. RST is active low and asserts low-leakage mode. At power-up, hold RST low until VCC and VEE have stabilized. Chip Select Input. Serial port activation input. CS is active low. Serial Clock Input. Clock for serial port. Data Input. Serial port data input. Positive Power-Supply Input Channel 2 Multiplexer Control Inputs. Differential controls RCV2 and NRCV2 place channel 2 into receive mode. Drive RCV2 above NRCV2 to place channel 2 into receive mode. Drive NRCV2 above RCV2 to place channel 2 into drive mode. Channel 2 Multiplexer Control Inputs. Differential controls DATA2 and NDATA2 select driver 2's input from DHV2 or DLV2. Drive DATA2 above NDATA2 to select DHV2. Drive NDATA2 above DATA2 to select DLV2. Channel 1 Multiplexer Control Inputs. Differential controls RCV1 and NRCV1 place channel 1 into receive mode. Drive RCV1 above NRCV1 to place channel 1 into receive mode. Drive NRCV1 above RCV1 to place channel 1 into drive mode. Channel 1 Multiplexer Control Inputs. Differential controls DATA1 and NDATA1 select driver 1's input from DHV1 or DLV1. Drive DATA1 above NDATA1 to select DHV1. Drive NDATA1 above DATA1 to select DLV1.
RST CS SCLK DIN VCC NRCV2 RCV2 NDATA2 DATA2 NRCV1 RCV1 NDATA1 DATA1
16, 26, 52, 58, 10, 26, 52, 58, 68, 74, 100 68, 74, 100 17 18 19 20 21 22 23 24 9 8 7 6 5 4 3 2
14
______________________________________________________________________________________
Quad Low-Power, 500Mbps ATE Driver/Comparator
Pin Description (continued)
PIN MAX9965 MAX9966 NAME FUNCTION Channel 1/2 Collector Voltage Input. For open-collector outputs, this is the pullup voltage for the internal termination resistors. For open-emitter outputs, this is the collector voltage of the output transistors. Not internally connected on open-collector versions without internal termination resistors. VCCO12 services both channel 1 and channel 2. Channel 2 Low Comparator Output. Differential output of channel 2 low comparator. Channel 2 High Comparator Output. Differential output of channel 2 high comparator. Channel 1 Low Comparator Output. Differential output of channel 1 low comparator. Channel 1 High Comparator Output. Differential output of channel 1 high comparator. Channel 2 High Clamp Reference Input Channel 2 Low Clamp Reference Input Channel 2 Driver High Reference Input Channel 2 Driver Low Reference Input Channel 2 Driver Termination Reference Input Channel 2 High Comparator Reference Input Channel 2 Low Comparator Reference Input Channel 1 High Clamp Reference Input Channel 1 Low Clamp Reference Input Channel 1 Driver High Reference Input Channel 1 Driver Low Reference Input Channel 1 Driver Termination Reference Input Channel 1 High Comparator Reference Input Channel 1 Low Comparator Reference Input Channel 1 Device Under Test Input/Output. Combined I/O for driver, comparator, and clamp. No Connect. Leave open. Channel 2 Device Under Test Input/Output. Combined I/O for driver, comparator, and clamp. Temperature Monitor Output
MAX9965/MAX9966
25
1
VCCO12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 53 57, 69 59 63
97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 57, 69 67 63
NCL2 CL2 NCH2 CH2 NCL1 CL1 NCH1 CH1 CPHV2 CPLV2 DHV2 DLV2 DTV2 CHV2 CLV2 CPHV1 CPLV1 DHV1 DLV1 DTV1 CHV1 CLV1 DUT1 N.C. DUT2 TEMP
______________________________________________________________________________________
15
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
Pin Description (continued)
PIN MAX9965 67 73 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 MAX9966 59 53 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NAME DUT3 DUT4 CLV4 CHV4 DTV4 DLV4 DHV4 CPLV4 CPHV4 CLV3 CHV3 DTV3 DLV3 DHV3 CPLV3 CPHV3 CH4 NCH4 CL4 NCL4 CH3 NCH3 CL3 NCL3 FUNCTION Channel 3 Device Under Test Input/Output. Combined I/O for driver, comparator, and clamp. Channel 4 Device Under Test Input/Output. Combined I/O for driver, comparator, and clamp. Channel 4 Low Comparator Reference Input Channel 4 High Comparator Reference Input Channel 4 Driver Termination Reference Input Channel 4 Driver Low Reference Input Channel 4 Driver High Reference Input Channel 4 Low Clamp Reference Input Channel 4 High Clamp Reference Input Channel 3 Low Comparator Reference Input Channel 3 High Comparator Reference Input Channel 3 Driver Termination Reference Input Channel 3 Driver Low Reference Input Channel 3 Driver High Reference Input Channel 3 Low Clamp Reference Input Channel 3 High Clamp Reference Input Channel 4 High Comparator Output. Differential outputs of channel 4 high comparator. Channel 4 Low Comparator Output. Differential outputs of channel 4 low comparator. Channel 3 High Comparator Output. Differential outputs of channel 3 high comparator. Channel 3 Low Comparator Output. Differential outputs of channel 3 low comparator.
16
______________________________________________________________________________________
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
ONE OF FOUR IDENTICAL CHANNELS SHOWN DLV_ DHV_ DTV_ SLEWRATE CONTROL
MULTIPLEXER
BUFFER 50 DUT_
SC0 OPTIONAL 100
SC1
LLEAK
MAX9965 MAX9966
DATA_ NDATA_ RCV_ NRCV_ OPTIONAL 100 CPHV_ CPLV_ CHV_
HIGH-Z
TMSEL
CLAMPS
CH_ NCH_
2 4 x 48 OPTIONAL 2 COMPARATORS
VCCO_ _
CL_ NCL_ CLV_ TEMP CS SCLK DIN RST SERIAL INTERFACE CH_ MODE BITS SERIAL INTERFACE IS COMMON TO ALL FOUR CHANNELS. MODE BITS ARE INDEPENTENTLY LLEAK LATCHED FOR EACH CHANNEL. SC0 SC1 TMSEL GND VCC VEE
Figure 1. MAX9965/MAX9966 Block Diagram ______________________________________________________________________________________ 17
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
Detailed Description
The MAX9965/MAX9966 four-channel, high-speed pin electronics driver and comparator ICs for automatic test equipment include, for each channel, a three-level pin driver, a dual comparator, and variable clamps (Figure 1). The driver features a -1.5V to +6.5V operating range and high-speed operation, including high-Z and active termination (3rd-level drive) modes, which is highly linear even at low-voltage swings. The devices are similar to the MAX9963/MAX9964 but with a comparator that provides even lower timing dispersion, due to changes in input slew rate and pulse width. The clamps provide damping of high-speed DUT_ waveforms when the device is configured as a high-impedance receiver. Each of the four channels has high-speed, differential inputs compatible with ECL, LVPECL, LVDS, and GTL signal levels, with optional 100 differential input terminations. Optional internal resistors at DATA_ and RCV_ provide differential termination of LVDS inputs. Optional internal resistors at CH_ and CL_ provide the pullup voltage and source termination for open-collector comparator outputs. These options significantly reduce the discrete component count on the circuit board. The MAX9965/MAX9966 are available in two grade options. An A-grade version provides tighter matching of gain and offset of the drivers, and tighter offset matching of the comparators. This allows reference levels to be shared across multiple channels in cost-sensitive systems. A B-grade version provides lower cost for system designs that incorporate independent reference levels for each channel.
HIGHSPEED INPUTS REFERENCE INPUTS 0 0 1 1 SLEW RATE BUFFER 0 0 1 50 DUT_
The MAX9965/MAX9966 modal operation is programmed through a 3-wire, low-voltage, CMOS-compatible serial interface.
Output Driver
The driver input is a high-speed multiplexer that selects one of three voltage inputs: DHV_, DLV_, or DTV_. This switching is controlled by high-speed inputs DATA_ and RCV_, and mode control bit TMSEL. A slew-rate circuit controls the slew rate of the buffer input. One of four possible slew rates can be selected (Table 1); the speed of the internal multiplexer sets the 100% driver slew rate (see the Driver Large-Signal Response in the Typical Operating Characteristics). DUT_ can be toggled at high speed between the buffer output and high-impedance mode, or it can be placed in low-leakage mode (Figure 2, Table 2). In high-impedance mode, the clamps are connected. This switching is controlled by the high-speed input RCV_ and the mode control bits TMSEL and LLEAK. In high-impedance mode, the bias current at DUT_ is less than 2A over the 0 to 3V range, while the node maintains its ability to track high-speed signals. In low-leakage mode, the bias current at DUT_ is further reduced to less than 15nA. See the Low-Leakage Mode section for more detailed information. The nominal driver output resistance is 50. Contact the factory for different values within the 40 to 50 range.
DLV_ DHV_ DTV_ DATA_ RCV_
HIGH-Z
CPHV_ CLAMPS TMSEL LLEAK CPLV_ 4 MODE COMPARATORS
SC0
Figure 2. Simplified Driver Channel 18 ______________________________________________________________________________________
SC1
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
Table 1. Slew Rate Logic
SC1 0 0 1 1 SC0 0 1 0 1 DRIVER SLEW RATE (%) 100 75 50 25
Table 3. Comparator Logic
DUT_ > CHV_ 0 0 1 1 DUT_ > CLV_ 0 1 0 1 CH_ 0 0 1 1 CL_ 0 1 0 1
Table 2. Driver Logic
EXTERNAL INTERNAL CONTROL CONNECTIONS REGISTER DATA_ 1 0 X X X RCV_ 0 0 1 1 X TMSEL X X 1 0 X LLEAK 0 0 0 0 1
DUT_ 8mA CH_
DRIVER OUTPUT
CHV_
Drive to DHV_ Drive to DLV_ Drive to DTV_ (term mode) High-impedance mode (high-z) Low-leakage mode
VEE
NCH_
2 4 x 48 OPTIONAL 2 VCCO_ _
Clamps
A pair of voltage clamps (high and low) can be configured to limit the voltage at DUT_, and to suppress reflections when the channel is configured as a highimpedance receiver. The clamps behave as diodes connected to the outputs of high-current buffers. Internal circuitry compensates for the diode drop at 1mA clamp current. Set the clamp voltages using external connections CPHV_ and CPLV_. The clamps are enabled only when the driver is in the high-impedance mode (Figure 2). For transient suppression, set the clamp voltages to approximately the minimum and maximum expected DUT_ voltage range and must be empirically determined. The optimal clamp voltages are application specific. If clamping is not desired, set the clamp voltages at least 0.7V outside the expected DUT_ voltage range; overvoltage protection remains active without loading DUT_.
8mA
CL_
CLV_
VEE
NCL_
Figure 3. Open-Collector Comparator Outputs
CH_ 106 DUT_
CHV_ 106 NCH_ VCCO_ _ CL_ 106
Comparators
The MAX9965/MAX9966 have two independent highspeed comparators for each channel. Each comparator has one input connected internally to DUT_ and the other input connected to either CHV_ or CLV_ (Figure 1). Comparator outputs are a logical result of the input conditions, as indicated in Table 3. The MAX9965/MAX9966s' comparators feature BJT inputs for improved comparator dispersion in contrast to the MAX9963/MAX9964s' JFET comparators.
CLV_ 106 NCL_
Figure 4. Open-Emitter Comparator Outputs ______________________________________________________________________________________ 19
Quad Low-Power, 500Mbps ATE Driver/Comparator
Three configurations are available for the comparator differential outputs to ease interfacing with a wide variety of logic families. An open-collector configuration switches an 8mA current source between two outputs. This configuration is available with and without internal termination resistors connected to VCCO_ (Figure 3). For external termination, leave VCCO_ unconnected and add the required external resistors. These resistors are typically 50 to the pullup voltage at the receiving end of the output trace. Alternate configurations may be used, provided that the Absolute Maximum Ratings are not exceeded. For internal termination, connect VCCO_ to the desired VOH voltage. Each output provides a nominal 400mVP-P swing and 50 source termination. An open-emitter configuration is also available (Figure 4). Connect an external collector voltage to VCCO_ and add external pulldown resistors. These are typically 50 to VCCO_ -2V at the receiving end of the output trace. Alternate configurations may be used, provided that the Absolute Maximum Ratings are not exceeded.
MAX9965/MAX9966
Table 4. Shift Register Functions
BIT D7 NAME 1E FUNCTION Channel 1 Write Enable. Set to 1 to update the control byte for channel 1. Set to zero to make no change to channel 1. Channel 2 Write Enable. Set to 1 to update the control byte for channel 2. Set to zero to make no change to channel 2. Channel 3 Write Enable. Set to 1 to update the control byte for channel 3. Set to zero to make no change to channel 3. Channel 4 Write Enable. Set to 1 to update the control byte for channel 4. Set to zero to make no change to channel 4. Low-Leakage Select. Set to 1 to put driver and clamps into low-leakage mode. Set to zero for normal operation. Driver Slew Rate Select. SC1 and SC0 set the driver slew rate. See Table 1. Driver Termination Select. Set to 1 to force the driver output to the DTV_ voltage (term mode) when RCV_ = 1. Set to zero to place the driver into a high impedance state (high-z mode) when RCV_ = 1. See Table 2.
D6
2E
D5
3E
D4
4E
D3 D2 D1
LLEAK SC1 SC0
Low-Leakage Mode, LLEAK
Asserting LLEAK through the serial port or with RST places the MAX9965/MAX9966 into a very-low-leakage state in which the DUT_ input current is less than 15nA over the 0 to 3V range. In this mode, the driver, comparators, and clamps are disabled. This mode is convenient for making IDDQ and PMU measurements without the need for an output disconnect relay. LLEAK is programmed independently for each channel. If DUT_ is driven with a high-speed signal while LLEAK is asserted, leakage current momentarily increases beyond the limits specified for normal operation. The Low-Leakage Recovery specification in the Electrical Characteristics table indicates device behavior under this condition.
tCH SCLK tCSS0 tCL
D0
TMSEL
tCSS1 tCSH1
CS tCSWH
tDH tDS DIN D7 D6 D5 D4 D3 D2 D1 D0
Figure 5. Serial Interface Timing 20 ______________________________________________________________________________________
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
SCLK DIN CS ENABLE 0 1 2 SHIFT REGISTER 3 4 5 6 7
F/F 3 7 D ENABLE RST Q 3 6 D
F/F Q 3 5 D
F/F Q 3 4 D
F/F Q
ENABLE RST
ENABLE RST
ENABLE RST
RST F/F 0-2 7 D ENABLE Q 3 1 0-2 6 D ENABLE F/F Q 3 1 0-2 5 D ENABLE F/F Q 3 1 0-2 4 D ENABLE F/F Q 3 1
TMSEL, SC0, SC1 LLEAK MODE BITS CHANNEL 1
TMSEL, SC0, SC1 LLEAK MODE BITS CHANNEL 2
TMSEL, SC0, SC1 LLEAK MODE BITS CHANNEL 3
TMSEL, SC0, SC1 LLEAK MODE BITS CHANNEL 4
Figure 6. Serial Interface
Temperature Monitor
Each device supplies a single temperature output signal, TEMP, that asserts a nominal output voltage of 3.43V at a die temperature of +70C (343K). The output voltage increases proportionately with temperature at a rate of 10mV/C. The temperature sensor output impedance is 15k (typ).
and RCV_, manage the features of each channel, as shown in Tables 1 and 2. RST sets LLEAK = 1 for all channels, forcing them into low-leakage mode. All other bits are unaffected. At power-up, hold RST low until VCC and VEE have stabilized.
Heat Removal
These devices require heat removal under normal circumstances through the exposed pad, either by soldering to circuit board copper (MAX9966) or by use of an external heat sink (MAX9965). The exposed pad is electrically at VEE potential for both package types, and must be either connected to VEE or isolated.
Serial Interface and Device Control
A CMOS-compatible serial interface controls the MAX9965/MAX9966 modes (Figure 6). Control data flow into a bit shift register (MSB first) and are latched when CS is taken high, as shown in the serial timing diagram, Figure 5. Data from the shift register are then loaded into any or all of a group of four quad latches, determined by bits D4 through D7, as indicated in Figure 6 and Table 4. The quad latches contain the four mode bits for each channel of the quad pin driver. The mode bits, in conjunction with external inputs DATA_
Chip Information
TRANSISTOR COUNT: 7293 PROCESS: Bipolar
______________________________________________________________________________________
21
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
Selector Guide
PART MAX9965ADCCQ* MAX9965AKCCQ* MAX9965AGCCQ* MAX9965AHCCQ* MAX9965AJCCQ* MAX9965BDCCQ* MAX9965BKCCQ* MAX9965BGCCQ MAX9965BHCCQ* MAX9965BJCCQ MAX9966ADCCQ* MAX9966AKCCQ* MAX9966AGCCQ* MAX9966AHCCQ* MAX9966AJCCQ* MAX9966BDCCQ* MAX9966BKCCQ* MAX9966BGCCQ MAX9966BHCCQ* MAX9966BJCCQ* ACCURACY GRADE A A A A A B B B B B A A A A A B B B B B COMPARATOR OUTPUT TYPE Open collector Open collector Open collector Open emitter Open emitter Open collector Open collector Open collector Open emitter Open emitter Open collector Open collector Open collector Open emitter Open emitter Open collector Open collector Open collector Open emitter Open emitter COMPARATOR OUTPUT TERMINATION None None 50 to VCCO__ None None None None 50 to VCCO__ None None None None 50 to VCCO__ None None None None 50 to VCCO__ None None HIGH-SPEED DIGITAL INPUT TERMINATION None 100 LVDS 100 LVDS None 100 LVDS None 100 LVDS 100 LVDS None 100 LVDS None 100 LVDS 100 LVDS None 100 LVDS None 100 LVDS 100 LVDS None 100 LVDS HEAT EXTRACTION Top Top Top Top Top Top Top Top Top Top Bottom Bottom Bottom Bottom Bottom Bottom Bottom Bottom Bottom Bottom PINPACKAGE 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EP 100 TQFP-EP 100 TQFP-EP 100 TQFP-EP 100 TQFP-EP 100 TQFP-EP 100 TQFP-EP 100 TQFP-EP 100 TQFP-EP 100 TQFP-EP
*Future product--contact factory for availability.
22
______________________________________________________________________________________
Quad Low-Power, 500Mbps ATE Driver/Comparator
MAX9965 Pin Configuration
CPHV3 CPHV4 TOP VIEW NCH3 NCH4 NCL3 NCL4 GND CH3 CH4 CL3 CL4 VCC VEE CPLV3 CPLV4 DHV3 CHV3 DHV4 CHV4
MAX9965/MAX9966
DTV3
DTV4
DLV3
CLV3
DLV4
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VCCO34 1 DATA4 2 NDATA4 3 RCV4 4 NRCV4 5 DATA3 6 NDATA3 7 RCV3 8 NRCV3 9 VEE 10 GND 11 RST 12 CS 13 SCLK 14 DIN 15 VCC 16 NRCV2 17 RCV2 18 NDATA2 19 DATA2 20 NRCV1 21 RCV1 22 NDATA1 23 DATA1 24 VCCO12 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NCL1 CL1 DTV2 NCH1 CPHV2 DHV2 CHV2 CPHV1 DHV1 DTV1 CH1 CPLV2 CPLV1 CHV1 DLV2 CLV2 DLV1 NCL2 NCH2 CLV1 VEE CL2 VCC GND CH2 75 GND 74 VCC 73 DUT4
CLV4 72 VEE 71 VEE 70 GND 69 N.C. 68 VCC 67 DUT3 66 VEE 65 VEE 64 GND 63 TEMP 62 GND 61 VEE 60 VEE 59 DUT2 58 VCC 57 N.C. 56 GND 55 VEE 54 VEE 53 DUT1 52 VCC 51 GND
MAX9965
TQFP-EPR
______________________________________________________________________________________
23
Quad Low-Power, 500Mbps ATE Driver/Comparator MAX9965/MAX9966
MAX9966 Pin Configuration
CPHV2 CPHV1 TOP VIEW NCH2 NCH1 NCL2 NCL1 GND CH2 CH1 CL2 CL1 VCC VEE CPLV2 CPLV1 DHV2 CHV2 DHV1 CHV1
DTV2
DTV1
DLV2
CLV2
DLV1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VCCO12 1 DATA1 2 NDATA1 3 RCV1 4 NRCV1 5 DATA2 6 NDATA2 7 RCV2 8 NRCV2 9 VCC 10 DIN 11 SCLK 12 CS 13 RST 14 GND 15 VEE 16 NRCV3 17 RCV3 18 NDATA3 19 DATA3 20 NRCV4 21 RCV4 22 NDATA4 23 DATA4 24 VCCO34 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NCL4 CL4 DTV3 NCH4 CPHV3 DHV3 CHV3 CPHV4 DHV4 DTV4 CH4 CPLV3 CPLV4 CHV4 DLV3 CLV3 DLV4 NCL3 NCH3 CLV4 VEE CL3 VCC GND CH3 75 GND 74 VCC 73 DUT1
CLV1 72 VEE 71 VEE 70 GND 69 N.C. 68 VCC 67 DUT2 66 VEE 65 VEE 64 GND 63 TEMP 62 GND 61 VEE 60 VEE 59 DUT3 58 VCC 57 N.C. 56 GND 55 VEE 54 VEE 53 DUT4 52 VCC 51 GND
MAX9966
TQFP-EP
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX9965-MAX9966

	To Download MAX9965-MAX9966 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .