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FUJITSU SEMICONDUCTOR DATA SHEET
Revision 0.1
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89201 Series
MB89201/N201/V201
DESCRIPTION
The MB89201 series is a line of single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such, timers, a serial interface, an A/D converter and an external interrupt.
FEATURES
* * * * * * * * * * * * * * * MB89600 Series CPU core Maximum memory space : 64 Kbytes Minimum execution time : 0.32 s/12.5 MHz Interrupt processing time : 2.88 s/12.5 MHz I/O ports : max. 27channels 21-bit timebase timer 8-bit PWM timer 8/16-bit capture timer/counter 10-bit A/D converter : 8 channels UART 8-bit serial I/O External interrupt 1 : 3 channels External interrupt 2 : 8 channels Wild Register : 2 bytes Multi-time programmable flash (MTP flash) Read protection (Continued)
PACKAGES
32-pin plastic SHDIP 64-pin plastic SHDIP
(DIP-32P-M06)
(DIP-64P-M01)
MB89201 Series
(Continued) * Low-power consumption modes ( sleep mode, and stop mode) * SHDIP-32 package * CMOS Technology
PRODUCT LINEUP
Part number Parameter
MB89201
MB89N201 Multi-time programmable flash product (read protection) 16 K x 8 bits (internal flash) 512 x 8 bits
MB89V201 Evaluation product (for development) 32K x 8-bit (external EPROM)
Classification
Mask ROM product 16 K x 8 bits (internal mask ROM)
ROM size RAM size
CPU functions
Number of instructions : Instruction bit length : Instruction length : Data bit length : Minimum execution time : Interrupt processing time :
136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.32 s to 5.1 s (12.5 MHz) 2.88 s to 46.1 s (12.5 MHz)
Ports 21-bit time base timer Watching timer
General-purpose I/O ports (CMOS) : 27 (also serve as peripherals ) (5 ports are also an N-ch open-drain type.) 21-bit Interrupt cycle : 0.66 ms, 2.64 ms, 21 ms, or 335.5 ms with 12.5-MHz main clock Reset generation cycle : 335.5 ms minimum with 12.5-MHz main clock 8-bit interval timer operation (square output capable, operating clock cycle : 0.32 s , 2.56 s, 5.1 s, 20.5 s) 8-bit resolution PWM operation (conversion cycle : 81.9 s to 21.47 s : in the selection of internal shift clock of 8/16-bit capture timer) Count clock selectable between 8-bit and 16-bit timer/counter outputs 8-bit capture timer/counter x 1 channel + 8-bit timer or 16-bit capture timer/counter x 1 channel Capable of event count operation and square wave output using external clock input with 8-bit timer 0 or 16-bit counter Transfer data length : 6/7/8 bits 8 bits LSB first/MSB first selectable One clock selectable from four operation clocks (one external shift clock, three internal shift clocks : 0.8 s, 6.4 s, 25.6 s) Output frequency : Pulse width and cycle selectable 3 channels (Interrupt vector, request flag, request output enabled) Edge selectable (Rising edge, falling edge, or both edges) Also available for resetting stop/sleep mode (Edge detectable even in stop mode) 1 channel with 8 inputs (Independent L-level interrupt and input enable) Also available for resetting stop/sleep mode (Level detectable even in stop mode) (Continued)
8-bit PWM timer
8/16-bit capture, timer/counter UART 8-bit Serial I/O 12-bit PPG timer External interrupt 1 (wake-up function) External interrupt 2 (wake-up function)
2
MB89201 Series
(Continued)
Part number Parameter
MB89201
MB89N201
MB89V201
10-bit A/D converter Wild Register Standby mode
10-bit precision x 8 channels A/D conversion function (Conversion time : 12.16 s/12.5 MHz) Continuous activation by 8/16-bit timer/counter output or time-base timer counter 8-bit x 2 Sleep mode, and Stop mode
Powr-on reset : Powr-on reset : Powr-on reset : Oscillation settling time Oscillation settling time*1 Voltage regulator and os(21.0 ms/12.5 MHz) cillation settling time External reset : External reset : (31.5 ms/12.5 MHz) Overhead time from a few s Oscillation settling time External reset : reset to the first in- Software reset : (21.0 ms/12.5 MHz) Oscillation settling time struction execution a few s Software reset : (21.0 ms/12.5 MHz) a few s Software reset : a few s Power supply Voltage*2 2.2 V to 5.5 V 3.5 V to 5.5 V 2.7 V to 5.5 V
*1 : Check section " MASK OPTIONS" *2 : The minimum operating voltage varies with the operating frequency, the function, and the connected ICE.
PACKAGE AND CORRESPONDING PRODUCTS
Package DIP-32P-M06 DIP-64P-M01 : Available x x : Not available x MB89201 MB89N201 MB89V201 x *
* : Adapter for 64-pin to 32-pin conversion (manufactured by) Part number : Inquiry:
DIFFERENCES AMONG PRODUCTS
1. 2. 3. Memory Size
Before evaluating using the evaluation product, verify its differences from the product that will actually be used.
Current Consumption
In the case of the MB89V201, add the current consumed by the EPROM which is connected to the adapter socket.
Mask Options
Functions that can be selected as options and how to designate these options vary by the product. Before using options check section " MASK OPTIONS".
3
MB89201 Series
PIN ASSIGNMENT
(TOP VIEW)
P04/INT24 P05/INT25 P06/INT26 P07/INT27 P60 P61 P62/RST X0 X1 VSS P37/BZ/PPG P36/INT12 P35/INT11 P34/TO/INT10 P33/EC C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC P03/INT23/AN7 P02/INT22/AN6 P01/INT21/AN5 P00/INT20/AN4 P43/AN3* P42/AN2* P41/AN1* P40/AN0* P72* P71* P70* P50/PWM P30/UCK/SCK P31/UO/SO P32/UI/SI
* : Heavy-current drive type
(DIP-32P-M06) (Continued)
4
MB89201 Series
(Continued) (TOP VIEW)
EVDD EVSS N.C. N.C. A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O8 O7 O6 O5 O4 O3 O2 O1 CE OE EVDD EVSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VCC P40/AN0* P41/AN1* P42/AN2* P43/AN3* P00/INT20/AN4 P01/INT21/AN5 P02/INT22/AN6 P03/INT23/AN7 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P37/BZ/PPG P36/INT12 P35/INT11 P34/TO/INT10 P33/EC P32/UI/SI P31/UO/SO P30/UCK/SCK P50/PWM P70* P71* P72* P60 P61 P62/RST SEL X0 X1 VSS
* : Heavy-current drive type
(DIP-64P-M01)
N.C. : Internally connected. Do not use.
5
MB89201 Series
PIN DESCRIPTION
Pin No.
SHDIP32*1 SHDIP64*2
Pin name X0 X1 P60 P61
Circuit type A H H
Function
Pins for connecting the crystal for the main clock. To use an external clock, input the signal to X0 and leave X1 open. General-purpose CMOS input port. General-purpose CMOS input port Reset I/O pin / General-purpose CMOS I/O port (selectable by metal option for MB89201/N201; selectable by SEL input for MB89V201). This pin serves as an N-channel open-drain output with pull-up resistor and a input as well. The reset is a hysteresis input. If the pin is selected to be reset I/O pin, then it outputs the "L" signal in response to an internal reset request. Also, it initializes the internal circuit upon input of the "L" signal. MB89V201 P62/RST selection input. If SEL is pullup, then P62/RST pin act as RST function; If SEL is pulldown, then P62/RST pin act as P62 function; General-purpose CMOS I/O ports. These pins also serve as an input (wake-up input) of external interrupt 2 or as an A/D converter analog input. The input of external interrupt 2 is a hysteresis input. General-purpose CMOS I/O ports. These pins also serve as an input (wake-up input) of external interrupt 2. The input of external interrupt 2 is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the clock I/O pin for the UART or 8-bit serial I/O. The resource is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the data output pin for the UART or 8-bit serial I/O. General-purpose CMOS I/O ports. This pin also serves as the data input pin for the UART or 8-bit serial I/O. The resource is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the external clock input pin for the 8/16-bit capture timer/counter. The resource is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the output pin for the 8/16-bit capture timer/ counter or as the input pin for external interrupt 1. The resource is a hysteresis input. General-purpose CMOS I/O ports. These pins also serve as the input pin for external interrupt 1. The resource is a hysteresis input.
8 9 5 6
35 34 39 38
7
37
P62/RST
C
36
SEL
P00/INT20/AN4 28 to 31 59 to 56 to P03/INT23/AN7 P04/INT24 to P07/INT27 P30/UCK/SCK
G
1 to 4
55 to 52
D
19
44
B
18
45
P31/UO/SO
E
17
46
P32/UI/SI
B
15
47
P33/EC
B
14
48
P34/TO/INT10
B
13, 12
49, 50
P35/INT11, P36/INT12
B
(Continued) *1 : DIP-32P-M06 *2 : DIP-64P-M01
6
MB89201 Series
(Continued) Pin No.
SHDIP*1 SHDIP*2
Pin name
Circuit type E E F E E
Function
General-purpose CMOS I/O ports. This pin also serves as the buzzer output pin or the 12-bit programmable pulse generator output. General-purpose CMOS I/O ports. This pin also serves as the 8-bit PWM output pin. General-purpose CMOS I/O ports. These pins can also be used as N-channel open-drain ports. These pins also serve as A/D converter analog input pins. Power supply pin Power (GND) pin General-purpose CMOS I/O ports. General-purpose CMOS I/O ports. MB89N201: Capacitance pin for regulating the power supply. Connect an external ceramic capacitor of about 0.1 F. MB89201: This pin is not internally connected. It is unnecessary to connect a capacitor.
11 20 24 to 27 32 10 21 22 to 23
51 43 63 to 60 64 33 42 41 to 40
P37/BZ/PPG P50/PWM P40/AN0 to P43/AN3 VCC VSS P70 P71 to P72
16
C
*1 : DIP-32P-M06 *2 : DIP-64P-M01
7
MB89201 Series
EXTERNAL EPROM PIN DESCRIPTION (MB89V201 only)
Pin No. 1, 31 2, 32 5 to 20 21 to 28 29 30 3, 4 Pin name EVDD EVSS A15 to A0 O8 to O1 CE OE N.C. I/O O O O I O O Function EPROM power supply pin EPROM power supply (GND) pin Address output pins Data input pins ROM chip enable pin Outputs "H" during standby. ROM output enable pin Outputs "L" at all times. Internally connected pins Be sure to leave them open.
8
MB89201 Series
I/O CIRCUIT TYPE
Type Circuit Remarks * At an oscillation feedback resistance of approximately 500 k
X1
A
X0
Standby control signal
P-ch
* CMOS output * Hysteresis input * Pull-up resistor optional
P-ch
B
N-ch
Input enable
Port / Resource
P-ch
C
Input enable Input enable
N-ch Port Reset
* At an output pull-up resister (P-ch) of approximately 50 k/5.0 V * N-ch open-drain output available * CMOS input * Hysteresis input (Reset input)
P-ch
* * * *
P-ch
CMOS output CMOS input Hysteresis input (Resource input) Pull-up resistor optional
D
N-ch Input enable Input enable Port Resource
(Continued)
9
MB89201 Series
(Continued) Type
Circuit * * * *
P-ch
Remarks CMOS output CMOS input Pull-up resistor optional P70-P72 are heavy-current drive type
P-ch
E
N-ch
Input enable
Port
P-ch
open-drain control
F
Input enable
N-ch Analog input Port A/D enable
* * * * *
CMOS output CMOS input Analog input N-ch open-drain output available P40-P43 are heavy-current drive type
P-ch
* * * *
P-ch
CMOS output CMOS input Hysteresis input (Resource input) Analog input
G
N-ch Input enable Input enable Analog input A/D enable Port Resource
* CMOS input
H
Input enable Port
10
MB89201 Series
HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in section " ELECTRICAL CHARACTERISTICS" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2.
Treatment of Unused Input Pins
Leaving unused input terminals open may lead to permanent damage due to malfunction and latchup; pull up or pull down the terminals through the resistors of 2 k or more. Make the unused I/O terminal in a state of output and leave it open and if it is in an input state, handle it with the same procedure as the input terminals.
3.
Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
4.
Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
5.
Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode.
6.
About the Wild Register Function
No wild register can be debugged on the MB89V201. For the operation check, test the MB89N201 installed on a target system.
7.
Program Execution in RAM
When the MB89V201 is used, no program can be executed in RAM.
8.
Note to Noise in the External Reset Pin (RST)
If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST).
9.
Cautions for the product that does not contain External Reset Pin (RST)
For the product that select P62 instead of RST pin by mask option, the only way to initialize the device is by power on reset. If the power supply rise / cutoff time does not meet the specifications, then power on reset cannot be generated, and the device become unusable.
11
MB89201 Series
PROGRAMMING AND ERASE FLASH MEMORY ON THE MB89N201
1. Flash Memory
The flash memory is located between C000H and FFFFH in the CPU memory map and incorporates a flash memory interface circuit that allows read access and program access from the CPU to be performed in the same way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the control of the CPU, providing an efficient method of updating program and data.
2.
* * * * * * *
Flash Memory Features
16 K bytex8-bit configuration Automatic programming algorithm (Embedded algorithm*) Includes an erase pause and restart function Data polling and toggle bit for detection of program/erase completion Detection of program/erase completion via CPU interrupt Compatible with JEDEC-standard commands No. of program/erase cycles : Minium 100; Maxium 1,000
* : Embedded Algorithm is a trademark of Advanced Micro Devices.
3.
Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or erase flash memory, the program must first be copied from flash memory to RAM so that programming can be performed without program access from flash memory.
4.
Flash Memory Control Status Register (FMCS)
bit 7 Address 0079H INTE R/W
RDYINT
bit 6
bit 5 WE R/W
bit 4 RDY R
bit 3
bit 2
bit 1
bit 0 Initial value 000X----B
R/W
5.
Memory Space
The memory space for the CPU access and for the parallel flash programmer access is listed below. Memory size 16 K bytes CPU address FFFFH to C000H Programmer address 3FFFH to 0000H
6.
Flash Programmer Adaptor and Recommended Flash Programmers
Part number MB89N201-PSH Package DIP-32P-M06 Adaptor Part number MB91919-607 Programmer Part number MB91919-001
Contact information : * Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770
7.
Flash Content Protection
Flash content can be read using serial programmer if the flash content protection mechanism is not activated. One predefined area of the flash (FFFCH) is assigned to be used for preventing the read access of flash content. If the protection code "01H" is written in this address (FFFCH), the flash content cannot be read by any serial programmer. Note : The program written into the flash cannot be verified once the flash protection code is written ("01H" in FFFCH). It is advised to write the flash protection code at last.
12
MB89201 Series
PROGRAMMING TO THE EPROM WITH EVALUATION DEVICE
1. 2. EPROM for Use
MBM27C256A-20TVM
Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer : Sun Hayato Co., Ltd.) listed below. Package Compatible socket part number LCC-32 ROM-32LC-28DP-S
Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403 FAX (81) -3-5396-9106
3.
Memory Space.
Normal operating mode Address 0000H I/O 0080H RAM 512 B 0280H
Not available
Corresponding adresses on the ROM programmer Address
8000H
0000H
PROM 32 KB
EPROM 32 KB
FFFFH
7FFFH
4.
Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer.
13
MB89201 Series
BLOCK DIAGRAM
X0 X1
Main clock oscillator
Timebase timer
Clock controller CMOS I/O port Port 5
Port 6
RST / P62 2 P60 to P61 3 *P70 to *P72
Reset circuit
8 bit PWM
P50 / PWM
CMOS I/O port (N-ch OD for P62) Port 7 CMOS I/O port
UART prescaler
UART
CMOS I/O port
Serial function switching
Internal bus
P04 / INT24 to P07 / INT27
4 Port 0
8
External interrupt2 (wake-up)
P30 / UCK / SCK P31 / UO / SO P32 / UI / SI
8 bit serial I/O
P00 / INT20 / AN4 4 to P03 / INT23 / AN7
4 4 Port 3 10 bit A/D Converter 8/16 bit capture timer/ counter P33 / EC P34 / TO / INT10
*P40 / AN0 4 to *P43 / AN3
Port 4
CMOS I/O port (N-ch OD)
Exernal interrupt 1
3
2
P35 / INT11 to P36 / INT12
512 byte RAM 12 bit PPG F2MC - 8 L CPU Other pins VCC, VSS, C Buzzer output 16 Kbyte ROM P37 / BZ / PPG
Wild register
CMOS I/O port
* : Heavy-current drive type
14
MB89201 Series
CPU CORE
1. Memory Space
The microcontrollers of the MB89201 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89201 series is structured as illustrated below. * Memory Space
MB89201 0000H I/O 0080H RAM 512 B 0100H Register 0100H Register 0080H RAM 512 B 0100H Register 0200H 0280H Not available 8000H C000H ROM 16 KB FFFFH FFFFH C000H FLASH 16 KB FFFFH External EPROM 32 KB 0000H I/O 0080H RAM 512 B MB89N201 0000H I/O MB89V201
0200H 0280H
0200H 0280H
Not available
Not available
15
MB89201 Series
2. Registers
The MB89201 series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided : Program counter (PC) : A 16-bit register for indicating instruction storage positions Accumulator (A) : A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX) : A 16-bit register for index modification Extra pointer (EP) : A 16-bit pointer for indicating a memory address Stack pointer (SP) : A 16-bit register for indicating a stack area Program status (PS) : A 16-bit register for storing a register pointer, a condition code
16 bit PC A T IX EP SP RP PS CCR
Initial value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR) . (See the diagram below.) * Structure of the Program Status Register
RP bit15 bit14 bit13 bit12 bit11 bit10 bit9 R4 R3 R2 R1 R0 - - H-flag I-flag IL1,0 N-flag Z-flag bit8 - bit7 H bit6 I bit5 IL1 CCR bit4 IL0 bit3 N bit2 Z bit1 V bit0 C CCR initial value X011XXXXB
PS
x : Undefined
V-flag C-flag
16
MB89201 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. * Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP "0" Generated addresses "0" "0" "0" "0" "0" "0" A9 "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3 Low OP codes b2 A2 b1 A1 b0 A0
A15 A14 A13 A12 A11 A10
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag : Set to "1" when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to "0" otherwise. This flag is for decimal adjustment instructions. I-flag : Interrupt is enabled when this flag is set to "1". Interrupt is disabled when the flag is cleared to "0". Cleared to "0" at the reset. IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 N-flag : Z-flag : V-flag : C-flag : IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt High-low High
Set to "1" if the MSB becomes to "1" as the result of an arithmetic operation. Cleared to "0" when the bit is cleared to "0". Set to "1" when an arithmetic operation results in 0. Cleared otherwise. Set to "1" if the complement on 2 overflows as a result of an arithmetic operation. Cleared to "0" if the overflow does not occur. Set to "1" when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to "0" otherwise. Set to the shift-out value in the case of a shift instruction.
17
MB89201 Series
The following general-purpose registers are provided : General-purpose registers : An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 16 banks can be used on the MB89201 series. The bank currently in use is indicated by the register bank pointer (RP) . * Register Bank Configuration
This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 16 banks
Memory area
18
MB89201 Series
I/O MAP
Address 0000H 0001H 0002H to 00006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H CNTR COMR EIC1 PDR3 DDR3 RSFR PDR4 DDR4 OUT4 PDR5 DDR5 RCR21 RCR22 RCR23 RCR24 BZCR TCCR TCR1 TCR0 TDR1 TDR0 TCPH TCPL TCR2 Port 3 data register Port 3 data direction register Reset flag register Port 4 data register Port 4 data direction register Port 4 output format register Port 5 data register Port 5 data direction register 12-bit PPG control register 1 12-bit PPG control register 2 12-bit PPG control register 3 12-bit PPG control register 4 Buzzer register Capture control register Timer 1 control register Timer 0 control register Timer 1 data register Timer 0 data register Capture data register H Capture data register L Timer output control register Prohibited area PWM control register PWM compare register External interrupt 1 Control register 1 R/W W R/W 0- 00000 0 XXXXXX X X 0000000 0 (Continued) SYCC STBC WDTC TBTC Register name PDR0 DDR0 Register description Port 0 data register Port 0 data direction register Prohibited area System clock control register Standby control register Watchdog timer control register Timebase timer control register Prohibited area R/W W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W XXXXXX X X 0000000 0 XXXX- - - - - - - XXXX - - - - 000 0 - - - - 000 0 -------X -------0 0000000 0 - - 00000 0 0- 00000 0 - - 00000 0 - - ---000 0000000 0 000- 000 0 0000000 0 XXXXXX X X XXXXXX X X XXXXXX X X XXXXXX X X ------00 R/W R/W R/W R/W 1 - - MM1 0 0 00010- - 0 - - - XXXX 00- - - 000 Read/write R/W W Initial value XXXXXX X X 0000000 0
19
MB89201 Series
Address 0025H 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH to 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH to 003FH 0040H 0041H 0042H 0043H 0044H 0045H 0046H 0047H 0048H to 005FH
Register name EIC2
Register description External interrupt 1 Control register 2 Prohibited area
Read/write R/W
Initial value - - - - 000 0
SMC SRC SSD SIDR SODR UPC
Serial mode control register Serial rate control register Serial status and data register Serial input data register Serial output data register Clock division selection register Prohibited area
R/W R/W R/W R W R/W
00000- 0 0 - - 01100 0 00100- 1X XXXXXX X X XXXXXX X X - - - - 001 0
ADC1 ADC2 ADDH ADDL ADEN
A/D converter control register 1 A/D converter control register 2 A/D converter data register H A/D converter data register L A/D enable register Prohibited area
R/W R/W R R R/W
- 000000 0 - 000000 1 - - - - - - XX XXXXXX X X 0000000 0
EIE2 EIF2
External interrupt 2 control register1 External interrupt 2 control register2 Prohibited area
R/W R/W
0000000 0 -------0
SMR SDR SSEL
Serial mode register Serial data register Serial function switching register Prohibited area
R/W R/W R/W
0000000 0 XXXXXX X X -------0
WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WREN WROR
Upper-address setting register Lower-address setting register Data setting register 0 Upper-address setting register Lower-address setting register Data setting register 1 Address comparison EN register Wild-register data test register Prohibited area
R/W R/W R/W R/W R/W R/W R/W R/W
XXXXXX X X XXXXXX X X XXXXXX X X XXXXXX X X XXXXXX X X XXXXXX X X XXXXXX 0 0 ------00 (Continued)
20
MB89201 Series
(Continued) Address 0060H 0061H 0062H 0063H 0064H 0065H 0066H to 006FH 0070H 0071H 0072H 0073H to 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH ILR1 ILR2 ILR3 ILR4 ITR FMCS PUL0 PUL3 PUL5
Register name PDR6 DDR6 PUL6 PDR7 DDR7 PUL7
Register description Port 6 data register Port 6 data direction register* Port 6 pull-up setting register Port 7 data register Port 7 data direction register Port 7 pull-up setting register Prohibited area Port-0 pull-up setting register Port-3 pull-up setting register Port-5 pull-up setting register Prohibited area Flash memory control status register Prohibited area Interrupt level setting register1 Interrupt level setting register2 Interrupt level setting register3 Interrupt level setting register4 Interrupt test register
Read/write R/W R/W R/W R/W R/W R/W
Initial value - - - - - 1XX ------00 - - ---000 - - - - - XXX - - ---000 - - ---000
R/W R/W R/W
0000000 0 0000000 0 -------0
R/W
0 0 0 X- - - -
W W W W Not available
1111111 1 1111111 1 1111111 1 1111111 1 ------00
- : Unused, X : Undefined, M : Set using the mask option Note : Do not use prohibited areas. * : No used in MB89N201
21
MB89201 Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage "L" level maximum output current Symbol VCC VI VO IOL Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 Max. VSS + 6.0 VCC + 0.3 VCC + 6.0 15 Unit V V V mA Average value (operating current x operating rate) Pins excluding P40 to P43, P70 to P72 Average value (operating current x operating rate) Pins P40 to P43, P70 to P72
(Vss = 0.0V)
Remarks
IOLAV1 "L" level average output current IOLAV2 "L" level total maximum output current "H" level maximum output current "H" level average output current "H" level total maximum output current Power consumption Operating temperature Storage temperature IOL IOH IOHAV IOH Pd Ta Tstg
4
mA
-40 -55
12 100 -10 -4 -50 200 +85 +150
mA mA mA mA mA mW C C
Pins excluding P60 to P61 Average value (operating current x operating rate)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
22
MB89201 Series
2. Recommended Operating Conditions
Parameter Symbol Value Min. 2.2 Power supply voltage VCC 3.5 2.7 1.5 VIH "H" level input voltage VIHS VIL "L" level input voltage VILS Open-drain output pin application voltage Operating temperature VD Ta VSS - 0.3 VSS - 0.3 -40 0.2 VCC VCC + 0.3 +85 V V C 0.8 VCC VSS - 0.3 VCC + 0.3 0.3 VCC V V 0.7 VCC Max. 5.5 5.5 5.5 5.5 VCC + 0.3 Unit V V V V V MB89201 MB89N201 MB89V201 Retains the RAM state in stop mode P00 to P07, P31, P37, P40 to P43, P50, P60 to P62, P70 to P72 RST, EC, INT20 to INT27, UCK/SCK, INT10 to INT12, P30, P32 to P36, UI/SI P00 to P07, P31, P37, P40 to P43, P50, P60 to P62, P70 to P72 RST, EC, INT20 to INT27, UCK/SCK, INT10 to INT12, P30, P32 to P36, UI/SI P40 to P43, P62, RST
(Vss = 0.0V)
Remarks
Operating Assurance for MB89201 and MB89PV201 6
5.5
Operating Assurance for MB89N201 6
5.5
5
4.5
Analog accuracy assurance range
Operating voltage (V)
5 Operation & analog accuracy assurance range 4
3.5
Operating voltage (V)
4
3.5
Operation assurance range
3
2.7 2.2
3
2 : Area is assured only for the MB89201 1
2
1
0
1
2
3
4
8 5 6 7 Operating Frequency (MHz)
9
10
11
12.5
0
1
2
3
4
8 5 6 7 Operating Frequency (MHz)
9
10
11
12.5
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
23
MB89201 Series
3. DC Characteristics
(VCC = 5.0 V 10%, VSS = 0.0 V, FCH = 12.5 MHz (External clock) , Ta = -40 C to +85 C) Parameter Symbol VIH "H" level input voltage VIHS Pin name
P00 to P07, P31, P37, P40 to P43, P50, P60 to P62, P70 to P72 P30, P32 to P36, RST UCK/SCK, UI/SI, EC, INT20 to INT27, INT10 to INT12 P00 to P07, P31, P37, P40 to P43, P50, P60 to P62, P70 to P72 P30, P32 to P36, RST, UCK/SCK, UI/SI, EC, INT20 to INT27, INT10 to INT12
Condition
Value Min. 0.7 VCC
Typ.
Max. VCC + 0.3
Unit
Remarks
V
0.8 VCC
VCC + 0.3
V
VIL "L" level input voltage VILS Open-drain output pin application voltage "H" level output voltage "L" level output voltage Input leakage current Pull-up resistance
VSS - 0.3
0.3 VCC
V
VSS - 0.3
0.2 VCC
V
VD
P40 to P43, RST/P62
VSS - 0.3
VCC + 0.3
V
VOH VOL1 VOL2 ILI
P00 to P07, P30 to P37, P40 to P43, P50, P70 to P72 P00 to P07, P30 to P37, P50, RST/P62 P40 to P43, P70 to P72 P00 to P07, P30 to P37, P40 to P43, P50 , P60 to P61, RST/P62, P70 to P72 P00 to P07, P30 to P37,
IOH = -4.0 mA IOL = 4.0 mA IOL = 12.0 mA 0.45 V < VI < VCC VI = 0.0 V When A/D converter stops When A/D converter starts When A/D converter stops When A/D converter stops
4.0

0.4 0.4 5
V V V A Without pull-up resistor
RPULL P50, RST/P62, P70 to P72
Normal operation mode (External clock, highest gear speed) VCC Sleep mode (External clock, highest gear speed) Stop mode Ta = +25 C (External clock) Other than VCC, VSS
25
50 8 6 10 8 4 3 10
100 12 9 15 12 6 5 1 10
k mA MB89201 mA MB89N201 mA MB89201 mA MB89N201 mA MB89201 mA MB89N201 A A pF
MB89201 MB89N201 MB89N201
ICC Power supply current ICCS
ICCH Input capacitance CIN
24
MB89201 Series
4. AC Characteristics
(VSS = 0.0 V, Ta = -40 C to +85 C) Parameter RST "L" pulse width Internal reset pulse extension tHCYL : 1 oscillating clock cycle time Symbol tZLZH tirst Condition Value Min. 45 48 tHCYL Max. Unit ns ns Remarks
(1) Reset Timing
tZLZH
0.8 VCC 0.2 VCC
RST
0.2 VCC
Internal reset signal
tirst
Notes: *When the power-on reset option is not on, leave the external reset on until oscillation becomes stable. *If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST). (2) Power-on Reset (VSS = 0.0 V, Ta = -40 C to +85 C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Condition Value Min. 1 Max. 50 Unit ms ms Due to repeated operations Remarks
tR 2.0 V
tOFF
VCC
0.2 V
0.2 V
0.2 V
Note : The supply voltage must be set to the minimum value required for operation within the prescribed default oscillation settling time. Note : For the product that select P62 instead of RST pin by mask option, the only way to initialize the device is by power on reset. If the power supply rise / cutoff time does not meet the specifications, then power on reset cannot be generated, and the device become unusable. 25
MB89201 Series
(3) Clock Timing (VSS = 0.0 V, Ta = -40C to +85C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Symbol FCH tXCYL tWH tWL tCR tCF Condition Value Min. 1 80 20 Max. 12.5 1000 10 Unit MHz ns ns ns Remarks
* X0 and X1 Timing and Conditions
tXCYL tWH tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL
X0
* Main Clock Conditions
When a crystal or ceramic resonator is used When an exernal clock is used
X0
X1
X0
X1 open
(4) Instruction Cycle. Parameter Instruction cycle (minimum execution time) Symbol tINST Value (typical) 4/FCH, 8/FCH, 16/FCH, 64/FCH Unit s Remarks tINST = 0.32 s when operating at FCH = 12.5 MHz (4/FCH)
26
MB89201 Series
(6) Peripheral Input Timing (VCC = 5.0 V 10%, VSS = 0.0 V, Ta = -40 C to +85 C) Parameter Peripheral input "H" pulse width Peripheral input "L" pulse width Symbol tILIH tIHIL Pin name INT10 to INT12, INT20 to INT27, EC Value Min. 2 tINST* 2 tINST* Max. Unit s s Remarks
* : For information on tINST see " (4) Instruction Cycle".
tILIH
tIHIL
INT10 to INT12, INT20 to INT27, EC
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
(VCC = 5.0 V 10%, VSS = 0.0 V, Ta = -40 C to +85 C) Parameter Peripheral input "H" noise limit Symbol tIHNC Pin name P00 to P07, P30 to P37, P40 to P43, P50, P60 to P62, P70 to P72, RST, EC, INT20 to INT27, INT10 to INT12 Value Min. Typ. 45 Max. Unit ns Remarks
Peripheral input "L" noise limit
tILNC
45
ns
tIHNC
tILNC
INT10 to INT12, EC
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
27
MB89201 Series
(7) UART, Serial I/O Timing (VCC = 5.0 V 10%, VSS = 0.0 V, Ta = -40 C to +85 C) Parameter Serial clock cycle time UCK/SCK SO time Valid SI UCK/SCK UCK/SCK Valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width UCK/SCK SO time Valid SI UCK/SCK UCK/SCK Valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK/SCK UCK/SCK, SO Internal shift UCK/SCK, SI clock mode UCK/SCK, SI UCK/SCK UCK/SCK UCK/SCK, SO UCK/SCK, SI UCK/SCK, SI External shift clock mode Condition Value Min. 2 tINST* -200 1/2 tINST* 1/2 tINST* tINST* tINST* 0 1/2 tINST* 1/2 tINST* Max. 200 200 Unit Remarks s ns s s s s ns s s
* : For information on tinst, see " (4) Instruction Cycle". * Internal Shift Clock Mode
tSCYC 2.4 V
UCK/SCK
0.8 V tSLOV
0.8 V
SO
2.4 V 0.8 V tIVSH tSHIX
SI
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
* External Shift Clock Mode
tSLSH tSHSL 0.8 VCC 0.8 VCC
UCK/SCK
0.2 VCC
0.2 VCC tSLOV
SO
2.4 V 0.8 V tIVSH tSHIX
SI
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
28
MB89201 Series
5. A/D Converter
(VSS = 0.0 V, Ta = -40 C to +85 C) Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage A/D mode conversion time Analog port input current Analog input voltage range Power supply voltage for A/D accuracy assurance VOT VFST IAIN VCC Symbol Value Min. -5.0 -3.0 -2.5 VSS - 3.5 LSB VCC - 6.5 LSB 0 4.5 3.5 Typ. VSS + 0.5 LSB VCC - 1.5 LSB Max. 10 +5.0 +3.0 +2.5 VSS + 4.5 LSB VCC + 2.0 LSB 38 tINST* 10 VCC 5.5 5.5 Unit bit LSB LSB LSB V V s A V V V
MB89201 / MB89V201 MB89N201
(1) A/D Converter Electrical Characteristics
Remarks
* : For information on tinst, see " (4) Instruction Cycle" in "4. AC Characteristics." (2) A/D Converter Glossary * Resolution Analog changes that are identifiable with the A/D converter When the number of bits is 10, analog voltage can be divided into 210 = 1024. * Linearity error (unit : LSB) The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1111" "11 1111 1110") from actual conversion characteristics * Differential linearity error (unit : LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value * Total error (unit : LSB) The difference between theoretical and actual conversion values
Theoretical I/O characteristics
3FF 3FE 3FD 1.5 LSB VFST
3FF 3FE 3FD Actual conversion value {1 LSB x N + 0.5 LSB}
Total error
Digital output
004 003 002 001 0.5 LSB AVSS VCC VOT 1 LSB
Digital output
004 003 002 001 AVSS VNT Actual conversion value Theoretical value VCC
Analog input
Analog input
1 LSB =
VFST - VOT 1022
(V)
Total error of digital output N =
VNT - {1 LSB x N + 0.5 LSB} 1 LSB 29
MB89201 Series
Zero transition error
004 Actual conversion value 003 3FF
Full-scale transition error
Theoretical value
Actual conversion value
Digital output
Digital output
3FE VFST (Measured value) Actual conversion value
002 Theoretical conversion value 001 VOT (Measured value) AVSS Actual conversion value
3FD
3FC
VCC
Analog input
Analog input
Linearity error
3FF 3FE Actual conversion value {1 LSB x N + VOT} N+1
Differential linearity error
Theoretical conversion value
Digital output
3FD
Actual conversion value
Digital output
VFST (Measured value) VNT 004 003 002 001 AVSS Theoretical conversion value VOT (Measured value) VCC Actual conversion value
V (N + 1) T
N
N-1
VNT Actual conversion value
N-2 AVSS
VCC
Analog input
Analog input
Linearity error of digital output N =
VNT - {1 LSB x N + VOT} 1 LSB V (N + 1) T - VNT -1 1 LSB
Differential linearity of error digital output N =
30
MB89201 Series
(3) Notes on Using A/D Converter * Input impedance of the analog input pins The A/D converter used for the MB89201 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for 16 instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 4 k) . Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 F for the analog input pin. * Analog Input Equivalent Circuit
Analog input pin Sample hold circuit
Comparator R C
If the analog input impedance is higher than 4 k, it is recommended to connect an external capacitor of approx. 0.1 F. MB89201 R = approx. 2.2 k, C = approx. 45 pF MB89N201 R = approx. 3.2 k, C = approx. 30 pF
Close for 16 instruction cycles after activating A/D conversion Analog channel selector
* Error The smaller the | VCC - AVSS |, the greater the error would become relatively.
31
MB89201 Series
EXAMPLE CHARACTERISTICS
* Power supply current MB89201/MB89N201 : 8 MHz ( when external clock are used) MB89201 Normal operation mode (ICC1 - VCC, ICC2 - VCC)
ICC (mA) (FCH = 8 MHz, Ta = +25 C) 8
MB89N201 Normal operation mode (ICC1 - VCC, ICC2 - VCC)
ICC (mA) (FCH = 8 MHz, Ta = +25 C) 8
2
6 ICC1 (gear : 4 divide) 4
6
4 ICC1 (gear : 4 divide)
1
2
ICC2 (gear : 64 divide)
2 ICC2 (gear : 64 divide)
0 3 4 5 VCC (V) 6
0 3 4 5 VCC (V) 6
0
MB89201 Sleep mode (ICCs1 - VCC, ICCs2 - VCC)
ICCs (mA) (FCH = 8 MHz, Ta = +25 C) 4
MB89N201 Sleep mode (ICCs1 - VCC, ICCs2 - VCC)
ICCs (mA) (FCH = 8 MHz, Ta = +25 C) 4
3
3
2
ICCs1 (gear : 4 divide)
2 ICCs1 (gear : 4 divide) 1
1 ICCs2 (gear : 64 divide) 0 3 4 5 VCC (V) 6
ICCs2 (gear : 64 divide) 0 3 4 5 VCC (V) 6
32
MB89201 Series
* MB89201/MB89N201 : 4 MHz (when external clock are used) MB89201 Normal operation mode (ICC1 - VCC, ICC2 - VCC)
ICC (mA) (FCH = 4 MHz, Ta = +25 C) 4
MB89N201 Normal operation mode (ICC1 - VCC, ICC2 - VCC)
ICC (mA) (FCH = 4 MHz, Ta = +25 C) 4
3
ICC1 (gear : 4 divide)
3
2
2
ICC1 (gear : 4 divide)
1 ICC2 (gear : 64 divide) 0 3 4 5 VCC (V) 6
1 ICC2 (gear : 64 divide) 3 4 5 VCC (V) 6
0
MB89201 MB89N201 Seep mode Seep mode (ICCs1 - VCC, ICCs2 - VCC) (ICCs1 - VCC, ICCs2 - VCC)
ICCs (mA) (FCH = 4 MHz, Ta = +25 C) 4 ICCs (mA) (FCH = 4 MHz, Ta = +25 C) 4
3
3
2
2
1
ICCs1 (gear : 4 divide) ICCs2 (gear : 64 divide) 4 5 6 VCC (V)
1
ICCs1 (gear : 4 divide) ICCs2 (gear : 64 divide) 3 4 5 VCC (V) 6
0 3
0
33
MB89201 Series
* MB89201/MB89N201 : 12.5 MHz (when external clock is used) MB89201 Normal operation mode (ICC1 - VCC, ICC2 - VCC)
ICC (mA) (FCH = 12.5 MHz, Ta = +25 C) 8
MB89201 Normal operation mode (ICCs1 - VCC, ICCs2 - VCC)
ICCs (mA) (FCH = 12.5 MHz, Ta = +25 C) 4
MB89201 Normal operation mode (ICCh - VCC)
ICCh (A) (FCH = 12.5 MHz, Ta = +25 C) 0.4
6 ICC1 (gear : 4 divide) 4
3
0.3
2 ICCs1 (gear : 4 divide)
0.2
2
ICC2 (gear : 64 divide)
1
0.1
ICCs2 (gear : 64 divide) 0 0 3 4 5 VCC (V) 6 0 0 3 4 5 VCC (V) 6 0 0 3 4 5 VCC (V) 6
MB89201 Stop mode (ICCh - oC)
ICCh (A) 10 (FCH = 12.5 MHz, VCC = 5.5 V) ICCh (A) 10
MB89N201 Stop mode (ICCh - oC)
(FCH = 12.5 MHz, VCC = 5.5 V)
8
8
6
6
4
4
2
2
0 -50
-25
0
25
50
75
100
125
150
0 -50
-25
0
25
50
75
100
125
150
Temperature (C)
Temperature (C)
34
MB89201 Series
(2) "L" level output voltage VOL vs. IOL1
VOL (V) 0.6 VCC = 2.0 V VOL (V) 0.6
VOL vs. IOL2
VCC = 2.0 V
0.5 VCC = 2.5 V 0.4 VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V
0.5 VCC = 2.5 V 0.4 VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V
0.3
0.3
0.2
0.2
0.1
0.1
0.0 1 2 3 4 5 6 IOL1 (mA)
0.0 4 6 8 10 12 14 16 IOL2 (mA)
(3) "H" level output voltage (VCC - VOH) vs. IOH
VCC - VOH (V) 0.8 0.7 VCC = 2.5 V 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -1 VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V VCC = 2.0 V
-2
-3
-4
-5
-6
IOH (mA)
35
MB89201 Series
MASK OPTIONS
No Part number Specifying procedure Selection of initial value of main clock oscillation settling time* (with FCH = 12.5 MHz) 01 : 214/FCH (Approx.1.31 ms) 10 : 217/FCH (Approx.10.5 ms) 11 : 218/FCH (Approx.21.0 ms) Reset pin output** With reset output Without reset output External Reset pin RST external reset pin is used P62 I/O pin is used MB89201
Specify when ordering masking
MB89N201
MB89V201
Specify by part number
1
Selectable
Fixed to 218/FCH
Fixed to 218/FCH
2
Selectable
With reset output
With reset output
3
Selectable
Selectable
Selectable by SEL input
FCH : Main clock oscillation frequency * : Initial value to which the oscillation settling time bit (SYCC : WT1, WT0) in the system clock control register is set ** : Reset pin output is available only if external reset pin option choose to use RST external reset pin
ORDERING INFORMATION
Part number MB89201-PSH MB89N201-PSH MB89N201A-PSH MB89V201-CFV Package 32-pin Plastic SHDIP (DIP-32P-M06) 32-pin Plastic SHDIP (DIP-32P-M06) 32-pin Plastic SHDIP (DIP-32P-M06) 64-pin Plastic SHDIP (DIP-64P-M01) P62 I/O pin is used RST external reset pin is used Remarks
36
MB89201 Series
PACKAGE DIMENSIONS
32-pin plastic SHDIP (DIP-32P-M06)
8.89 28.00
+0.20 -0.30
+0.25 -0.25
4.70
+0.70 -0.20
DIP-32P-M06 D32018S-c
1.02
+0.30 -0.20
3.30
1.27MAX.
0.48
+0.08 -0.12
+0.20 -0.30
Dimensions in mm (inches) (Continued)
37
MB89201 Series
(Continued) 64pin plastic SHDIP (DIP-64P-M01)
58.00 -0.55 2.283 -.022
+0.22
+.009
INDEX-1 17.000.25 (.669.010) INDEX-2
4.95 -0.20 .195 -.008
+0.70 +.028
0.70 -0.19 .028 -.007
+0.50 +.020
3.30 -0.30 .130
+0.20 +.008 -.012 +0.40 -0.20 +.016 -.008
0.270.10 (.011.004) 1.378 .0543 1.778(.0700) 0.470.10 (.019.004) 0.25(.010)
M
19.05(.750) 0~15
1.00 -0 .039
+0.50 +.020 -.0
C
2001 FUJITSU LIMITED D64001S-c-4-5
Dimensions in mm (inches)
38
MB89201 Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ F0207 FUJITSU LIMITED Printed in Japan
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
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